Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze

28 files changed, 109 insertions, 384 deletions

diff --git a/board/avnet/fx12mm/Kconfig b/board/avnet/fx12mm/Kconfig
deleted file mode 100644
index 0b67ebde93b..00000000000
--- a/board/avnet/fx12mm/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_FX12MM
-
-config SYS_BOARD
-	default "fx12mm"
-
-config SYS_VENDOR
-	default "avnet"
-
-config SYS_CONFIG_NAME
-	default "fx12mm"
-
-endif
diff --git a/board/avnet/fx12mm/MAINTAINERS b/board/avnet/fx12mm/MAINTAINERS
deleted file mode 100644
index c92e258df95..00000000000
--- a/board/avnet/fx12mm/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-FX12MM BOARD
-M:	Georg Schardt <schardt@team-ctech.de>
-S:	Maintained
-F:	board/avnet/fx12mm/
-F:	include/configs/fx12mm.h
-F:	configs/fx12mm_defconfig
-F:	configs/fx12mm_flash_defconfig
diff --git a/board/avnet/fx12mm/Makefile b/board/avnet/fx12mm/Makefile
deleted file mode 100644
index 618b42f8917..00000000000
--- a/board/avnet/fx12mm/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2008
-# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es
-# This work has been supported by: Qtechnology http://qtec.com/
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	+= fx12mm.o
-
-include $(srctree)/board/xilinx/ppc405-generic/Makefile
diff --git a/board/avnet/fx12mm/fx12mm.c b/board/avnet/fx12mm/fx12mm.c
deleted file mode 100644
index 92e1cfb75f3..00000000000
--- a/board/avnet/fx12mm/fx12mm.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * (C) Copyright 2008
- *
- * Author: Xilinx Inc.
- *
- * Modified by:
- *  Georg Schardt <schardt@team-ctech.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/processor.h>
-
-int checkboard(void)
-{
-	char buf[64];
-	int i;
-	int l = getenv_f("serial#", buf, sizeof(buf));
-
-	if (l < 0) {
-		printf("Avnet Virtex4 FX12 with no serial #");
-	} else {
-		printf("Avnet Virtex4 FX12 Minimodul # ");
-		for (i = 0; i < l; ++i) {
-			if (buf[i] == ' ')
-				break;
-			putc(buf[i]);
-		}
-	}
-	putc('\n');
-	return 0;
-}
diff --git a/board/avnet/fx12mm/xparameters.h b/board/avnet/fx12mm/xparameters.h
deleted file mode 100644
index 94f682f8ecc..00000000000
--- a/board/avnet/fx12mm/xparameters.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * (C) Copyright 2008
- *
- * Georg Schardt <schardt@team-ctech.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * CAUTION: This file is based on the xparameters.h automatically
- * generated by libgen. Version: Xilinx EDK 10.1.02 Build EDK_K_SP2.5
- */
-
-#ifndef __XPARAMETER_H__
-#define __XPARAMETER_H__
-
-/* RS232 */
-#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
-#define XPAR_UARTNS550_0_BASEADDR 0x83E00000
-
-
-/* INT_C */
-#define XPAR_XPS_INTC_0_DEVICE_ID 0
-#define XPAR_XPS_INTC_0_BASEADDR 0x81800000
-#define XPAR_INTC_MAX_NUM_INTR_INPUTS 2
-
-/* CPU core clock */
-#define XPAR_CORE_CLOCK_FREQ_HZ 300000000
-#define XPAR_PLB_CLOCK_FREQ_HZ  100000000
-
-/* RAM */
-#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
-
-/* FLASH */
-#define XPAR_FLASH_MEM0_BASEADDR 0xFFC00000
-
-#endif
diff --git a/board/avnet/v5fx30teval/Kconfig b/board/avnet/v5fx30teval/Kconfig
deleted file mode 100644
index 079387b707a..00000000000
--- a/board/avnet/v5fx30teval/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_V5FX30TEVAL
-
-config SYS_BOARD
-	default "v5fx30teval"
-
-config SYS_VENDOR
-	default "avnet"
-
-config SYS_CONFIG_NAME
-	default "v5fx30teval"
-
-endif
diff --git a/board/avnet/v5fx30teval/MAINTAINERS b/board/avnet/v5fx30teval/MAINTAINERS
deleted file mode 100644
index 91dde7a5c8f..00000000000
--- a/board/avnet/v5fx30teval/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-V5FX30TEVAL BOARD
-M:	Ricardo Ribalda <ricardo.ribalda@uam.es>
-S:	Maintained
-F:	board/avnet/v5fx30teval/
-F:	include/configs/v5fx30teval.h
-F:	configs/v5fx30teval_defconfig
-F:	configs/v5fx30teval_flash_defconfig
diff --git a/board/avnet/v5fx30teval/Makefile b/board/avnet/v5fx30teval/Makefile
deleted file mode 100644
index 8c41af02d4f..00000000000
--- a/board/avnet/v5fx30teval/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2008
-# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es
-# This work has been supported by: Qtechnology http://qtec.com/
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	+= v5fx30teval.o
-
-include $(srctree)/board/xilinx/ppc440-generic/Makefile
diff --git a/board/avnet/v5fx30teval/v5fx30teval.c b/board/avnet/v5fx30teval/v5fx30teval.c
deleted file mode 100644
index 68b0eb959de..00000000000
--- a/board/avnet/v5fx30teval/v5fx30teval.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
- * This work has been supported by: QTechnology  http://qtec.com/
- * SPDX-License-Identifier:	GPL-2.0+
-*/
-
-#include <config.h>
-#include <common.h>
-#include <asm/processor.h>
-
-
-int checkboard(void)
-{
-	puts("Avnet Virtex 5 FX30 Evaluation Board\n");
-	return 0;
-}
diff --git a/board/avnet/v5fx30teval/xparameters.h b/board/avnet/v5fx30teval/xparameters.h
deleted file mode 100644
index 95b8c285ad1..00000000000
--- a/board/avnet/v5fx30teval/xparameters.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
- * This work has been supported by: QTechnology  http://qtec.com/
- * based on xparameters.h by Xilinx
- *
- * SPDX-License-Identifier:	GPL-2.0+
-*/
-
-#ifndef XPARAMETER_H
-#define XPARAMETER_H
-
-#define XPAR_DDR2_SDRAM_MEM_BASEADDR	0x00000000
-#define XPAR_INTC_0_BASEADDR		0x81800000
-#define XPAR_UARTLITE_0_BASEADDR	0x84000000
-#define XPAR_FLASH_MEM0_BASEADDR	0xFF000000
-#define XPAR_PLB_CLOCK_FREQ_HZ		100000000
-#define XPAR_CORE_CLOCK_FREQ_HZ		400000000
-#define XPAR_INTC_MAX_NUM_INTR_INPUTS	13
-#define XPAR_UARTLITE_0_BAUDRATE	9600
-
-#endif
diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c
index dfa62932222..ccd4ec955b5 100644
--- a/board/xilinx/microblaze-generic/microblaze-generic.c
+++ b/board/xilinx/microblaze-generic/microblaze-generic.c
@@ -12,7 +12,6 @@
 #include <common.h>
 #include <config.h>
 #include <fdtdec.h>
-#include <netdev.h>
 #include <asm/processor.h>
 #include <asm/microblaze_intc.h>
 #include <asm/asm.h>
@@ -24,7 +23,6 @@ DECLARE_GLOBAL_DATA_PTR;
 static int reset_pin = -1;
 #endif
 
-#if CONFIG_IS_ENABLED(OF_CONTROL)
 ulong ram_base;
 
 void dram_init_banksize(void)
@@ -58,14 +56,6 @@ int dram_init(void)
 
 	return 0;
 };
-#else
-int dram_init(void)
-{
-	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
-
-	return 0;
-}
-#endif
 
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
@@ -86,7 +76,7 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	return 0;
 }
 
-int gpio_init (void)
+static int gpio_init(void)
 {
 #ifdef CONFIG_XILINX_GPIO
 	reset_pin = gpio_alloc(CONFIG_SYS_GPIO_0_ADDR, "reset", 1);
@@ -96,32 +86,9 @@ int gpio_init (void)
 	return 0;
 }
 
-void board_init(void)
+int board_late_init(void)
 {
 	gpio_init();
-}
 
-int board_eth_init(bd_t *bis)
-{
-	int ret = 0;
-
-#ifdef CONFIG_XILINX_AXIEMAC
-	ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
-						XILINX_AXIDMA_BASEADDR);
-#endif
-
-#if defined(CONFIG_XILINX_EMACLITE) && defined(XILINX_EMACLITE_BASEADDR)
-	u32 txpp = 0;
-	u32 rxpp = 0;
-# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
-	txpp = 1;
-# endif
-# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
-	rxpp = 1;
-# endif
-	ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
-			txpp, rxpp);
-#endif
-
-	return ret;
+	return 0;
 }
diff --git a/board/xilinx/microblaze-generic/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h
index 8ba146cb88d..ccb528ed926 100644
--- a/board/xilinx/microblaze-generic/xparameters.h
+++ b/board/xilinx/microblaze-generic/xparameters.h
@@ -28,15 +28,6 @@
 #define XILINX_TIMER_BASEADDR	0x41c00000
 #define XILINX_TIMER_IRQ	0
 
-/* Uart pheriphery is RS232_Uart */
-#define XILINX_UARTLITE_BASEADDR	0x40600000
-#define XILINX_UARTLITE_BAUDRATE	115200
-
-/* IIC pheriphery is IIC_EEPROM */
-#define XILINX_IIC_0_BASEADDR	0x40800000
-#define XILINX_IIC_0_FREQ	100000
-#define XILINX_IIC_0_BIT	0
-
 /* GPIO is LEDs_4Bit*/
 #define XILINX_GPIO_BASEADDR	0x40000000
 
@@ -44,18 +35,6 @@
 #define XILINX_FLASH_START	0x2c000000
 #define XILINX_FLASH_SIZE	0x00800000
 
-/* Main Memory is DDR_SDRAM_64Mx32 */
-#define XILINX_RAM_START	0x28000000
-#define XILINX_RAM_SIZE	0x04000000
-
-/* Sysace Controller is SysACE_CompactFlash */
-#define XILINX_SYSACE_BASEADDR	0x41800000
-#define XILINX_SYSACE_HIGHADDR	0x4180ffff
-#define XILINX_SYSACE_MEM_WIDTH	16
-
-/* Ethernet controller is Ethernet_MAC */
-#define XILINX_EMACLITE_BASEADDR       0x40C00000
-
 /* Watchdog IP is wxi_timebase_wdt_0 */
 #define XILINX_WATCHDOG_BASEADDR	0x50000000
 #define XILINX_WATCHDOG_IRQ		1
diff --git a/board/xilinx/ml507/Kconfig b/board/xilinx/ml507/Kconfig
deleted file mode 100644
index d580a7beafe..00000000000
--- a/board/xilinx/ml507/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_ML507
-
-config SYS_BOARD
-	default "ml507"
-
-config SYS_VENDOR
-	default "xilinx"
-
-config SYS_CONFIG_NAME
-	default "ml507"
-
-endif
diff --git a/board/xilinx/ml507/MAINTAINERS b/board/xilinx/ml507/MAINTAINERS
deleted file mode 100644
index 8b40f445008..00000000000
--- a/board/xilinx/ml507/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-ML507 BOARD
-M:	Ricardo Ribalda <ricardo.ribalda@uam.es>
-S:	Maintained
-F:	board/xilinx/ml507/
-F:	include/configs/ml507.h
-F:	configs/ml507_defconfig
-F:	configs/ml507_flash_defconfig
diff --git a/board/xilinx/ml507/Makefile b/board/xilinx/ml507/Makefile
deleted file mode 100644
index 9a3809f3c06..00000000000
--- a/board/xilinx/ml507/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2008
-# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es
-# This work has been supported by: Qtechnology http://qtec.com/
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	+= ml507.o
-
-include $(srctree)/board/xilinx/ppc440-generic/Makefile
diff --git a/board/xilinx/ml507/ml507.c b/board/xilinx/ml507/ml507.c
deleted file mode 100644
index 83b764b7337..00000000000
--- a/board/xilinx/ml507/ml507.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
- * This work has been supported by: QTechnology  http://qtec.com/
- * SPDX-License-Identifier:	GPL-2.0+
-*/
-
-#include <config.h>
-#include <common.h>
-#include <asm/processor.h>
-
-
-int checkboard(void)
-{
-	puts("Xilinx ML507 Board\n");
-	return 0;
-}
diff --git a/board/xilinx/ml507/xparameters.h b/board/xilinx/ml507/xparameters.h
deleted file mode 100644
index e30e592bbe1..00000000000
--- a/board/xilinx/ml507/xparameters.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
- * This work has been supported by: QTechnology  http://qtec.com/
- * based on xparameters-ml507.h by Xilinx
- *
- * SPDX-License-Identifier:	GPL-2.0+
-*/
-
-#ifndef XPARAMETER_H
-#define XPARAMETER_H
-
-#define XPAR_DDR2_SDRAM_MEM_BASEADDR	0x00000000
-#define XPAR_IIC_EEPROM_BASEADDR	0x81600000
-#define XPAR_INTC_0_BASEADDR		0x81800000
-#define XPAR_UARTLITE_0_BASEADDR	0x84000000
-#define XPAR_FLASH_MEM0_BASEADDR	0xFE000000
-#define XPAR_PLB_CLOCK_FREQ_HZ		100000000
-#define XPAR_CORE_CLOCK_FREQ_HZ		400000000
-#define XPAR_INTC_MAX_NUM_INTR_INPUTS	13
-#define XPAR_UARTLITE_0_BAUDRATE	9600
-
-#endif
diff --git a/board/xilinx/ppc405-generic/MAINTAINERS b/board/xilinx/ppc405-generic/MAINTAINERS
index 2b0c98dc8b7..ba48f50c29b 100644
--- a/board/xilinx/ppc405-generic/MAINTAINERS
+++ b/board/xilinx/ppc405-generic/MAINTAINERS
@@ -1,5 +1,5 @@
 PPC405-GENERIC BOARD
-M:	Ricardo Ribalda <ricardo.ribalda@uam.es>
+M:	Ricardo Ribalda <ricardo.ribalda@gmail.com>
 S:	Maintained
 F:	board/xilinx/ppc405-generic/
 F:	include/configs/xilinx-ppc405-generic.h
diff --git a/board/xilinx/ppc405-generic/Makefile b/board/xilinx/ppc405-generic/Makefile
index c9da8706574..2800f686264 100644
--- a/board/xilinx/ppc405-generic/Makefile
+++ b/board/xilinx/ppc405-generic/Makefile
@@ -3,10 +3,10 @@
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # (C) Copyright 2008
-# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
 # Work supported by Qtechnology http://www.qtec.com
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y	+= ../../xilinx/ppc405-generic/xilinx_ppc405_generic.o
+obj-y	+= xilinx_ppc405_generic.o
diff --git a/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c b/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c
index e3dd468f1eb..3729f07624a 100644
--- a/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c
+++ b/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c
@@ -1,6 +1,6 @@
 /*
  * (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
  * This work has been supported by: QTechnology  http://qtec.com/
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -10,39 +10,32 @@
 #include <common.h>
 #include <asm/processor.h>
 
-ulong __get_PCI_freq(void)
+ulong get_PCI_freq(void)
 {
 	return 0;
 }
 
-ulong get_PCI_freq(void) __attribute__((weak, alias("__get_PCI_freq")));
-
-int __board_pre_init(void)
-{
-	return 0;
-}
-int board_pre_init(void) __attribute__((weak, alias("__board_pre_init")));
-
-int __checkboard(void)
+int checkboard(void)
 {
 	puts("Xilinx PPC405 Generic Board\n");
 	return 0;
 }
-int checkboard(void) __attribute__((weak, alias("__checkboard")));
 
-phys_size_t __initdram(int board_type)
+phys_size_t initdram(int board_type)
 {
 	return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
 			    CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024);
 }
-phys_size_t initdram(int) __attribute__((weak, alias("__initdram")));
 
-void __get_sys_info(sys_info_t *sysInfo)
+void get_sys_info(sys_info_t *sys_info)
 {
-	sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
-	sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
-	sysInfo->freqPCI = 0;
+	sys_info->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
+	sys_info->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
+	sys_info->freqPCI = 0;
 
 	return;
 }
-void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info")));
+
+int get_serial_clock(void){
+	return XPAR_UARTNS550_0_CLOCK_FREQ_HZ;
+}
diff --git a/board/xilinx/ppc405-generic/xparameters.h b/board/xilinx/ppc405-generic/xparameters.h
index f0ff78fca56..c3df9e51091 100644
--- a/board/xilinx/ppc405-generic/xparameters.h
+++ b/board/xilinx/ppc405-generic/xparameters.h
@@ -1,6 +1,6 @@
 /*
  * (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
  * This work has been supported by: QTechnology  http://qtec.com/
  * based on xparameters-ml507.h by Xilinx
  *
@@ -14,12 +14,11 @@
 #define XPAR_IIC_EEPROM_BASEADDR	0x81600000
 #define XPAR_INTC_0_BASEADDR		0x81800000
 #define XPAR_SPI_0_BASEADDR             0x83400000
-#define XPAR_UARTLITE_0_BASEADDR	0x84000000
 #define XPAR_FLASH_MEM0_BASEADDR	0xFE000000
 #define XPAR_PLB_CLOCK_FREQ_HZ		100000000
 #define XPAR_CORE_CLOCK_FREQ_HZ		400000000
-#define XPAR_INTC_MAX_NUM_INTR_INPUTS	13
-#define XPAR_UARTLITE_0_BAUDRATE	9600
+#define XPAR_INTC_MAX_NUM_INTR_INPUTS	32
 #define XPAR_SPI_0_NUM_TRANSFER_BITS	8
+#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ	100000000
 
 #endif
diff --git a/board/xilinx/ppc440-generic/MAINTAINERS b/board/xilinx/ppc440-generic/MAINTAINERS
index 2d0b11af914..0258c8204ae 100644
--- a/board/xilinx/ppc440-generic/MAINTAINERS
+++ b/board/xilinx/ppc440-generic/MAINTAINERS
@@ -1,5 +1,5 @@
 PPC440-GENERIC BOARD
-M:	Ricardo Ribalda <ricardo.ribalda@uam.es>
+M:	Ricardo Ribalda <ricardo.ribalda@gmail.com>
 S:	Maintained
 F:	board/xilinx/ppc440-generic/
 F:	include/configs/xilinx-ppc440-generic.h
diff --git a/board/xilinx/ppc440-generic/Makefile b/board/xilinx/ppc440-generic/Makefile
index 0acd95d6e4e..4d5f41029ac 100644
--- a/board/xilinx/ppc440-generic/Makefile
+++ b/board/xilinx/ppc440-generic/Makefile
@@ -3,11 +3,11 @@
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # (C) Copyright 2008
-# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
 # Work supported by Qtechnology http://www.qtec.com
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y	+= ../../xilinx/ppc440-generic/xilinx_ppc440_generic.o
-extra-y 	+= ../../xilinx/ppc440-generic/init.o
+obj-y	+= xilinx_ppc440_generic.o
+extra-y += init.o
diff --git a/board/xilinx/ppc440-generic/init.S b/board/xilinx/ppc440-generic/init.S
index 4598a376843..f9ff35f51b7 100644
--- a/board/xilinx/ppc440-generic/init.S
+++ b/board/xilinx/ppc440-generic/init.S
@@ -1,6 +1,6 @@
 /*
  *  (C) Copyright 2008
- *  Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ *  Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
  *  This work has been supported by: QTechnology  http://qtec.com/
  *
  * SPDX-License-Identifier:	GPL-2.0+
diff --git a/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c b/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c
index 74df2f4ff78..d8233529304 100644
--- a/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c
+++ b/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c
@@ -1,6 +1,6 @@
 /*
  * (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
  * This work has been supported by: QTechnology  http://qtec.com/
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -8,34 +8,51 @@
 
 #include <config.h>
 #include <common.h>
+#include <netdev.h>
 #include <asm/processor.h>
 
-int __board_pre_init(void)
-{
-	return 0;
-}
-int board_pre_init(void) __attribute__((weak, alias("__board_pre_init")));
-
-int __checkboard(void)
+int checkboard(void)
 {
 	puts("Xilinx PPC440 Generic Board\n");
 	return 0;
 }
-int checkboard(void) __attribute__((weak, alias("__checkboard")));
 
-phys_size_t __initdram(int board_type)
+phys_size_t initdram(int board_type)
 {
 	return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
 			    CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024);
 }
-phys_size_t initdram(int) __attribute__((weak, alias("__initdram")));
 
-void __get_sys_info(sys_info_t *sysInfo)
+void get_sys_info(sys_info_t *sys_info)
 {
-	sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
-	sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
-	sysInfo->freqPCI = 0;
+	sys_info->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
+	sys_info->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
+	sys_info->freqPCI = 0;
 
 	return;
 }
-void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info")));
+
+int get_serial_clock(void){
+	return XPAR_UARTNS550_0_CLOCK_FREQ_HZ;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int ret = 0;
+
+	puts("Init xilinx temac\n");
+#ifdef XPAR_LLTEMAC_0_BASEADDR
+	ret |= xilinx_ll_temac_eth_init(bis, XPAR_LLTEMAC_0_BASEADDR,
+			XILINX_LL_TEMAC_M_SDMA_DCR | XILINX_LL_TEMAC_M_SDMA_PLB,
+			XPAR_LLTEMAC_0_LLINK_CONNECTED_BASEADDR);
+
+#endif
+
+#ifdef XPAR_LLTEMAC_1_BASEADDR
+	ret |= xilinx_ll_temac_eth_init(bis, XPAR_LLTEMAC_1_BASEADDR,
+			XILINX_LL_TEMAC_M_SDMA_DCR | XILINX_LL_TEMAC_M_SDMA_PLB,
+			XPAR_LLTEMAC_1_LLINK_CONNECTED_BASEADDR);
+#endif
+
+	return ret;
+}
diff --git a/board/xilinx/ppc440-generic/xparameters.h b/board/xilinx/ppc440-generic/xparameters.h
index e30e592bbe1..b45a6a1d766 100644
--- a/board/xilinx/ppc440-generic/xparameters.h
+++ b/board/xilinx/ppc440-generic/xparameters.h
@@ -1,6 +1,6 @@
 /*
  * (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
  * This work has been supported by: QTechnology  http://qtec.com/
  * based on xparameters-ml507.h by Xilinx
  *
@@ -12,12 +12,15 @@
 
 #define XPAR_DDR2_SDRAM_MEM_BASEADDR	0x00000000
 #define XPAR_IIC_EEPROM_BASEADDR	0x81600000
-#define XPAR_INTC_0_BASEADDR		0x81800000
-#define XPAR_UARTLITE_0_BASEADDR	0x84000000
-#define XPAR_FLASH_MEM0_BASEADDR	0xFE000000
+#define XPAR_INTC_0_BASEADDR		0x87000000
+#define XPAR_FLASH_MEM0_BASEADDR	0xF0000000
 #define XPAR_PLB_CLOCK_FREQ_HZ		100000000
 #define XPAR_CORE_CLOCK_FREQ_HZ		400000000
-#define XPAR_INTC_MAX_NUM_INTR_INPUTS	13
-#define XPAR_UARTLITE_0_BAUDRATE	9600
+#define XPAR_INTC_MAX_NUM_INTR_INPUTS	32
+#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ	100000000
+#define XPAR_LLTEMAC_0_LLINK_CONNECTED_BASEADDR 0x80
+#define XPAR_LLTEMAC_1_LLINK_CONNECTED_BASEADDR 0x98
+#define XPAR_LLTEMAC_0_BASEADDR		0x83000000
+#define XPAR_LLTEMAC_1_BASEADDR		0x83000040
 
 #endif
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 414f5302a06..01bae5d67e3 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -8,7 +8,6 @@
 #include <fdtdec.h>
 #include <fpga.h>
 #include <mmc.h>
-#include <netdev.h>
 #include <zynqpl.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
@@ -94,34 +93,11 @@ int board_late_init(void)
 #ifdef CONFIG_DISPLAY_BOARDINFO
 int checkboard(void)
 {
-	puts("Board:\tXilinx Zynq\n");
+	puts("Board: Xilinx Zynq\n");
 	return 0;
 }
 #endif
 
-int board_eth_init(bd_t *bis)
-{
-	u32 ret = 0;
-
-#ifdef CONFIG_XILINX_AXIEMAC
-	ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
-						XILINX_AXIDMA_BASEADDR);
-#endif
-#ifdef CONFIG_XILINX_EMACLITE
-	u32 txpp = 0;
-	u32 rxpp = 0;
-# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
-	txpp = 1;
-# endif
-# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
-	rxpp = 1;
-# endif
-	ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
-			txpp, rxpp);
-#endif
-	return ret;
-}
-
 int dram_init(void)
 {
 #if CONFIG_IS_ENABLED(OF_CONTROL)
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 2cf47125d43..44d347ed3bf 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -9,6 +9,7 @@
 #include <netdev.h>
 #include <ahci.h>
 #include <scsi.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/io.h>
@@ -28,10 +29,18 @@ int board_early_init_r(void)
 {
 	u32 val;
 
-	val = readl(&crlapb_base->timestamp_ref_ctrl);
-	val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
-	writel(val, &crlapb_base->timestamp_ref_ctrl);
-
+	if (current_el() == 3) {
+		val = readl(&crlapb_base->timestamp_ref_ctrl);
+		val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
+		writel(val, &crlapb_base->timestamp_ref_ctrl);
+
+		/* Program freq register in System counter */
+		writel(zynqmp_get_system_timer_freq(),
+		       &iou_scntr_secure->base_frequency_id_register);
+		/* And enable system counter */
+		writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
+		       &iou_scntr_secure->counter_control_register);
+	}
 	/* Program freq register in System counter and enable system counter */
 	writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register);
 	writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG |
@@ -48,11 +57,6 @@ int dram_init(void)
 	return 0;
 }
 
-int timer_init(void)
-{
-	return 0;
-}
-
 void reset_cpu(ulong addr)
 {
 }
@@ -73,11 +77,36 @@ int board_late_init(void)
 	reg = readl(&crlapb_base->boot_mode);
 	bootmode = reg & BOOT_MODES_MASK;
 
+	puts("Bootmode: ");
 	switch (bootmode) {
-	case SD_MODE:
+	case JTAG_MODE:
+		puts("JTAG_MODE\n");
+		setenv("modeboot", "jtagboot");
+		break;
+	case QSPI_MODE_24BIT:
+	case QSPI_MODE_32BIT:
+		setenv("modeboot", "qspiboot");
+		puts("QSPI_MODE\n");
+		break;
 	case EMMC_MODE:
+		puts("EMMC_MODE\n");
+		setenv("modeboot", "sdboot");
+		break;
+	case SD_MODE:
+		puts("SD_MODE\n");
 		setenv("modeboot", "sdboot");
 		break;
+	case SD_MODE1:
+		puts("SD_MODE1\n");
+#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
+		setenv("sdbootdev", "1");
+#endif
+		setenv("modeboot", "sdboot");
+		break;
+	case NAND_MODE:
+		puts("NAND_MODE\n");
+		setenv("modeboot", "nandboot");
+		break;
 	default:
 		printf("Invalid Boot Mode:0x%x\n", bootmode);
 		break;
@@ -88,7 +117,7 @@ int board_late_init(void)
 
 int checkboard(void)
 {
-	puts("Board:\tXilinx ZynqMP\n");
+	puts("Board: Xilinx ZynqMP\n");
 	return 0;
 }