mpc5xxx: Remove all references to MGT5100

We do not support a processor that never reached a real customer.

Signed-off-by: Detlev Zundel <dzu@denx.de>

25 files changed, 2 insertions, 473 deletions

diff --git a/board/bc3450/bc3450.c b/board/bc3450/bc3450.c
index 6fb0096bede..3117b5fbffe 100644
--- a/board/bc3450/bc3450.c
+++ b/board/bc3450/bc3450.c
@@ -104,7 +104,6 @@ static void sdram_start (int hi_addr)
  *	      is something else than 0x00000000.
  */
 
-#if defined(CONFIG_MPC5200)
 phys_size_t initdram (int board_type)
 {
 	ulong dramsize = 0;
@@ -204,57 +203,6 @@ phys_size_t initdram (int board_type)
 	return dramsize;
 }
 
-#elif defined(CONFIG_MGT5100)
-
-phys_size_t initdram (int board_type)
-{
-	ulong dramsize = 0;
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup and enable SDRAM chip selects */
-	*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
-	*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;	/* 2G		*/
-	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22);	/* Enable SDRAM */
-	__asm__ volatile ("sync");
-
-	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-
-	/* address select register */
-	*(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
-	__asm__ volatile ("sync");
-
-	/* find RAM size */
-	sdram_start(0);
-	test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* set SDRAM end address according to size */
-	*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* Retrieve amount of SDRAM available */
-	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	return dramsize;
-}
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
-
 int checkboard (void)
 {
 #if defined (CONFIG_TQM5200)
@@ -276,10 +224,6 @@ void flash_preinit(void)
 	 * Note that CS_BOOT cannot be cleared when
 	 * executing in flash.
 	 */
-#if defined(CONFIG_MGT5100)
-	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25);	/* disable CS_BOOT */
-	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16);	/* enable CS0	   */
-#endif
 	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1;		/* clear RO	   */
 }
 
diff --git a/board/bc3450/mt48lc16m16a2-75.h b/board/bc3450/mt48lc16m16a2-75.h
index 3f1e1691bb6..48b43213dcb 100644
--- a/board/bc3450/mt48lc16m16a2-75.h
+++ b/board/bc3450/mt48lc16m16a2-75.h
@@ -23,7 +23,6 @@
 
 #define SDRAM_DDR	0		/* is SDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x00CD0000
 /* #define SDRAM_MODE	0x008D0000 */ /* CAS latency 2 */
@@ -33,15 +32,3 @@
 /*#define SDRAM_CONFIG1	0xD7322800 */ /* SDRAM controller bug workaround */
 #define SDRAM_CONFIG2	0x8AD70000
 /*#define SDRAM_CONFIG2	0xDDD70000 */ /* SDRAM controller bug workaround */
-
-#elif defined(CONFIG_MGT5100)
-/* Settings for XLB = 66 MHz */
-#define SDRAM_MODE	0x008D0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xC2222600
-#define SDRAM_CONFIG2	0x88B70004
-#define SDRAM_ADDRSEL	0x02000000
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
diff --git a/board/canmb/canmb.c b/board/canmb/canmb.c
index dce07bf785a..6ddc858ea4a 100644
--- a/board/canmb/canmb.c
+++ b/board/canmb/canmb.c
@@ -81,7 +81,6 @@ static void sdram_start (int hi_addr)
  *            is something else than 0x00000000.
  */
 
-#if defined(CONFIG_MPC5200)
 phys_size_t initdram (int board_type)
 {
 	ulong dramsize = 0;
@@ -183,57 +182,6 @@ phys_size_t initdram (int board_type)
 	return dramsize + dramsize2;
 }
 
-#elif defined(CONFIG_MGT5100)
-
-phys_size_t initdram (int board_type)
-{
-	ulong dramsize = 0;
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup and enable SDRAM chip selects */
-	*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
-	*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
-	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
-	__asm__ volatile ("sync");
-
-	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-
-	/* address select register */
-	*(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
-	__asm__ volatile ("sync");
-
-	/* find RAM size */
-	sdram_start(0);
-	test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* set SDRAM end address according to size */
-	*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* Retrieve amount of SDRAM available */
-	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	return dramsize;
-}
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
-
 int checkboard (void)
 {
 	puts ("Board: CANMB\n");
diff --git a/board/canmb/mt48lc16m32s2-75.h b/board/canmb/mt48lc16m32s2-75.h
index ffdf0396a54..15477259cae 100644
--- a/board/canmb/mt48lc16m32s2-75.h
+++ b/board/canmb/mt48lc16m32s2-75.h
@@ -23,21 +23,8 @@
 
 #define SDRAM_DDR	0		/* is SDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x00CD0000
 #define SDRAM_CONTROL	0x504F0000
 #define SDRAM_CONFIG1	0xD2322800
 #define SDRAM_CONFIG2	0x8AD70000
-
-#elif defined(CONFIG_MGT5100)
-/* Settings for XLB = 66 MHz */
-#define SDRAM_MODE	0x008D0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xC2222600
-#define SDRAM_CONFIG2	0x88B70004
-#define SDRAM_ADDRSEL	0x02000000
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
diff --git a/board/esd/cpci5200/mt46v16m16-75.h b/board/esd/cpci5200/mt46v16m16-75.h
index 22d0a554442..cf63806a588 100644
--- a/board/esd/cpci5200/mt46v16m16-75.h
+++ b/board/esd/cpci5200/mt46v16m16-75.h
@@ -23,7 +23,6 @@
 
 #define SDRAM_DDR	1	/* is DDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x018D0000
 #define SDRAM_EMODE	0x40090000
@@ -31,7 +30,3 @@
 #define SDRAM_CONFIG1	0x73722930
 #define SDRAM_CONFIG2	0x47770000
 #define SDRAM_TAPDELAY	0x10000000
-
-#else
-#error CONFIG_MPC5200 not defined
-#endif
diff --git a/board/esd/mecp5200/mt46v16m16-75.h b/board/esd/mecp5200/mt46v16m16-75.h
index 22d0a554442..cf63806a588 100644
--- a/board/esd/mecp5200/mt46v16m16-75.h
+++ b/board/esd/mecp5200/mt46v16m16-75.h
@@ -23,7 +23,6 @@
 
 #define SDRAM_DDR	1	/* is DDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x018D0000
 #define SDRAM_EMODE	0x40090000
@@ -31,7 +30,3 @@
 #define SDRAM_CONFIG1	0x73722930
 #define SDRAM_CONFIG2	0x47770000
 #define SDRAM_TAPDELAY	0x10000000
-
-#else
-#error CONFIG_MPC5200 not defined
-#endif
diff --git a/board/esd/pf5200/mt46v16m16-75.h b/board/esd/pf5200/mt46v16m16-75.h
index 22d0a554442..cf63806a588 100644
--- a/board/esd/pf5200/mt46v16m16-75.h
+++ b/board/esd/pf5200/mt46v16m16-75.h
@@ -23,7 +23,6 @@
 
 #define SDRAM_DDR	1	/* is DDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x018D0000
 #define SDRAM_EMODE	0x40090000
@@ -31,7 +30,3 @@
 #define SDRAM_CONFIG1	0x73722930
 #define SDRAM_CONFIG2	0x47770000
 #define SDRAM_TAPDELAY	0x10000000
-
-#else
-#error CONFIG_MPC5200 not defined
-#endif
diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c
index 75244610cff..47b21955579 100644
--- a/board/icecube/icecube.c
+++ b/board/icecube/icecube.c
@@ -134,7 +134,6 @@ static void sdram_start (int hi_addr)
  *            is something else than 0x00000000.
  */
 
-#if defined(CONFIG_MPC5200)
 phys_size_t initdram (int board_type)
 {
 	ulong dramsize = 0;
@@ -258,65 +257,12 @@ phys_size_t initdram (int board_type)
 	return dramsize + dramsize2;
 }
 
-#elif defined(CONFIG_MGT5100)
-
-phys_size_t initdram (int board_type)
-{
-	ulong dramsize = 0;
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup and enable SDRAM chip selects */
-	*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
-	*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
-	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
-	__asm__ volatile ("sync");
-
-	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-
-	/* address select register */
-	*(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
-	__asm__ volatile ("sync");
-
-	/* find RAM size */
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* set SDRAM end address according to size */
-	*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* Retrieve amount of SDRAM available */
-	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	return dramsize;
-}
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
-
 int checkboard (void)
 {
 #if defined (CONFIG_LITE5200B)
 	puts ("Board: Freescale Lite5200B\n");
-#elif defined(CONFIG_MPC5200)
+#else
 	puts ("Board: Motorola MPC5200 (IceCube)\n");
-#elif defined(CONFIG_MGT5100)
-	puts ("Board: Motorola MGT5100 (IceCube)\n");
 #endif
 	return 0;
 }
@@ -329,10 +275,6 @@ void flash_preinit(void)
 	 * Note that CS_BOOT cannot be cleared when
 	 * executing in flash.
 	 */
-#if defined(CONFIG_MGT5100)
-	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
-	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
-#endif
 	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
 }
 
diff --git a/board/icecube/mt46v16m16-75.h b/board/icecube/mt46v16m16-75.h
index 4c0f9a74067..eb857404f13 100644
--- a/board/icecube/mt46v16m16-75.h
+++ b/board/icecube/mt46v16m16-75.h
@@ -23,7 +23,6 @@
 
 #define SDRAM_DDR	1		/* is DDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x018D0000
 #define SDRAM_EMODE	0x40090000
@@ -31,7 +30,3 @@
 #define SDRAM_CONFIG1	0x73722930
 #define SDRAM_CONFIG2	0x47770000
 #define SDRAM_TAPDELAY	0x10000000
-
-#else
-#error CONFIG_MPC5200 not defined
-#endif
diff --git a/board/icecube/mt46v32m16.h b/board/icecube/mt46v32m16.h
index de2b48bc603..519bf6d0f08 100644
--- a/board/icecube/mt46v32m16.h
+++ b/board/icecube/mt46v32m16.h
@@ -23,7 +23,6 @@
 
 #define SDRAM_DDR	1		/* is DDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x018D0000
 #define SDRAM_EMODE	0x40090000
@@ -31,7 +30,3 @@
 #define SDRAM_CONFIG1	0x73722930
 #define SDRAM_CONFIG2	0x47770000
 #define SDRAM_TAPDELAY	0x10000000
-
-#else
-#error CONFIG_MPC5200 not defined
-#endif
diff --git a/board/icecube/mt48lc16m16a2-75.h b/board/icecube/mt48lc16m16a2-75.h
index ffdf0396a54..15477259cae 100644
--- a/board/icecube/mt48lc16m16a2-75.h
+++ b/board/icecube/mt48lc16m16a2-75.h
@@ -23,21 +23,8 @@
 
 #define SDRAM_DDR	0		/* is SDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x00CD0000
 #define SDRAM_CONTROL	0x504F0000
 #define SDRAM_CONFIG1	0xD2322800
 #define SDRAM_CONFIG2	0x8AD70000
-
-#elif defined(CONFIG_MGT5100)
-/* Settings for XLB = 66 MHz */
-#define SDRAM_MODE	0x008D0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xC2222600
-#define SDRAM_CONFIG2	0x88B70004
-#define SDRAM_ADDRSEL	0x02000000
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
diff --git a/board/jupiter/jupiter.c b/board/jupiter/jupiter.c
index 6e752c6554a..967aabdcfa9 100644
--- a/board/jupiter/jupiter.c
+++ b/board/jupiter/jupiter.c
@@ -227,10 +227,6 @@ void flash_preinit(void)
 	 * Note that CS_BOOT cannot be cleared when
 	 * executing in flash.
 	 */
-#if defined(CONFIG_MGT5100)
-	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
-	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
-#endif
 	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
 }
 
@@ -248,10 +244,8 @@ void flash_afterinit(ulong size)
 		*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
 			STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
 	}
-#if defined(CONFIG_MPC5200)
 	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
 	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
-#endif
 }
 
 int update_flash_size (int flash_size)
diff --git a/board/mcc200/mt46v16m16-75.h b/board/mcc200/mt46v16m16-75.h
index f650faaa109..423febe20a5 100644
--- a/board/mcc200/mt46v16m16-75.h
+++ b/board/mcc200/mt46v16m16-75.h
@@ -23,7 +23,6 @@
 
 #define SDRAM_DDR	1		/* is DDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x018D0000
 #define SDRAM_EMODE	0x40090000
@@ -31,7 +30,3 @@
 #define SDRAM_CONFIG1	0x73722930
 #define SDRAM_CONFIG2	0x47770000
 #define SDRAM_TAPDELAY	0x10000000
-
-#else
-#error CONFIG_MPC5200 not defined
-#endif
diff --git a/board/mcc200/mt48lc16m16a2-75.h b/board/mcc200/mt48lc16m16a2-75.h
index ffdf0396a54..15477259cae 100644
--- a/board/mcc200/mt48lc16m16a2-75.h
+++ b/board/mcc200/mt48lc16m16a2-75.h
@@ -23,21 +23,8 @@
 
 #define SDRAM_DDR	0		/* is SDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x00CD0000
 #define SDRAM_CONTROL	0x504F0000
 #define SDRAM_CONFIG1	0xD2322800
 #define SDRAM_CONFIG2	0x8AD70000
-
-#elif defined(CONFIG_MGT5100)
-/* Settings for XLB = 66 MHz */
-#define SDRAM_MODE	0x008D0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xC2222600
-#define SDRAM_CONFIG2	0x88B70004
-#define SDRAM_ADDRSEL	0x02000000
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
diff --git a/board/mcc200/mt48lc16m32s2-75.h b/board/mcc200/mt48lc16m32s2-75.h
index ffdf0396a54..15477259cae 100644
--- a/board/mcc200/mt48lc16m32s2-75.h
+++ b/board/mcc200/mt48lc16m32s2-75.h
@@ -23,21 +23,8 @@
 
 #define SDRAM_DDR	0		/* is SDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x00CD0000
 #define SDRAM_CONTROL	0x504F0000
 #define SDRAM_CONFIG1	0xD2322800
 #define SDRAM_CONFIG2	0x8AD70000
-
-#elif defined(CONFIG_MGT5100)
-/* Settings for XLB = 66 MHz */
-#define SDRAM_MODE	0x008D0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xC2222600
-#define SDRAM_CONFIG2	0x88B70004
-#define SDRAM_ADDRSEL	0x02000000
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
diff --git a/board/munices/mt48lc16m16a2-75.h b/board/munices/mt48lc16m16a2-75.h
index ffdf0396a54..15477259cae 100644
--- a/board/munices/mt48lc16m16a2-75.h
+++ b/board/munices/mt48lc16m16a2-75.h
@@ -23,21 +23,8 @@
 
 #define SDRAM_DDR	0		/* is SDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x00CD0000
 #define SDRAM_CONTROL	0x504F0000
 #define SDRAM_CONFIG1	0xD2322800
 #define SDRAM_CONFIG2	0x8AD70000
-
-#elif defined(CONFIG_MGT5100)
-/* Settings for XLB = 66 MHz */
-#define SDRAM_MODE	0x008D0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xC2222600
-#define SDRAM_CONFIG2	0x88B70004
-#define SDRAM_ADDRSEL	0x02000000
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
diff --git a/board/pm520/mt46v16m16-75.h b/board/pm520/mt46v16m16-75.h
index f650faaa109..423febe20a5 100644
--- a/board/pm520/mt46v16m16-75.h
+++ b/board/pm520/mt46v16m16-75.h
@@ -23,7 +23,6 @@
 
 #define SDRAM_DDR	1		/* is DDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x018D0000
 #define SDRAM_EMODE	0x40090000
@@ -31,7 +30,3 @@
 #define SDRAM_CONFIG1	0x73722930
 #define SDRAM_CONFIG2	0x47770000
 #define SDRAM_TAPDELAY	0x10000000
-
-#else
-#error CONFIG_MPC5200 not defined
-#endif
diff --git a/board/pm520/mt48lc16m16a2-75.h b/board/pm520/mt48lc16m16a2-75.h
index ffdf0396a54..15477259cae 100644
--- a/board/pm520/mt48lc16m16a2-75.h
+++ b/board/pm520/mt48lc16m16a2-75.h
@@ -23,21 +23,8 @@
 
 #define SDRAM_DDR	0		/* is SDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x00CD0000
 #define SDRAM_CONTROL	0x504F0000
 #define SDRAM_CONFIG1	0xD2322800
 #define SDRAM_CONFIG2	0x8AD70000
-
-#elif defined(CONFIG_MGT5100)
-/* Settings for XLB = 66 MHz */
-#define SDRAM_MODE	0x008D0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xC2222600
-#define SDRAM_CONFIG2	0x88B70004
-#define SDRAM_ADDRSEL	0x02000000
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
diff --git a/board/pm520/pm520.c b/board/pm520/pm520.c
index 9da1041733f..d6914343fae 100644
--- a/board/pm520/pm520.c
+++ b/board/pm520/pm520.c
@@ -84,7 +84,6 @@ static void sdram_start (int hi_addr)
  *            is something else than 0x00000000.
  */
 
-#if defined(CONFIG_MPC5200)
 phys_size_t initdram (int board_type)
 {
 	ulong dramsize = 0;
@@ -186,64 +185,9 @@ phys_size_t initdram (int board_type)
 	return dramsize + dramsize2;
 }
 
-#elif defined(CONFIG_MGT5100)
-
-phys_size_t initdram (int board_type)
-{
-	ulong dramsize = 0;
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup and enable SDRAM chip selects */
-	*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
-	*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
-	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
-	__asm__ volatile ("sync");
-
-	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-
-	/* address select register */
-	*(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
-	__asm__ volatile ("sync");
-
-	/* find RAM size */
-	sdram_start(0);
-	test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* set SDRAM end address according to size */
-	*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* Retrieve amount of SDRAM available */
-	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	return dramsize;
-}
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
-
 int checkboard (void)
 {
-#if defined(CONFIG_MPC5200)
 	puts ("Board: MicroSys PM520 \n");
-#elif defined(CONFIG_MGT5100)
-	puts ("Board: MicroSys PM510 \n");
-#endif
 	return 0;
 }
 
@@ -255,10 +199,6 @@ void flash_preinit(void)
 	 * Note that CS_BOOT cannot be cleared when
 	 * executing in flash.
 	 */
-#if defined(CONFIG_MGT5100)
-	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
-	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
-#endif
 	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
 }
 
diff --git a/board/total5200/mt48lc16m16a2-75.h b/board/total5200/mt48lc16m16a2-75.h
index 5b0923e3e82..ae237c6cab0 100644
--- a/board/total5200/mt48lc16m16a2-75.h
+++ b/board/total5200/mt48lc16m16a2-75.h
@@ -23,21 +23,8 @@
 
 #define SDRAM_DDR	0		/* is SDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x00CD0000
 #define SDRAM_CONTROL	0x504F0000
 #define SDRAM_CONFIG1	0xD2322800
 #define SDRAM_CONFIG2	0x8AD70000
-
-#elif defined(CONFIG_MGT5100)
-/* Settings for XLB = 66 MHz */
-#define SDRAM_MODE	0x008D0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xC2222600
-#define SDRAM_CONFIG2	0x88B70004
-#define SDRAM_ADDRSEL	0x02000000
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
diff --git a/board/total5200/mt48lc32m16a2-75.h b/board/total5200/mt48lc32m16a2-75.h
index 4b5ac80b350..cb4b43d63e9 100644
--- a/board/total5200/mt48lc32m16a2-75.h
+++ b/board/total5200/mt48lc32m16a2-75.h
@@ -28,13 +28,8 @@
 
 #define SDRAM_DDR	0		/* is SDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x00CD0000
 #define SDRAM_CONTROL	0x514F0000
 #define SDRAM_CONFIG1	0xD2322800
 #define SDRAM_CONFIG2	0x8AD70000
-
-#else
-#error CONFIG_MPC5200 is not defined
-#endif
diff --git a/board/total5200/sdram.c b/board/total5200/sdram.c
index dc4c6f18c2d..d883eb656da 100644
--- a/board/total5200/sdram.c
+++ b/board/total5200/sdram.c
@@ -76,7 +76,6 @@ static void mpc5xxx_sdram_start (sdram_conf_t *sdram_conf, int hi_addr)
  *            is something else than 0x00000000.
  */
 
-#if defined(CONFIG_MPC5200)
 long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf)
 {
 	ulong dramsize = 0;
@@ -174,54 +173,3 @@ long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf)
 
 	return dramsize + dramsize2;
 }
-
-#elif defined(CONFIG_MGT5100)
-
-long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf)
-{
-	ulong dramsize = 0;
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup and enable SDRAM chip selects */
-	*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
-	*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
-	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
-	__asm__ volatile ("sync");
-
-	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = sdram_conf->config1;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = sdram_conf->config2;
-
-	/* address select register */
-	*(vu_long *)MPC5XXX_SDRAM_XLBSEL = sdram_conf->addrsel;
-	__asm__ volatile ("sync");
-
-	/* find RAM size */
-	mpc5xxx_sdram_start(sdram_conf, 0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	mpc5xxx_sdram_start(sdram_conf, 1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		mpc5xxx_sdram_start(sdram_conf, 0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* set SDRAM end address according to size */
-	*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* Retrieve amount of SDRAM available */
-	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	return dramsize;
-}
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif
diff --git a/board/total5200/sdram.h b/board/total5200/sdram.h
index bc21e1d300f..396a190145d 100644
--- a/board/total5200/sdram.h
+++ b/board/total5200/sdram.h
@@ -28,12 +28,7 @@ typedef struct {
 	ulong control;
 	ulong config1;
 	ulong config2;
-#if defined(CONFIG_MPC5200)
 	ulong tapdelay;
-#endif
-#if defined(CONFIG_MGT5100)
-	ulong addrsel;
-#endif
 } sdram_conf_t;
 
 long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf);
diff --git a/board/total5200/total5200.c b/board/total5200/total5200.c
index c524d63f93c..61b5b807af0 100644
--- a/board/total5200/total5200.c
+++ b/board/total5200/total5200.c
@@ -47,26 +47,17 @@ phys_size_t initdram (int board_type)
 	sdram_conf.control = SDRAM_CONTROL;
 	sdram_conf.config1 = SDRAM_CONFIG1;
 	sdram_conf.config2 = SDRAM_CONFIG2;
-#if defined(CONFIG_MPC5200)
 	sdram_conf.tapdelay = 0;
-#endif
-#if defined(CONFIG_MGT5100)
-	sdram_conf.addrsel = SDRAM_ADDRSEL;
-#endif
 	return mpc5xxx_sdram_init (&sdram_conf);
 }
 
 int checkboard (void)
 {
-#if defined(CONFIG_MPC5200)
 #if CONFIG_TOTAL5200_REV==2
 	puts ("Board: Total5200 Rev.2 ");
 #else
 	puts ("Board: Total5200 ");
 #endif
-#elif defined(CONFIG_MGT5100)
-	puts ("Board: Total5100 ");
-#endif
 
 	/*
 	 * Retrieve FPGA Revision.
@@ -85,20 +76,6 @@ int checkboard (void)
 	return 0;
 }
 
-#if defined(CONFIG_MGT5100)
-int board_early_init_r(void)
-{
-	/*
-	 * Now, when we are in RAM, enable CS0
-	 * because CS_BOOT cannot be written.
-	 */
-	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
-	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
-
-	return 0;
-}
-#endif
-
 #ifdef	CONFIG_PCI
 static struct pci_controller hose;
 
@@ -266,9 +243,7 @@ static const S1D_REGS init_regs [] =
 void video_get_info_str (int line_number, char *info)
 {
 	if (line_number == 1) {
-#ifdef CONFIG_MGT5100
-		strcpy (info, " Total5100");
-#elif CONFIG_TOTAL5200_REV==1
+#if CONFIG_TOTAL5200_REV==1
 		strcpy (info, " Total5200");
 #elif CONFIG_TOTAL5200_REV==2
 		strcpy (info, " Total5200 Rev.2");
diff --git a/board/tqc/tqm5200/mt48lc16m16a2-75.h b/board/tqc/tqm5200/mt48lc16m16a2-75.h
index 3f1e1691bb6..48b43213dcb 100644
--- a/board/tqc/tqm5200/mt48lc16m16a2-75.h
+++ b/board/tqc/tqm5200/mt48lc16m16a2-75.h
@@ -23,7 +23,6 @@
 
 #define SDRAM_DDR	0		/* is SDR */
 
-#if defined(CONFIG_MPC5200)
 /* Settings for XLB = 132 MHz */
 #define SDRAM_MODE	0x00CD0000
 /* #define SDRAM_MODE	0x008D0000 */ /* CAS latency 2 */
@@ -33,15 +32,3 @@
 /*#define SDRAM_CONFIG1	0xD7322800 */ /* SDRAM controller bug workaround */
 #define SDRAM_CONFIG2	0x8AD70000
 /*#define SDRAM_CONFIG2	0xDDD70000 */ /* SDRAM controller bug workaround */
-
-#elif defined(CONFIG_MGT5100)
-/* Settings for XLB = 66 MHz */
-#define SDRAM_MODE	0x008D0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xC2222600
-#define SDRAM_CONFIG2	0x88B70004
-#define SDRAM_ADDRSEL	0x02000000
-
-#else
-#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
-#endif