diff options
| author | Penda Naveen Kumar <pnaveen@ti.com> | 2009-07-31 00:06:36 +0530 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2009-08-08 11:59:40 +0200 |
| commit | 3b9043a7c03290c9bdbef03848307263f5f3472c (patch) | |
| tree | 9c5560893b38cbf4061b28e3e571c6449a8a69d4 /cpu/arm_cortexa8 | |
| parent | 61c68ae0b43bb5d6ab32958c45289aa197b1a2d1 (diff) | |
omap3: bug fix for NOR boot support
This patch provides bug fix, when omap3 uses nor boot.
Signed-off-by: Penda Naveen Kumar<pnaveen@ti.com>
Acked-by: Dirk Behme <dirk.behme@googlemail.com>
Diffstat (limited to 'cpu/arm_cortexa8')
| -rw-r--r-- | cpu/arm_cortexa8/omap3/lowlevel_init.S | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/cpu/arm_cortexa8/omap3/lowlevel_init.S b/cpu/arm_cortexa8/omap3/lowlevel_init.S index cf1f927cffd..73063ec8e66 100644 --- a/cpu/arm_cortexa8/omap3/lowlevel_init.S +++ b/cpu/arm_cortexa8/omap3/lowlevel_init.S @@ -135,19 +135,19 @@ _go_to_speed: .word go_to_speed /* these constants need to be close for PIC code */ /* The Nor has to be in the Flash Base CS0 for this condition to happen */ flash_cfg1_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1) + .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG1) flash_cfg3_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3) + .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG3) flash_cfg3_val: .word STNOR_GPMC_CONFIG3 flash_cfg4_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4) + .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG4) flash_cfg4_val: .word STNOR_GPMC_CONFIG4 flash_cfg5_val: .word STNOR_GPMC_CONFIG5 flash_cfg5_addr: - .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5) + .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG5) pll_ctl_add: .word CM_CLKEN_PLL pll_div_add1: |