* Patch by Dave Ellis, 22 May 2003:LABEL_2003_05_23_0055

  Fix problem with only partially cleared .bss segment

* Patch by Rune Torgersen, 12 May 2003:
  get PCI to work on a MPC8266ADS board; incorporate change to
  cpu/mpc8260/pci.c to enable overrides of PCI memory parameters

1 files changed, 187 insertions, 32 deletions

diff --git a/cpu/mpc8260/pci.c b/cpu/mpc8260/pci.c
index b7a04d52b23..47c5dae18f9 100644
--- a/cpu/mpc8260/pci.c
+++ b/cpu/mpc8260/pci.c
@@ -26,22 +26,30 @@
 #ifdef CONFIG_PCI
 
 #include <pci.h>
+#include <mpc8260.h>
 #include <asm/m8260_pci.h>
 
 /*
  *   Local->PCI map (from CPU)                             controlled by
  *   MPC826x master window
  *
- *   0x80000000 - 0xBFFFFFFF    Total CPU2PCI space        PCIBR0
+ *   0x80000000 - 0xBFFFFFFF    CPU2PCI space              PCIBR0
+ *   0xF4000000 - 0xF7FFFFFF    CPU2PCI space              PCIBR1
  *                       
- *   0x80000000 - 0x8FFFFFFF    PCI Mem with prefetch      (Outbound ATU #1)
- *   0x90000000 - 0x9FFFFFFF    PCI Mem w/o  prefetch      (Outbound ATU #2)
- *   0xA0000000 - 0xAFFFFFFF    32-bit PCI IO              (Outbound ATU #3)
+ *   0x80000000 - 0x9FFFFFFF    0x80000000 - 0x9FFFFFFF   (Outbound ATU #1)
+ *                              PCI Mem with prefetch
+ *
+ *   0xA0000000 - 0xBFFFFFFF    0xA0000000 - 0xBFFFFFFF   (Outbound ATU #2)
+ *                              PCI Mem w/o  prefetch
+ *
+ *   0xF4000000 - 0xF7FFFFFF    0x00000000 - 0x03FFFFFF   (Outbound ATU #3)
+ *                              32-bit PCI IO
  *                      
  *   PCI->Local map (from PCI)
  *   MPC826x slave window                                  controlled by
  *
- *   0x00000000 - 0x07FFFFFF    MPC826x local memory       (Inbound ATU #1)
+ *   0x00000000 - 0x1FFFFFFF    0x00000000 - 0x1FFFFFFF   (Inbound ATU #1)
+ *                              MPC826x local memory
  */
 
 /* 
@@ -49,20 +57,57 @@
  * This window is set up using the first set of Inbound ATU registers
  */
 
-#define PCI_SLV_MEM_LOCAL	CFG_SDRAM_BASE		/* Local base */
-#define PCI_SLV_MEM_BUS		0x00000000		/* PCI base */
+#ifndef CFG_PCI_SLV_MEM_LOCAL 
+#define PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE		/* Local base */ 
+#else 
+#define PCI_SLV_MEM_LOCAL CFG_PCI_SLV_MEM_LOCAL 
+#endif
+
+#ifndef CFG_PCI_SLV_MEM_BUS
+#define PCI_SLV_MEM_BUS 0x00000000		/* PCI base */
+#else
+#define PCI_SLV_MEM_BUS CFG_PCI_SLV_MEM_BUS
+#endif
+
+#ifndef CFG_PICMR0_MASK_ATTRIB
 #define PICMR0_MASK_ATTRIB	(PICMR_MASK_512MB | PICMR_ENABLE | \
                           	 PICMR_PREFETCH_EN)
+#else
+#define PICMR0_MASK_ATTRIB CFG_PICMR0_MASK_ATTRIB
+#endif
 
 /* 
- * This is the window that allows the CPU to access PCI address space.
- * It will be setup with the SIU PCIBR0 register. All three PCI master
- * windows, which allow the CPU to access PCI prefetch, non prefetch,
- * and IO space (see below), must all fit within this window. 
+ * These are the windows that allow the CPU to access PCI address space.
+ * All three PCI master windows, which allow the CPU to access PCI 
+ * prefetch, non prefetch, and IO space (see below), must all fit within 
+ * these windows.
  */
 
-#define PCI_MSTR_LOCAL		0x80000000		/* Local base */
+/* PCIBR0 */
+#ifndef CFG_PCI_MSTR0_LOCAL
+#define PCI_MSTR0_LOCAL		0x80000000		/* Local base */ 
+#else 
+#define PCI_MSTR0_LOCAL CFG_PCI_MSTR0_LOCAL
+#endif
+
+#ifndef CFG_PCIMSK0_MASK
 #define PCIMSK0_MASK		PCIMSK_1GB		/* Size of window */
+#else
+#define PCIMSK0_MASK	CFG_PCIMSK0_MASK
+#endif
+
+/* PCIBR1 */
+#ifndef CFG_PCI_MSTR1_LOCAL
+#define PCI_MSTR1_LOCAL		0xF4000000		/* Local base */ 
+#else 
+#define PCI_MSTR1_LOCAL		CFG_PCI_MSTR1_LOCAL 
+#endif
+
+#ifndef CFG_PCIMSK1_MASK
+#define  PCIMSK1_MASK		PCIMSK_64MB		/* Size of window */
+#else
+#define  PCIMSK1_MASK		CFG_PCIMSK1_MASK
+#endif
 
 /* 
  * Master window that allows the CPU to access PCI Memory (prefetch).
@@ -70,11 +115,35 @@
  * in the bridge.
  */
 
-#define PCI_MSTR_MEM_LOCAL	0x80000000          /* Local base */
-#define PCI_MSTR_MEM_BUS	0x80000000          /* PCI base   */
-#define CPU_PCI_MEM_START	PCI_MSTR_MEM_LOCAL
-#define PCI_MSTR_MEM_SIZE	0x10000000          /* 256MB */
+#ifndef CFG_PCI_MSTR_MEM_LOCAL
+#define PCI_MSTR_MEM_LOCAL 0x80000000          /* Local base */
+#else
+#define PCI_MSTR_MEM_LOCAL CFG_PCI_MSTR_MEM_LOCAL
+#endif
+
+#ifndef CFG_PCI_MSTR_MEM_BUS
+#define PCI_MSTR_MEM_BUS 0x80000000          /* PCI base   */
+#else
+#define PCI_MSTR_MEM_BUS CFG_PCI_MSTR_MEM_BUS
+#endif
+
+#ifndef CFG_CPU_PCI_MEM_START
+#define CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
+#else
+#define CPU_PCI_MEM_START CFG_CPU_PCI_MEM_START
+#endif
+
+#ifndef CFG_PCI_MSTR_MEM_SIZE
+#define PCI_MSTR_MEM_SIZE 0x10000000          /* 256MB */
+#else
+#define PCI_MSTR_MEM_SIZE CFG_PCI_MSTR_MEM_SIZE
+#endif
+
+#ifndef CFG_POCMR0_MASK_ATTRIB
 #define POCMR0_MASK_ATTRIB	(POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
+#else
+#define POCMR0_MASK_ATTRIB CFG_POCMR0_MASK_ATTRIB
+#endif
 
 /* 
  * Master window that allows the CPU to access PCI Memory (non-prefetch).
@@ -82,11 +151,35 @@
  * in the bridge.
  */
 
-#define PCI_MSTR_MEMIO_LOCAL    0x90000000          /* Local base */
-#define PCI_MSTR_MEMIO_BUS      0x90000000          /* PCI base   */
-#define CPU_PCI_MEMIO_START     PCI_MSTR_MEMIO_LOCAL
-#define PCI_MSTR_MEMIO_SIZE     0x10000000          /* 256MB */
-#define POCMR1_MASK_ATTRIB      (POCMR_MASK_256MB | POCMR_ENABLE)
+#ifndef CFG_PCI_MSTR_MEMIO_LOCAL 
+#define PCI_MSTR_MEMIO_LOCAL 0x90000000          /* Local base */ 
+#else 
+#define PCI_MSTR_MEMIO_LOCAL CFG_PCI_MSTR_MEMIO_LOCAL 
+#endif
+
+#ifndef CFG_PCI_MSTR_MEMIO_BUS 
+#define PCI_MSTR_MEMIO_BUS 0x90000000          /* PCI base   */ 
+#else 
+#define PCI_MSTR_MEMIO_BUS CFG_PCI_MSTR_MEMIO_BUS 
+#endif
+
+#ifndef CFG_CPU_PCI_MEMIO_START 
+#define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL 
+#else 
+#define CPU_PCI_MEMIO_START CFG_CPU_PCI_MEMIO_START 
+#endif
+
+#ifndef CFG_PCI_MSTR_MEMIO_SIZE 
+#define PCI_MSTR_MEMIO_SIZE 0x20000000          /* 512MB */ 
+#else 
+#define PCI_MSTR_MEMIO_SIZE CFG_PCI_MSTR_MEMIO_SIZE 
+#endif
+
+#ifndef CFG_POCMR1_MASK_ATTRIB
+#define POCMR1_MASK_ATTRIB      (POCMR_MASK_512MB | POCMR_ENABLE)
+#else
+#define POCMR1_MASK_ATTRIB CFG_POCMR1_MASK_ATTRIB
+#endif
 
 /* 
  * Master window that allows the CPU to access PCI IO space.
@@ -94,15 +187,35 @@
  * in the bridge.
  */
 
-#define PCI_MSTR_IO_LOCAL       0xA0000000          /* Local base */
-#ifdef CONFIG_ATC
-#define PCI_MSTR_IO_BUS         0x00000000          /* PCI base   */
-#else
-#define PCI_MSTR_IO_BUS         0xA0000000          /* PCI base   */
+#ifndef CFG_PCI_MSTR_IO_LOCAL 
+#define PCI_MSTR_IO_LOCAL 0xA0000000          /* Local base */ 
+#else 
+#define PCI_MSTR_IO_LOCAL CFG_PCI_MSTR_IO_LOCAL 
+#endif
+
+#ifndef CFG_PCI_MSTR_IO_BUS 
+#define PCI_MSTR_IO_BUS 0xA0000000          /* PCI base   */ 
+#else 
+#define PCI_MSTR_IO_BUS CFG_PCI_MSTR_IO_BUS 
+#endif
+
+#ifndef CFG_CPU_PCI_IO_START 
+#define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL 
+#else 
+#define CPU_PCI_IO_START CFG_CPU_PCI_IO_START 
+#endif
+
+#ifndef CFG_PCI_MSTR_IO_SIZE 
+#define PCI_MSTR_IO_SIZE 0x10000000          /* 256MB */ 
+#else 
+#define PCI_MSTR_IO_SIZE CFG_PCI_MSTR_IO_SIZE 
 #endif
-#define CPU_PCI_IO_START        PCI_MSTR_IO_LOCAL
-#define PCI_MSTR_IO_SIZE        0x10000000          /* 256MB */
+
+#ifndef CFG_POCMR2_MASK_ATTRIB
 #define POCMR2_MASK_ATTRIB      (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO)
+#else
+#define POCMR2_MASK_ATTRIB CFG_POCMR2_MASK_ATTRIB
+#endif
 
 /* PCI bus configuration registers.
  */
@@ -117,6 +230,9 @@ static inline void  pci_outl(u32 addr, u32 data)
 
 void pci_mpc8250_init(struct pci_controller *hose)
 {
+#ifdef CONFIG_MPC8266ADS
+    DECLARE_GLOBAL_DATA_PTR;
+#endif
     u16 tempShort;
     u32 immr_addr = CFG_IMMR;
     volatile immap_t *immap = (immap_t *) CFG_IMMR;
@@ -125,11 +241,19 @@ void pci_mpc8250_init(struct pci_controller *hose)
     pci_setup_indirect(hose, CFG_IMMR + PCI_CFG_ADDR_REG,
 	                         CFG_IMMR + PCI_CFG_DATA_REG);
 
+    /*
+     * Setting required to enable local bus for PCI (SIUMCR [LBPC]).
+     */
+#ifdef CONFIG_MPC8266ADS
+    immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
+				   | SIUMCR_LBPC01;
+#else
     /* 
      * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]), 
      * and local bus for PCI (SIUMCR [LBPC]).
      */
     immap->im_siu_conf.sc_siumcr = 0x00640000;
+#endif
 
     /* Make PCI lowest priority */
     /* Each 4 bits is a device bus request  and the MS 4bits 
@@ -153,18 +277,33 @@ void pci_mpc8250_init(struct pci_controller *hose)
     immap->im_siu_conf.sc_ppc_acr = 0x6;
 
     /* 
-     * Set up master window that allows the CPU to access PCI space. This 
-     * window is set up using the first SIU PCIBR registers.
+     * Set up master windows that allow the CPU to access PCI space. These 
+     * windows are set up using the two SIU PCIBR registers.
      */
     *(volatile unsigned long*)(immr_addr + M8265_PCIMSK0) = PCIMSK0_MASK;
     *(volatile unsigned long*)(immr_addr + M8265_PCIBR0) =
-	    PCI_MSTR_LOCAL | PCIBR_ENABLE;
+	    PCI_MSTR0_LOCAL | PCIBR_ENABLE;
+
+#ifdef CONFIG_MPC8266ADS
+    *(volatile unsigned long*)(immr_addr + M8265_PCIMSK1) = PCIMSK1_MASK;
+    *(volatile unsigned long*)(immr_addr + M8265_PCIBR1) =
+	    PCI_MSTR1_LOCAL | PCIBR_ENABLE;
+#endif 
 
     /* Release PCI RST (by default the PCI RST signal is held low)  */
     pci_outl (immr_addr | PCI_GCR_REG, PCIGCR_PCI_BUS_EN);
 
     /* give it some time */
-    udelay(1000);
+    {
+#ifdef CONFIG_MPC8266ADS 
+		/* Give the PCI cards more time to initialize before query 
+			This might be good for other boards also
+		*/
+        int i;
+        for (i = 0; i < 1000; ++i)
+#endif
+            udelay(1000);
+    }
 
     /* 
      * Set up master window that allows the CPU to access PCI Memory (prefetch) 
@@ -218,18 +357,34 @@ void pci_mpc8250_init(struct pci_controller *hose)
     hose->last_busno = 0xff;
 
     /* System memory space */
+#ifdef CONFIG_MPC8266ADS
+    pci_set_region(hose->regions + 0,
+		       PCI_SLV_MEM_BUS,
+		       PCI_SLV_MEM_LOCAL,
+		       gd->ram_size,
+		       PCI_REGION_MEM | PCI_REGION_MEMORY);
+#else
     pci_set_region(hose->regions + 0,
 		       CFG_SDRAM_BASE,
 		       CFG_SDRAM_BASE,
 		       0x4000000,
 		       PCI_REGION_MEM | PCI_REGION_MEMORY);
+#endif
 
     /* PCI memory space */
+#ifdef CONFIG_MPC8266ADS
+    pci_set_region(hose->regions + 0,
+		       PCI_SLV_MEM_BUS,
+		       PCI_SLV_MEM_LOCAL,
+		       gd->ram_size,
+		       PCI_REGION_MEM | PCI_REGION_MEMORY);
+#else
     pci_set_region(hose->regions + 1,
 		       PCI_MSTR_MEM_BUS,
 		       PCI_MSTR_MEM_LOCAL,
 		       PCI_MSTR_MEM_SIZE,
 		       PCI_REGION_MEM);
+#endif
 
     /* PCI I/O space */
     pci_set_region(hose->regions + 2,