diff options
| author | Scott Wood <scottwood@freescale.com> | 2009-01-20 11:56:11 -0600 |
|---|---|---|
| committer | Kim Phillips <kim.phillips@freescale.com> | 2009-01-21 18:43:57 -0600 |
| commit | 6677876181cc8772bca8a372479a500d160f3993 (patch) | |
| tree | 47919055c6d6de9e7a0a84c922a13d0161c394b2 /cpu/mpc83xx | |
| parent | 8b34557c546e5e9f34ebf83c93413dad973d93df (diff) | |
83xx: Use the proper sequence for updating IMMR.
This ensures that subsequent accesses properly hit the new window.
The dcbi during the NAND loop was accidentally working around this;
it's no longer necessary, as the cache is not enabled.
Reported-by: Suchit Lepcha <Suchit.Lepcha@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Diffstat (limited to 'cpu/mpc83xx')
| -rw-r--r-- | cpu/mpc83xx/start.S | 18 |
1 files changed, 15 insertions, 3 deletions
diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S index beebc9951c5..26e31061f41 100644 --- a/cpu/mpc83xx/start.S +++ b/cpu/mpc83xx/start.S @@ -200,9 +200,23 @@ boot_cold: /* time t 3 */ nop boot_warm: /* time t 5 */ mfmsr r5 /* save msr contents */ + + /* 83xx manuals prescribe a specific sequence for updating IMMRBAR. */ + bl 1f +1: mflr r7 + lis r3, CONFIG_SYS_IMMR@h ori r3, r3, CONFIG_SYS_IMMR@l + + lwz r6, IMMRBAR(r4) + isync + stw r3, IMMRBAR(r4) + lwz r6, 0(r7) /* Arbitrary external load */ + isync + + lwz r6, IMMRBAR(r3) + isync /* Initialise the E300 processor core */ /*------------------------------------------*/ @@ -212,9 +226,7 @@ boot_warm: /* time t 5 */ * is loaded. Wait for the rest before branching * to another flash page. */ - addi r7, r3, 0x50b0 -1: dcbi 0, r7 - lwz r6, 0(r7) +1: lwz r6, 0x50b0(r3) andi. r6, r6, 1 beq 1b #endif |