Merge branch 'master' of git://www.denx.de/git/u-boot-mpc86xx

Conflicts:

	common/cmd_reginfo.c

Signed-off-by: Wolfgang Denk <wd@denx.de>

4 files changed, 108 insertions, 79 deletions

diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c
index 11354d38dab..e1b3c52dcdc 100644
--- a/cpu/mpc86xx/cpu.c
+++ b/cpu/mpc86xx/cpu.c
@@ -27,6 +27,7 @@
 #include <command.h>
 #include <asm/cache.h>
 #include <mpc86xx.h>
+#include <asm/fsl_law.h>
 
 #if defined(CONFIG_OF_FLAT_TREE)
 #include <ft_build.h>
@@ -324,6 +325,27 @@ ft_cpu_setup(void *blob, bd_t *bd)
 	if (p != NULL)
 		memcpy(p, bd->bi_enet3addr, 6);
 #endif
+#endif /* CONFIG_OF_FLAT_TREE */
+
+/*
+ * Print out the state of various machine registers.
+ * Currently prints out LAWs and BR0/OR0
+ */
+void mpc86xx_reginfo(void)
+{
+	immap_t *immap = (immap_t *)CFG_IMMR;
+	ccsr_lbc_t *lbc = &immap->im_lbc;
+
+	print_laws();
+
+	printf ("Local Bus Controller Registers\n"
+		"\tBR0\t0x%08X\tOR0\t0x%08X \n", in_be32(&lbc->br0), in_be32(&lbc->or0));
+	printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", in_be32(&lbc->br1), in_be32(&lbc->or1));
+	printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", in_be32(&lbc->br2), in_be32(&lbc->or2));
+	printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", in_be32(&lbc->br3), in_be32(&lbc->or3));
+	printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", in_be32(&lbc->br4), in_be32(&lbc->or4));
+	printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", in_be32(&lbc->br5), in_be32(&lbc->or5));
+	printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", in_be32(&lbc->br6), in_be32(&lbc->or6));
+	printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", in_be32(&lbc->br7), in_be32(&lbc->or7));
 
 }
-#endif
diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c
index 4f8956e0afe..ab5906dbc0a 100644
--- a/cpu/mpc86xx/cpu_init.c
+++ b/cpu/mpc86xx/cpu_init.c
@@ -49,6 +49,10 @@ void cpu_init_f(void)
 	/* Clear initial global data */
 	memset ((void *) gd, 0, sizeof (gd_t));
 
+#ifdef CONFIG_FSL_LAW
+	init_laws();
+#endif
+
 	/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
 	 * addresses - these have to be modified later when FLASH size
 	 * has been determined
@@ -114,5 +118,8 @@ void cpu_init_f(void)
  */
 int cpu_init_r(void)
 {
+#ifdef CONFIG_FSL_LAW
+	disable_law(0);
+#endif
 	return 0;
 }
diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c
index 54e40f1f50d..e501caf457a 100644
--- a/cpu/mpc86xx/spd_sdram.c
+++ b/cpu/mpc86xx/spd_sdram.c
@@ -27,7 +27,7 @@
 #include <i2c.h>
 #include <spd.h>
 #include <asm/mmu.h>
-
+#include <asm/fsl_law.h>
 
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void dma_init(void);
@@ -1123,7 +1123,6 @@ spd_sdram(void)
 	int memsize_ddr1 = 0;
 	unsigned int law_size_ddr1;
 	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
 #ifdef CONFIG_DDR_INTERLEAVE
 	volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1;
 #endif
@@ -1179,12 +1178,9 @@ spd_sdram(void)
 		/*
 		 * Set up LAWBAR for DDR 1 space.
 		 */
-		mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
-		mcm->lawar1 = (LAWAR_EN
-			       | LAWAR_TRGT_IF_DDR_INTERLEAVED
-			       | (LAWAR_SIZE & law_size_interleaved));
-		debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1);
-		debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1);
+#ifdef CONFIG_FSL_LAW
+		set_law(1, CFG_DDR_SDRAM_BASE, law_size_interleaved, LAW_TRGT_IF_DDR_INTRLV);
+#endif
 		debug("Interleaved memory size is 0x%08lx\n", memsize_total);
 
 #ifdef	CONFIG_DDR_INTERLEAVE
@@ -1239,12 +1235,9 @@ spd_sdram(void)
 		/*
 		 * Set up LAWBAR for DDR 1 space.
 		 */
-		mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
-		mcm->lawar1 = (LAWAR_EN
-			       | LAWAR_TRGT_IF_DDR1
-			       | (LAWAR_SIZE & law_size_ddr1));
-		debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1);
-		debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1);
+#ifdef CONFIG_FSL_LAW
+		set_law(1, CFG_DDR_SDRAM_BASE, law_size_ddr1, LAW_TRGT_IF_DDR_1);
+#endif
 	}
 
 #if  (CONFIG_NUM_DDR_CONTROLLERS > 1)
@@ -1269,17 +1262,11 @@ spd_sdram(void)
 		/*
 		 * Set up LAWBAR for DDR 2 space.
 		 */
-		if (ddr1_enabled)
-			mcm->lawbar8 = (((memsize_ddr1 * 1024 * 1024) >> 12)
-					& 0xfffff);
-		else
-			mcm->lawbar8 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
-
-		mcm->lawar8 = (LAWAR_EN
-			       | LAWAR_TRGT_IF_DDR2
-			       | (LAWAR_SIZE & law_size_ddr2));
-		debug("\nDDR: LAWBAR8=0x%08x\n", mcm->lawbar8);
-		debug("DDR: LAWAR8=0x%08x\n", mcm->lawar8);
+#ifdef CONFIG_FSL_LAW
+		set_law(8,
+			(ddr1_enabled ? (memsize_ddr1 * 1024 * 1024) : CFG_DDR_SDRAM_BASE),
+			law_size_ddr2, LAW_TRGT_IF_DDR_2);
+#endif
 	}
 
 	debug("\nMemory size of DDR2 = 0x%08lx\n", memsize_ddr2);
diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S
index 09f4ceedb57..c71c92659d3 100644
--- a/cpu/mpc86xx/start.S
+++ b/cpu/mpc86xx/start.S
@@ -235,17 +235,8 @@ in_flash:
 	bl	enable_ext_addr
 
 	/* setup the bats */
-	bl	setup_bats
-	sync
-
-#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
-	/* setup ccsrbar */
-	bl	setup_ccsrbar
-#endif
+	bl	early_bats
 
-	/* setup the law entries */
-	bl	law_entry
-	sync
 	/*
 	 * Cache must be enabled here for stack-in-cache trick.
 	 * This means we need to enable the BATS.
@@ -282,6 +273,16 @@ in_flash:
 
 	GET_GOT			/* initialize GOT access	*/
 
+	/* setup the rest of the bats */
+	bl      setup_bats
+	bl      clear_tlbs
+	sync
+
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+	/* setup ccsrbar */
+	bl      setup_ccsrbar
+#endif
+
 	/* run low-level CPU init code	   (from Flash) */
 	bl	cpu_init_f
 	sync
@@ -359,6 +360,7 @@ invalidate_bats:
 
 
 	/* setup_bats - set them up to some initial state */
+	/* Skip any BATS setup in early_bats */
 	.globl	setup_bats
 setup_bats:
 
@@ -454,42 +456,6 @@ setup_bats:
 	mtspr	DBAT4U, r3
 	isync
 
-	/* IBAT 5 */
-	addis	r4, r0, CFG_IBAT5L@h
-	ori	r4, r4, CFG_IBAT5L@l
-	addis	r3, r0, CFG_IBAT5U@h
-	ori	r3, r3, CFG_IBAT5U@l
-	mtspr	IBAT5L, r4
-	mtspr	IBAT5U, r3
-	isync
-
-	/* DBAT 5 */
-	addis	r4, r0, CFG_DBAT5L@h
-	ori	r4, r4, CFG_DBAT5L@l
-	addis	r3, r0, CFG_DBAT5U@h
-	ori	r3, r3, CFG_DBAT5U@l
-	mtspr	DBAT5L, r4
-	mtspr	DBAT5U, r3
-	isync
-
-	/* IBAT 6 */
-	addis	r4, r0, CFG_IBAT6L@h
-	ori	r4, r4, CFG_IBAT6L@l
-	addis	r3, r0, CFG_IBAT6U@h
-	ori	r3, r3, CFG_IBAT6U@l
-	mtspr	IBAT6L, r4
-	mtspr	IBAT6U, r3
-	isync
-
-	/* DBAT 6 */
-	addis	r4, r0, CFG_DBAT6L@h
-	ori	r4, r4, CFG_DBAT6L@l
-	addis	r3, r0, CFG_DBAT6U@h
-	ori	r3, r3, CFG_DBAT6U@l
-	mtspr	DBAT6L, r4
-	mtspr	DBAT6U, r3
-	isync
-
 	/* IBAT 7 */
 	addis	r4, r0, CFG_IBAT7L@h
 	ori	r4, r4, CFG_IBAT7L@l
@@ -508,18 +474,65 @@ setup_bats:
 	mtspr	DBAT7U, r3
 	isync
 
-1:
-	addis	r3, 0, 0x0000
-	addis	r5, 0, 0x4	/* upper bound of 0x00040000 for 7400/750 */
+	sync
+	blr
+
+/*
+ * early_bats:
+ *
+ * Set up bats needed early on - this is usually the BAT for the
+ * stack-in-cache and the Flash
+ */
+	.globl  early_bats
+early_bats:
+	/* IBAT 5 */
+	lis   	r4, CFG_IBAT5L@h
+	ori     r4, r4, CFG_IBAT5L@l
+	lis   	r3, CFG_IBAT5U@h
+	ori     r3, r3, CFG_IBAT5U@l
+	mtspr   IBAT5L, r4
+	mtspr   IBAT5U, r3
+	isync
+
+	/* DBAT 5 */
+	lis   	r4, CFG_DBAT5L@h
+	ori     r4, r4, CFG_DBAT5L@l
+	lis   	r3, CFG_DBAT5U@h
+	ori     r3, r3, CFG_DBAT5U@l
+	mtspr   DBAT5L, r4
+	mtspr   DBAT5U, r3
+	isync
+
+	/* IBAT 6 */
+	lis   	r4, CFG_IBAT6L@h
+	ori     r4, r4, CFG_IBAT6L@l
+	lis	r3, CFG_IBAT6U@h
+	ori     r3, r3, CFG_IBAT6U@l
+	mtspr   IBAT6L, r4
+	mtspr   IBAT6U, r3
 	isync
 
+	/* DBAT 6 */
+	lis   	r4, CFG_DBAT6L@h
+	ori     r4, r4, CFG_DBAT6L@l
+	lis   	r3, CFG_DBAT6U@h
+	ori     r3, r3, CFG_DBAT6U@l
+	mtspr   DBAT6L, r4
+	mtspr   DBAT6U, r3
+	isync
+	blr
+
+	.globl clear_tlbs
+clear_tlbs:
+	addis   r3, 0, 0x0000
+	addis   r5, 0, 0x4
+	isync
 tlblp:
-	tlbie	r3
+	tlbie   r3
 	sync
-	addi	r3, r3, 0x1000
-	cmp	0, 0, r3, r5
+	addi    r3, r3, 0x1000
+	cmp     0, 0, r3, r5
 	blt tlblp
-
 	blr
 
 	.globl enable_addr_trans