diff options
author | wdenk <wdenk> | 2003-03-26 06:55:25 +0000 |
---|---|---|
committer | wdenk <wdenk> | 2003-03-26 06:55:25 +0000 |
commit | dc7c9a1a52403093b9e4aef14ac4c5c014386e57 (patch) | |
tree | 4ca643323e3e7c96efd12190ec9bf10142acb375 /cpu/sa1100 | |
parent | 10f670178cce29d7f078ca622f0eeafd6903748a (diff) |
* Patch by Rick Bronson, 16 Mar 2003:
Add support for Atmel AT91RM9200DK w/NAND
* Patches by Robert Schwebel, 19 Mar 2003:
- use arm-linux-gcc as default compiler for ARM
- fix i2c fixup code
- fix missing baudrate setting
- added $loadaddr / CFG_LOAD_ADDR support to loadb
- moved "ignoring trailing characters" _before_ u-boot wants to
print out diagnostics messages; removes bogus characters at the
end of transmission
* Patch by John Zhan, 18 Mar 2003:
Add support for SinoVee Microsystems SC8xx boards
* Patch by Rolf Offermanns, 21 Mar 2003:
ported the dnp1110 related changes from the current armboot cvs to
current u-boot cvs. smc91111 does not work. problem marked in
smc91111.c, grep for "FIXME".
* Patch by Brian Auld, 25 Mar 2003:
Add support for STM flash chips on ebony board
* Add PCI support for MPC8250 Boards (PM825 module)
* Patch by Stefan Roese, 25 Mar 2003:
Diffstat (limited to 'cpu/sa1100')
-rw-r--r-- | cpu/sa1100/serial.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/cpu/sa1100/serial.c b/cpu/sa1100/serial.c index 68bcd1f2a40..d3b8628245e 100644 --- a/cpu/sa1100/serial.c +++ b/cpu/sa1100/serial.c @@ -53,17 +53,19 @@ void serial_setbrg (void) hang (); #ifdef CONFIG_SERIAL1 + /* SA1110 uart function */ + Ser1SDCR0 |= SDCR0_SUS; + /* Wait until port is ready ... */ - while (Ser1UTSR1 & UTSR1_TBY) { - } + while(Ser1UTSR1 & UTSR1_TBY) {} /* init serial serial 1 */ Ser1UTCR3 = 0x00; Ser1UTSR0 = 0xff; - Ser1UTCR0 = (UTCR0_1StpBit | UTCR0_8BitData); + Ser1UTCR0 = ( UTCR0_1StpBit | UTCR0_8BitData ); Ser1UTCR1 = 0; - Ser1UTCR2 = (u32) reg; - Ser1UTCR3 = (UTCR3_RXE | UTCR3_TXE); + Ser1UTCR2 = (u32)reg; + Ser1UTCR3 = ( UTCR3_RXE | UTCR3_TXE ); #elif CONFIG_SERIAL3 /* Wait until port is ready ... */ while (Ser3UTSR1 & UTSR1_TBY) { |