Merge branch 'master' of git://git.denx.de/u-boot-arm

6 files changed, 122 insertions, 151 deletions

diff --git a/cpu/arm925t/interrupts.c b/cpu/arm925t/interrupts.c
index e5c77f7a0fc..ec2a9789d32 100644
--- a/cpu/arm925t/interrupts.c
+++ b/cpu/arm925t/interrupts.c
@@ -1,4 +1,7 @@
 /*
+ * (C) Copyright 2009
+ * 2N Telekomunikace, <www.2n.cz>
+ *
  * (C) Copyright 2003
  * Texas Instruments, <www.ti.com>
  *
@@ -37,7 +40,8 @@
 #include <configs/omap1510.h>
 #include <asm/io.h>
 
-#define TIMER_LOAD_VAL 0xffffffff
+#define TIMER_LOAD_VAL	0xffffffff
+#define TIMER_CLOCK	(CONFIG_SYS_CLK_FREQ / (2 << CONFIG_SYS_PTV))
 
 static uint32_t timestamp;
 static uint32_t lastdec;
@@ -79,85 +83,41 @@ void set_timer (ulong t)
 /* delay x useconds AND preserve advance timestamp value */
 void udelay (unsigned long usec)
 {
-	ulong tmo, tmp;
-
-	if (usec >= 1000) {		/* if "big" number, spread normalization to seconds */
-		tmo = usec / 1000;	/* start to normalize for usec to ticks per sec */
-		tmo *= CONFIG_SYS_HZ;	/* find number of "ticks" to wait to achieve target */
-		tmo /= 1000;		/* finish normalize. */
-	} else {			/* else small number, don't kill it prior to HZ multiply */
-		tmo = usec * CONFIG_SYS_HZ;
-		tmo /= (1000*1000);
+	int32_t tmo = usec * (TIMER_CLOCK / 1000) / 1000;
+	uint32_t now, last = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM);
+
+	while (tmo > 0) {
+		now = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM);
+		if (last < now) /* count down timer underflow */
+			tmo -= TIMER_LOAD_VAL - now + last;
+		else
+			tmo -= last - now;
+		last = now;
 	}
-
-	tmp = get_timer (0);		/* get current timestamp */
-	if ((tmo + tmp + 1) < tmp)	/* if setting this fordward will roll time stamp */
-		reset_timer_masked ();	/* reset "advancing" timestamp to 0, set lastdec value */
-	else
-		tmo += tmp;		/* else, set advancing stamp wake up time */
-
-	while (get_timer_masked () < tmo) /* loop till event */
-		/*NOP*/;
 }
 
 void reset_timer_masked (void)
 {
 	/* reset time */
-	lastdec = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM);
+	lastdec = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM) /
+			(TIMER_CLOCK / CONFIG_SYS_HZ);
 	timestamp = 0;	       /* start "advancing" time stamp from 0 */
 }
 
 ulong get_timer_masked (void)
 {
-	uint32_t now = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM);
-
-	if (lastdec >= now) {		/* normal mode (non roll) */
-		/* normal mode */
-		timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */
-	} else {			/* we have overflow of the count down timer */
-		/* nts = ts + ld + (TLV - now)
-		 * ts=old stamp, ld=time that passed before passing through -1
-		 * (TLV-now) amount of time after passing though -1
-		 * nts = new "advancing time stamp"...it could also roll and cause problems.
-		 */
-		timestamp += lastdec + TIMER_LOAD_VAL - now;
-	}
+	uint32_t now = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM) /
+			(TIMER_CLOCK / CONFIG_SYS_HZ);
+	if (lastdec < now)	/* count down timer underflow */
+		timestamp += TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ) -
+				now + lastdec;
+	else
+		timestamp += lastdec - now;
 	lastdec = now;
 
 	return timestamp;
 }
 
-/* waits specified delay value and resets timestamp */
-void udelay_masked (unsigned long usec)
-{
-#ifdef CONFIG_INNOVATOROMAP1510
-	#define LOOPS_PER_MSEC 60 /* tuned on omap1510 */
-	volatile int i, time_remaining = LOOPS_PER_MSEC*usec;
-	for (i=time_remaining; i>0; i--) { }
-#else
-
-	ulong tmo;
-	ulong endtime;
-	signed long diff;
-
-	if (usec >= 1000) {		/* if "big" number, spread normalization to seconds */
-		tmo = usec / 1000;	/* start to normalize for usec to ticks per sec */
-		tmo *= CONFIG_SYS_HZ;	/* find number of "ticks" to wait to achieve target */
-		tmo /= 1000;		/* finish normalize. */
-	} else {			/* else small number, don't kill it prior to HZ multiply */
-		tmo = usec * CONFIG_SYS_HZ;
-		tmo /= (1000*1000);
-	}
-
-	endtime = get_timer_masked () + tmo;
-
-	do {
-		ulong now = get_timer_masked ();
-		diff = endtime - now;
-	} while (diff >= 0);
-#endif
-}
-
 /*
  * This function is derived from PowerPC code (read timebase as long long).
  * On ARM it just returns the timer value.
diff --git a/cpu/arm926ejs/at91/clock.c b/cpu/arm926ejs/at91/clock.c
index 31e53b30dd3..f776f70b115 100644
--- a/cpu/arm926ejs/at91/clock.c
+++ b/cpu/arm926ejs/at91/clock.c
@@ -126,6 +126,7 @@ static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
 fail:
 	return 0;
 }
+#endif
 
 static u32 at91_pll_rate(u32 freq, u32 reg)
 {
@@ -141,7 +142,6 @@ static u32 at91_pll_rate(u32 freq, u32 reg)
 
 	return freq;
 }
-#endif
 
 int at91_clock_init(unsigned long main_clock)
 {
diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c
index 5e7b935e4b9..3e1780b31d8 100644
--- a/cpu/arm_cortexa8/cpu.c
+++ b/cpu/arm_cortexa8/cpu.c
@@ -101,7 +101,7 @@ void l2cache_enable()
 	volatile unsigned int j;
 
 	/* ES2 onwards we can disable/enable L2 ourselves */
-	if (get_cpu_rev() == CPU_3430_ES2) {
+	if (get_cpu_rev() >= CPU_3XX_ES20) {
 		__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
 		__asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
 		__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
@@ -131,7 +131,7 @@ void l2cache_disable()
 	volatile unsigned int j;
 
 	/* ES2 onwards we can disable/enable L2 ourselves */
-	if (get_cpu_rev() == CPU_3430_ES2) {
+	if (get_cpu_rev() >= CPU_3XX_ES20) {
 		__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
 		__asm__ __volatile__("bic %0, %0, #0x2":"=r"(i));
 		__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c
index 15ea936b406..51d5cf636fe 100644
--- a/cpu/arm_cortexa8/omap3/board.c
+++ b/cpu/arm_cortexa8/omap3/board.c
@@ -39,6 +39,8 @@
 
 extern omap3_sysinfo sysinfo;
 
+extern u32 is_mem_sdr(void);
+
 /******************************************************************************
  * Routine: delay
  * Description: spinning delay to use before udelay works
@@ -272,11 +274,6 @@ int dram_init(void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 	unsigned int size0 = 0, size1 = 0;
-	u32 btype;
-
-	btype = get_board_type();
-
-	display_board_info(btype);
 
 	/*
 	 * If a second bank of DDR is attached to CS1 this is
@@ -342,3 +339,23 @@ U_BOOT_CMD(
 	);
 
 #endif /* CONFIG_NAND_OMAP_GPMC */
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+/**
+ * Print board information
+ */
+int checkboard (void)
+{
+	char *mem_s ;
+
+	if (is_mem_sdr())
+		mem_s = "mSDR";
+	else
+		mem_s = "LPDDR";
+
+	printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
+			sysinfo.nand_string);
+
+	return 0;
+}
+#endif	/* CONFIG_DISPLAY_BOARDINFO */
diff --git a/cpu/arm_cortexa8/omap3/clock.c b/cpu/arm_cortexa8/omap3/clock.c
index 8ac31bec2f9..d035677857f 100644
--- a/cpu/arm_cortexa8/omap3/clock.c
+++ b/cpu/arm_cortexa8/omap3/clock.c
@@ -132,7 +132,7 @@ void prcm_init(void)
 	void (*f_lock_pll) (u32, u32, u32, u32);
 	int xip_safe, p0, p1, p2, p3;
 	u32 osc_clk = 0, sys_clkin_sel;
-	u32 clk_index, sil_index;
+	u32 clk_index, sil_index = 0;
 	prm_t *prm_base = (prm_t *)PRM_BASE;
 	prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
 	dpll_param *dpll_param_p;
@@ -170,7 +170,8 @@ void prcm_init(void)
 	 * and sil_index will get the values for that SysClk for the
 	 * appropriate silicon rev.
 	 */
-	sil_index = get_cpu_rev() - 1;
+	if (get_cpu_rev())
+		sil_index = 1;
 
 	/* Unlock MPU DPLL (slows things down, and needed later) */
 	sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
diff --git a/cpu/arm_cortexa8/omap3/sys_info.c b/cpu/arm_cortexa8/omap3/sys_info.c
index b385b912b43..2f04cd6d970 100644
--- a/cpu/arm_cortexa8/omap3/sys_info.c
+++ b/cpu/arm_cortexa8/omap3/sys_info.c
@@ -35,6 +35,12 @@ extern omap3_sysinfo sysinfo;
 static gpmc_csx_t *gpmc_cs_base = (gpmc_csx_t *)GPMC_CONFIG_CS0_BASE;
 static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE;
 static ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
+static char *rev_s[CPU_3XX_MAX_REV] = {
+				"1.0",
+				"2.0",
+				"2.1",
+				"3.0",
+				"3.1"};
 
 /*****************************************************************
  * dieid_num_r(void) - read and set die ID
@@ -76,18 +82,27 @@ u32 get_cpu_type(void)
 u32 get_cpu_rev(void)
 {
 	u32 cpuid = 0;
+	ctrl_id_t *id_base;
 
 	/*
 	 * On ES1.0 the IDCODE register is not exposed on L4
-	 * so using CPU ID to differentiate
-	 * between ES2.0 and ES1.0.
+	 * so using CPU ID to differentiate between ES1.0 and > ES1.0.
 	 */
 	__asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
 	if ((cpuid & 0xf) == 0x0)
-		return CPU_3430_ES1;
-	else
-		return CPU_3430_ES2;
+		return CPU_3XX_ES10;
+	else {
+		/* Decode the IDs on > ES1.0 */
+		id_base = (ctrl_id_t *) OMAP34XX_ID_L4_IO_BASE;
 
+		cpuid = (readl(&id_base->idcode) >> CPU_3XX_ID_SHIFT) & 0xf;
+
+		/* Some early ES2.0 seem to report ID 0, fix this */
+		if(cpuid == 0)
+			cpuid = CPU_3XX_ES20;
+
+		return cpuid;
+	}
 }
 
 /****************************************************
@@ -130,23 +145,6 @@ u32 get_sdr_cs_offset(u32 cs)
 	return offset;
 }
 
-/***********************************************************************
- * get_board_type() - get board type based on current production stats.
- *  - NOTE-1-: 2 I2C EEPROMs will someday be populated with proper info.
- *    when they are available we can get info from there.  This should
- *    be correct of all known boards up until today.
- *  - NOTE-2- EEPROMs are populated but they are updated very slowly.  To
- *    avoid waiting on them we will use ES version of the chip to get info.
- *    A later version of the FPGA migth solve their speed issue.
- ************************************************************************/
-u32 get_board_type(void)
-{
-	if (get_cpu_rev() == CPU_3430_ES2)
-		return sysinfo.board_type_v2;
-	else
-		return sysinfo.board_type_v1;
-}
-
 /***************************************************************************
  *  get_gpmc0_base() - Return current address hardware will be
  *     fetching from. The below effectively gives what is correct, its a bit
@@ -185,61 +183,6 @@ u32 get_board_rev(void)
 	return 0x20;
 }
 
-/*********************************************************************
- *  display_board_info() - print banner with board info.
- *********************************************************************/
-void display_board_info(u32 btype)
-{
-	char *cpu_s, *mem_s, *sec_s;
-
-	switch (get_cpu_type()) {
-	case OMAP3503:
-		cpu_s = "3503";
-		break;
-	case OMAP3515:
-		cpu_s = "3515";
-		break;
-	case OMAP3525:
-		cpu_s = "3525";
-		break;
-	case OMAP3530:
-		cpu_s = "3530";
-		break;
-	default:
-		cpu_s = "35XX";
-		break;
-	}
-
-	if (is_mem_sdr())
-		mem_s = "mSDR";
-	else
-		mem_s = "LPDDR";
-
-	switch (get_device_type()) {
-	case TST_DEVICE:
-		sec_s = "TST";
-		break;
-	case EMU_DEVICE:
-		sec_s = "EMU";
-		break;
-	case HS_DEVICE:
-		sec_s = "HS";
-		break;
-	case GP_DEVICE:
-		sec_s = "GP";
-		break;
-	default:
-		sec_s = "?";
-	}
-
-
-	printf("OMAP%s-%s rev %d, CPU-OPP2 L3-165MHz\n", cpu_s,
-	       sec_s, get_cpu_rev());
-	printf("%s + %s/%s\n", sysinfo.board_string,
-	       mem_s, sysinfo.nand_string);
-
-}
-
 /********************************************************
  *  get_base(); get upper addr of current execution
  *******************************************************/
@@ -305,3 +248,53 @@ u32 get_device_type(void)
 {
 	return ((readl(&ctrl_base->status) & (DEVICE_MASK)) >> 8);
 }
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+/**
+ * Print CPU information
+ */
+int print_cpuinfo (void)
+{
+	char *cpu_s, *sec_s;
+
+	switch (get_cpu_type()) {
+	case OMAP3503:
+		cpu_s = "3503";
+		break;
+	case OMAP3515:
+		cpu_s = "3515";
+		break;
+	case OMAP3525:
+		cpu_s = "3525";
+		break;
+	case OMAP3530:
+		cpu_s = "3530";
+		break;
+	default:
+		cpu_s = "35XX";
+		break;
+	}
+
+	switch (get_device_type()) {
+	case TST_DEVICE:
+		sec_s = "TST";
+		break;
+	case EMU_DEVICE:
+		sec_s = "EMU";
+		break;
+	case HS_DEVICE:
+		sec_s = "HS";
+		break;
+	case GP_DEVICE:
+		sec_s = "GP";
+		break;
+	default:
+		sec_s = "?";
+	}
+
+	printf("OMAP%s-%s ES%s, CPU-OPP2 L3-165MHz\n",
+			cpu_s, sec_s, rev_s[get_cpu_rev()]);
+
+	return 0;
+}
+#endif	/* CONFIG_DISPLAY_CPUINFO */