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| author | Sudhakar Rajashekhara <sudhakar.raj@ti.com> | 2010-11-03 13:15:23 +0530 |
|---|---|---|
| committer | Sudhakar Rajashekhara <sudhakar.raj@ti.com> | 2010-11-03 13:15:23 +0530 |
| commit | eab9d7e640fd85ebdafb31e57255c8a21149c7a8 (patch) | |
| tree | 7ad22931f1eb5aea6061f9e867b60fbee38ea8bc /doc/README.JFFS2_NAND | |
| parent | 978955ff4a9771e888b3e99039513fc5f671c419 (diff) | |
da8xx/omap-l1: modifications for Logic PD Rev.3 AM18xx EVM2009.11-omapl138-201011030745
AHCLKR/UART1_RTS/GP0[11] pin needs to be configured for
MMC and NOR to work on Rev.3 EVM. When GP0[11] is low,
the SD0 interface will not work, but NOR flash will. When
GP0[11] is high, SD0 will work but NOR flash will not.
Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Diffstat (limited to 'doc/README.JFFS2_NAND')
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