Prepare v2012.04-rc2; minor Coding Style cleanupv2012.04-rc2

Signed-off-by: Wolfgang Denk <wd@denx.de>

1 files changed, 14 insertions, 14 deletions

diff --git a/doc/README.sbc8548 b/doc/README.sbc8548
index 0f3f5432f26..feac5e3e63e 100644
--- a/doc/README.sbc8548
+++ b/doc/README.sbc8548
@@ -23,7 +23,7 @@ of each choice are listed below.
 
 Choice #1 does not enable CONFIG_PCI, and assumes that the PCI slot
 will be left empty (M66EN high), and so the board will operate with
-a base clock of 66MHz.  Note that you need both PCI enabled in u-boot
+a base clock of 66MHz.	Note that you need both PCI enabled in u-boot
 and linux in order to have functional PCI under linux.
 
 The second enables PCI support and builds for a 33MHz clock rate.  Note
@@ -37,29 +37,29 @@ card. [The above discussion assumes that the SW2[1-4] has not been changed
 to reflect a different CCB:SYSCLK ratio]
 
 The third option builds PCI support in, and leaves the clocking at the
-default 66MHz.  Options four and five are just repeats of option two
+default 66MHz.	Options four and five are just repeats of option two
 and three, but with PCI-e support enabled as well.
 
 PCI output listing with an intel e1000 PCI-x and a Syskonnect SK-9Exx
-is shown below for sbc8548_PCI_66_PCIE_config.  (Note that PCI-e with
+is shown below for sbc8548_PCI_66_PCIE_config.	(Note that PCI-e with
 a 33MHz PCI configuration is currently untested.)
 
     => pci 0
     Scanning PCI devices on bus 0
-    BusDevFun  VendorId   DeviceId   Device Class       Sub-Class
+    BusDevFun  VendorId	  DeviceId   Device Class	Sub-Class
     _____________________________________________________________
-    00.00.00   0x1057     0x0012     Processor               0x20
-    00.01.00   0x8086     0x1026     Network controller      0x00
+    00.00.00   0x1057	  0x0012     Processor		     0x20
+    00.01.00   0x8086	  0x1026     Network controller	     0x00
     => pci 1
     Scanning PCI devices on bus 1
-    BusDevFun  VendorId   DeviceId   Device Class       Sub-Class
+    BusDevFun  VendorId	  DeviceId   Device Class	Sub-Class
     _____________________________________________________________
-    01.00.00   0x1957     0x0012     Processor               0x20
+    01.00.00   0x1957	  0x0012     Processor		     0x20
     => pci 2
     Scanning PCI devices on bus 2
-    BusDevFun  VendorId   DeviceId   Device Class       Sub-Class
+    BusDevFun  VendorId	  DeviceId   Device Class	Sub-Class
     _____________________________________________________________
-    02.00.00   0x1148     0x9e00     Network controller      0x00
+    02.00.00   0x1148	  0x9e00     Network controller	     0x00
     =>
 
 Memory Size and using SPD:
@@ -80,10 +80,10 @@ You can also visually inspect the board to see if this hardware
 fix has been applied:
 
       1) Remove R314 (RES-R0174-033, 1K, 0603). R314 is located on
-         the back of the PCB behind the DDR SDRAM SODIMM connector.
+	 the back of the PCB behind the DDR SDRAM SODIMM connector.
       2) Solder RES-R0174-033 (1K, 0603) resistor from R314 pin 2 pad
-         to R313 pin 2.  Pin 2 for each resistor is the end of the
-         resistor closest to the CPU.
+	 to R313 pin 2.	 Pin 2 for each resistor is the end of the
+	 resistor closest to the CPU.
 
 Boards without the mod will have R314 and R313 in parallel, like "||".
 After the mod, they will be touching and form an "L" shape.
@@ -155,7 +155,7 @@ Hardware Reference:
 ===================
 
 The following contains some summary information on hardware settings
-that are relevant to u-boot, based on the board manual.  For the
+that are relevant to u-boot, based on the board manual.	 For the
 most up to date and complete details of the board, please request the
 reference manual ERG-00327-001.pdf from www.windriver.com