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authorSimon Glass <sjg@chromium.org>2014-10-13 23:42:00 -0600
committerSimon Glass <sjg@chromium.org>2014-10-22 10:36:48 -0600
commit623b638607aa00dad85cee36e229011c79b249ce (patch)
tree4c27026c7806a865949d7c42f617f14566a55919 /doc
parent44ba6b0eccb37dd98becece22632bcc5e5cd2fbe (diff)
dm: spi: Add soft_spi implementation
Add a new implementation of soft_spi that uses device tree to specify the GPIOs. This will replace soft_spi_legacy for boards which use driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Diffstat (limited to 'doc')
-rw-r--r--doc/device-tree-bindings/spi/soft-spi.txt34
1 files changed, 34 insertions, 0 deletions
diff --git a/doc/device-tree-bindings/spi/soft-spi.txt b/doc/device-tree-bindings/spi/soft-spi.txt
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+Soft SPI
+
+The soft SPI bus implementation allows the use of GPIO pins to simulate a
+SPI bus. No SPI host is required for this to work. The down-side is that the
+performance will typically be much lower than a real SPI bus.
+
+The soft SPI node requires the following properties:
+
+compatible: "u-boot,soft-spi"
+soft_spi_cs: GPIO number to use for SPI chip select (output)
+soft_spi_sclk: GPIO number to use for SPI clock (output)
+soft_spi_mosi: GPIO number to use for SPI MOSI line (output)
+soft_spi_miso GPIO number to use for SPI MISO line (input)
+spi-delay-us: Number of microseconds of delay between each CS transition
+
+The GPIOs should be specified as required by the GPIO controller referenced.
+The first cell holds the phandle of the controller and the second cell
+typically holds the GPIO number.
+
+
+Example:
+
+ soft-spi {
+ compatible = "u-boot,soft-spi";
+ cs-gpio = <&gpio 235 0>; /* Y43 */
+ sclk-gpio = <&gpio 225 0>; /* Y31 */
+ mosi-gpio = <&gpio 227 0>; /* Y33 */
+ miso-gpio = <&gpio 224 0>; /* Y30 */
+ spi-delay-us = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cs@0 {
+ };
+ };