diff options
| author | Tom Rini <trini@konsulko.com> | 2024-05-30 07:23:30 -0600 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-05-30 07:23:30 -0600 |
| commit | c2d15c4b7996520614c5025b37fd6d38c70600c8 (patch) | |
| tree | e74b40f573d6e174af10503e886f581c6eafd28f /drivers/cache/cache-andes-l2.c | |
| parent | b1d2af984f5baa7440f6cc409efa6f0561415800 (diff) | |
| parent | 1d29c718b7ba09807f8060796d9c21772e3c1b52 (diff) | |
Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
- board: fix support for icicle
- board: support Star64 board
- andes: minor fixes
- riscv: deprecate cache enablement in start.S
Diffstat (limited to 'drivers/cache/cache-andes-l2.c')
| -rw-r--r-- | drivers/cache/cache-andes-l2.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/drivers/cache/cache-andes-l2.c b/drivers/cache/cache-andes-l2.c index 45d29f2fbd9..bc6f7ed7c1e 100644 --- a/drivers/cache/cache-andes-l2.c +++ b/drivers/cache/cache-andes-l2.c @@ -30,7 +30,7 @@ struct l2cache { volatile u64 cctl_command2; volatile u64 cctl_access_line2; volatile u64 cctl_command3; - volatile u64 cctl_access_line4; + volatile u64 cctl_access_line3; volatile u64 cctl_status; }; @@ -97,13 +97,15 @@ static int andes_l2_disable(struct udevice *dev) struct andes_l2_plat *plat = dev_get_plat(dev); volatile struct l2cache *regs = plat->regs; u8 hart = gd->arch.boot_hart; + void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(regs, hart); + void __iomem *cctlstatus = (void __iomem *)CCTL_STATUS_REG(regs, hart); if ((regs) && (readl(®s->control) & L2_ENABLE)) { writel(L2_WBINVAL_ALL, cctlcmd); - while ((readl(®s->cctl_status) & CCTL_STATUS_MSK(hart))) { - if ((readl(®s->cctl_status) & CCTL_STATUS_ILLEGAL(hart))) { + while ((readl(cctlstatus) & CCTL_STATUS_MSK(hart))) { + if ((readl(cctlstatus) & CCTL_STATUS_ILLEGAL(hart))) { printf("L2 flush illegal! hanging..."); hang(); } |