diff options
| author | Michal Simek <michal.simek@xilinx.com> | 2021-02-09 15:28:15 +0100 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2021-02-23 14:56:59 +0100 |
| commit | 9b7aac75365b68bae2e8f7cf074ba95638d31882 (patch) | |
| tree | 9d2ee4b001275fe6a2191ead6ec3913e033a783d /drivers/clk | |
| parent | 3aba25bc382beeb8a92b46d23fd1db47dfcb1121 (diff) | |
clk: zynq: Add dummy clock enable function
A lot of Xilinx drivers are checking -ENOSYS which means that clock driver
doesn't have enable function. Remove this checking from drivers and create
dummy enable function as was done for clk_fixed_rate driver by
commit 6bf6d81c1112 ("clk: fixed_rate: add dummy enable() function").
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/clk_zynq.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/clk/clk_zynq.c b/drivers/clk/clk_zynq.c index bf32d8317ab..1f71b7d1e4f 100644 --- a/drivers/clk/clk_zynq.c +++ b/drivers/clk/clk_zynq.c @@ -444,11 +444,21 @@ static ulong zynq_clk_get_rate(struct clk *clk) } #endif +static int dummy_enable(struct clk *clk) +{ + /* + * Add implementation but by default all clocks are enabled + * after power up which is only one supported case now. + */ + return 0; +} + static struct clk_ops zynq_clk_ops = { .get_rate = zynq_clk_get_rate, #ifndef CONFIG_SPL_BUILD .set_rate = zynq_clk_set_rate, #endif + .enable = dummy_enable, }; static int zynq_clk_probe(struct udevice *dev) |