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| author | Tien Fong Chee <tien.fong.chee@intel.com> | 2025-02-18 16:34:54 +0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2025-02-25 10:53:48 -0600 |
| commit | e3097ca2bbdef182ac4e162387a4d1e92c625007 (patch) | |
| tree | 22fd31ba28e39ef170ff177d053413c876b6908b /drivers/ddr/altera/sdram_agilex.c | |
| parent | b833de8d42663e157ce0039c5a7771f5d4aef11e (diff) | |
arm: dts: agilex5: Add HPS cache coherency unit configuration settings
These configuration settings are required to enable cache maintenance and
access between initiators and targets.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Diffstat (limited to 'drivers/ddr/altera/sdram_agilex.c')
0 files changed, 0 insertions, 0 deletions