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| author | Marek Vasut <marek.vasut+renesas@mailbox.org> | 2025-06-30 20:51:13 +0200 |
|---|---|---|
| committer | Marek Vasut <marek.vasut+renesas@mailbox.org> | 2025-07-10 19:26:55 +0200 |
| commit | 787dafb15a8ea2bcbeabaf68a3c87ac80b814390 (patch) | |
| tree | eb231baa17de2b13447cbaf4478113467aef5fdb /drivers/ddr/marvell/axp/ddr3_hw_training.c | |
| parent | 16a900210956fe7c476b2355c7090c2cc078f71d (diff) | |
net: sh_eth: arm: renesas: README: Drop CFG_SH_ETHER_CACHE_*
Drop CFG_SH_ETHER_CACHE_WRITEBACK and CFG_SH_ETHER_CACHE_INVALIDATE,
which are now always enabled in the sh_eth driver, because those cache
operations are always available. On architectures which do not implement
cache operations yet, cache operations have to be implemented first.
CFG_SH_ETHER_ALIGNE_SIZE now set as SH_ETHER_ALIGN_SIZE in sh_eth.h
based on architecture and no longer configured on board level.
Remove CFG_SH_ETHER_CACHE_WRITEBACK configuration option from README.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Diffstat (limited to 'drivers/ddr/marvell/axp/ddr3_hw_training.c')
0 files changed, 0 insertions, 0 deletions