Merge git://git.denx.de/u-boot-fsl-qoriq

trini: Drop local memset() from
examples/standalone/mem_to_mem_idma2intr.c

Signed-off-by: Tom Rini <trini@konsulko.com>

4 files changed, 213 insertions, 40 deletions

diff --git a/drivers/ddr/fsl/Makefile b/drivers/ddr/fsl/Makefile
index 01ea86217c0..00dea428e3a 100644
--- a/drivers/ddr/fsl/Makefile
+++ b/drivers/ddr/fsl/Makefile
@@ -33,3 +33,4 @@ obj-$(CONFIG_SYS_FSL_DDRC_GEN3)	+= mpc85xx_ddr_gen3.o
 obj-$(CONFIG_SYS_FSL_DDR_86XX)		+= mpc86xx_ddr.o
 obj-$(CONFIG_SYS_FSL_DDRC_ARM_GEN3)	+= arm_ddr_gen3.o
 obj-$(CONFIG_SYS_FSL_DDRC_GEN4) += fsl_ddr_gen4.o
+obj-$(CONFIG_SYS_FSL_MMDC) += fsl_mmdc.o
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index d37e2474c91..042af09770f 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -50,8 +50,13 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	u32 temp_sdram_cfg;
 	u32 total_gb_size_per_controller;
 	int timeout;
+#if defined(CONFIG_SYS_FSL_ERRATUM_A008511) || \
+	defined(CONFIG_SYS_FSL_ERRATUM_A009801)
+	u32 temp32;
+#endif
+
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
-	u32 temp32, mr6;
+	u32 mr6;
 	u32 vref_seq1[3] = {0x80, 0x96, 0x16};	/* for range 1 */
 	u32 vref_seq2[3] = {0xc0, 0xf0, 0x70};	/* for range 2 */
 	u32 *vref_seq = vref_seq1;
@@ -218,7 +223,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	ddr_out32(&ddr->err_disable, regs->err_disable);
 #endif
 	ddr_out32(&ddr->err_int_en, regs->err_int_en);
-	for (i = 0; i < 32; i++) {
+	for (i = 0; i < 64; i++) {
 		if (regs->debug[i]) {
 			debug("Write to debug_%d as %08x\n",
 			      i+1, regs->debug[i]);
@@ -238,7 +243,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
 	/* Part 1 of 2 */
-	/* This erraum only applies to verion 5.2.0 */
 	if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
 		/* Disable DRAM VRef training */
 		ddr_out32(&ddr->ddr_cdr2,
@@ -247,13 +251,25 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 		temp32 = ddr_in32(&ddr->debug[28]);
 		temp32 |= DDR_TX_BD_DIS;
 		ddr_out32(&ddr->debug[28], temp32);
-		/* Disable D_INIT */
-		ddr_out32(&ddr->sdram_cfg_2,
-			  regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
 		ddr_out32(&ddr->debug[25], 0x9000);
+	} else if (fsl_ddr_get_version(ctrl_num) == 0x50201) {
+		/* Output enable forced off */
+		ddr_out32(&ddr->debug[37], 1 << 31);
+		/* Enable Vref training */
+		ddr_out32(&ddr->ddr_cdr2,
+			  regs->ddr_cdr2 | DDR_CDR2_VREF_TRAIN_EN);
+	} else {
+		debug("Erratum A008511 doesn't apply.\n");
 	}
 #endif
 
+#if defined(CONFIG_SYS_FSL_ERRATUM_A009803) || \
+	defined(CONFIG_SYS_FSL_ERRATUM_A008511)
+	/* Disable D_INIT */
+	ddr_out32(&ddr->sdram_cfg_2,
+		  regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
+#endif
+
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009801
 	temp32 = ddr_in32(&ddr->debug[25]);
 	temp32 &= ~DDR_CAS_TO_PRE_SUB_MASK;
@@ -331,21 +347,21 @@ step2:
 #if defined(CONFIG_SYS_FSL_ERRATUM_A008511) || \
 	defined(CONFIG_SYS_FSL_ERRATUM_A009803)
 	/* Part 2 of 2 */
-	/* This erraum only applies to verion 5.2.0 */
-	if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
-		/* Wait for idle */
-		timeout = 40;
-		while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
-		       (timeout > 0)) {
-			udelay(1000);
-			timeout--;
-		}
-		if (timeout <= 0) {
-			printf("Controler %d timeout, debug_2 = %x\n",
-			       ctrl_num, ddr_in32(&ddr->debug[1]));
-		}
+	timeout = 40;
+	/* Wait for idle. D_INIT needs to be cleared earlier, or timeout */
+	while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
+	       (timeout > 0)) {
+		udelay(1000);
+		timeout--;
+	}
+	if (timeout <= 0) {
+		printf("Controler %d timeout, debug_2 = %x\n",
+		       ctrl_num, ddr_in32(&ddr->debug[1]));
+	}
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
+	/* This erraum only applies to verion 5.2.0 */
+	if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
 		/* The vref setting sequence is different for range 2 */
 		if (regs->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
 			vref_seq = vref_seq2;
@@ -392,32 +408,32 @@ step2:
 			printf("Controler %d timeout, debug_2 = %x\n",
 			       ctrl_num, ddr_in32(&ddr->debug[1]));
 		}
-		/* Restore D_INIT */
-		ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
+	}
 #endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803
-		if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
-			/* if it's RDIMM */
-			if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) {
-				for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-					if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
-						continue;
-					set_wait_for_bits_clear(&ddr->sdram_md_cntl,
-								MD_CNTL_MD_EN |
-								MD_CNTL_CS_SEL(i) |
-								0x070000ed,
-								MD_CNTL_MD_EN);
-					udelay(1);
-				}
+	if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
+		/* if it's RDIMM */
+		if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) {
+			for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+				if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
+					continue;
+				set_wait_for_bits_clear(&ddr->sdram_md_cntl,
+							MD_CNTL_MD_EN |
+							MD_CNTL_CS_SEL(i) |
+							0x070000ed,
+							MD_CNTL_MD_EN);
+				udelay(1);
 			}
-
-			ddr_out32(&ddr->err_disable,
-				  regs->err_disable & ~DDR_ERR_DISABLE_APED);
 		}
-#endif
+
+		ddr_out32(&ddr->err_disable,
+			  regs->err_disable & ~DDR_ERR_DISABLE_APED);
 	}
 #endif
+	/* Restore D_INIT */
+	ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
+#endif
 
 	total_gb_size_per_controller = 0;
 	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
diff --git a/drivers/ddr/fsl/fsl_mmdc.c b/drivers/ddr/fsl/fsl_mmdc.c
new file mode 100644
index 00000000000..52eec0f9e99
--- /dev/null
+++ b/drivers/ddr/fsl/fsl_mmdc.c
@@ -0,0 +1,156 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/*
+ * Generic driver for Freescale MMDC(Multi Mode DDR Controller).
+ */
+
+#include <common.h>
+#include <fsl_mmdc.h>
+#include <asm/io.h>
+
+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
+{
+	int timeout = 1000;
+
+	out_be32(ptr, value);
+
+	while (in_be32(ptr) & bits) {
+		udelay(100);
+		timeout--;
+	}
+	if (timeout <= 0)
+		printf("Error: %p wait for clear timeout.\n", ptr);
+}
+
+void mmdc_init(const struct fsl_mmdc_info *priv)
+{
+	struct mmdc_regs *mmdc = (struct mmdc_regs *)CONFIG_SYS_FSL_DDR_ADDR;
+	unsigned int tmp;
+
+	/* 1. set configuration request */
+	out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ);
+
+	/* 2. configure the desired timing parameters */
+	out_be32(&mmdc->mdotc, priv->mdotc);
+	out_be32(&mmdc->mdcfg0, priv->mdcfg0);
+	out_be32(&mmdc->mdcfg1, priv->mdcfg1);
+	out_be32(&mmdc->mdcfg2, priv->mdcfg2);
+
+	/* 3. configure DDR type and other miscellaneous parameters */
+	out_be32(&mmdc->mdmisc, priv->mdmisc);
+	out_be32(&mmdc->mpmur0,	MMDC_MPMUR0_FRC_MSR);
+	out_be32(&mmdc->mdrwd, priv->mdrwd);
+	out_be32(&mmdc->mpodtctrl, priv->mpodtctrl);
+
+	/* 4. configure the required delay while leaving reset */
+	out_be32(&mmdc->mdor, priv->mdor);
+
+	/* 5. configure DDR physical parameters */
+	/* set row/column address width, burst length, data bus width */
+	tmp = priv->mdctl & ~(MDCTL_SDE0 | MDCTL_SDE1);
+	out_be32(&mmdc->mdctl, tmp);
+	/* configure address space partition */
+	out_be32(&mmdc->mdasp, priv->mdasp);
+
+	/* 6. perform a ZQ calibration - not needed here, doing in #8b */
+
+	/* 7. enable MMDC with the desired chip select */
+#if (CONFIG_CHIP_SELECTS_PER_CTRL == 1)
+		out_be32(&mmdc->mdctl, tmp | MDCTL_SDE0);
+#elif (CONFIG_CHIP_SELECTS_PER_CTRL == 2)
+		out_be32(&mmdc->mdctl, tmp | MDCTL_SDE0 | MDCTL_SDE1);
+#endif
+
+	/* 8a. dram init sequence: update MRs for ZQ, ODT, PRE, etc */
+	out_be32(&mmdc->mdscr,  CMD_ADDR_LSB_MR_ADDR(8) | MDSCR_ENABLE_CON_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2);
+
+	out_be32(&mmdc->mdscr,  CMD_ADDR_LSB_MR_ADDR(0) | MDSCR_ENABLE_CON_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3);
+
+	out_be32(&mmdc->mdscr,  CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1);
+
+	out_be32(&mmdc->mdscr,  CMD_ADDR_MSB_MR_OP(0x19) |
+				CMD_ADDR_LSB_MR_ADDR(0x30) |
+				MDSCR_ENABLE_CON_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0);
+
+	/* 8b. ZQ calibration */
+	out_be32(&mmdc->mdscr,  CMD_ADDR_MSB_MR_OP(0x4) | MDSCR_ENABLE_CON_REQ |
+				CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0);
+
+	set_wait_for_bits_clear(&mmdc->mpzqhwctrl, priv->mpzqhwctrl,
+				MPZQHWCTRL_ZQ_HW_FORCE);
+
+	/* 9a. calibrations now, wr lvl */
+	out_be32(&mmdc->mdscr,  CMD_ADDR_LSB_MR_ADDR(0x84) |
+				MDSCR_ENABLE_CON_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1);
+
+	out_be32(&mmdc->mdscr,  MDSCR_ENABLE_CON_REQ | MDSCR_WL_EN |
+				CMD_NORMAL);
+
+	set_wait_for_bits_clear(&mmdc->mpwlgcr, MPWLGCR_HW_WL_EN,
+				MPWLGCR_HW_WL_EN);
+
+	mdelay(1);
+
+	out_be32(&mmdc->mdscr,  CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1);
+	out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ);
+
+	mdelay(1);
+
+	/* 9b. read DQS gating calibration */
+	out_be32(&mmdc->mdscr,  CMD_ADDR_MSB_MR_OP(4) | MDSCR_ENABLE_CON_REQ |
+				CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0);
+
+	out_be32(&mmdc->mdscr,  CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3);
+
+	out_be32(&mmdc->mppdcmpr2, MPPDCMPR2_MPR_COMPARE_EN);
+
+	/* set absolute read delay offset */
+	if (priv->mprddlctl)
+		out_be32(&mmdc->mprddlctl, priv->mprddlctl);
+	else
+		out_be32(&mmdc->mprddlctl, MMDC_MPRDDLCTL_DEFAULT_DELAY);
+
+	set_wait_for_bits_clear(&mmdc->mpdgctrl0,
+				AUTO_RD_DQS_GATING_CALIBRATION_EN,
+				AUTO_RD_DQS_GATING_CALIBRATION_EN);
+
+	out_be32(&mmdc->mdscr,  MDSCR_ENABLE_CON_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_3);
+
+	/* 9c. read calibration */
+	out_be32(&mmdc->mdscr,  CMD_ADDR_MSB_MR_OP(4) | MDSCR_ENABLE_CON_REQ |
+				CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0);
+	out_be32(&mmdc->mdscr,  CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3);
+	out_be32(&mmdc->mppdcmpr2,  MPPDCMPR2_MPR_COMPARE_EN);
+	set_wait_for_bits_clear(&mmdc->mprddlhwctl,
+				MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN,
+				MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN);
+
+	out_be32(&mmdc->mdscr,  MDSCR_ENABLE_CON_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_3);
+
+	/* 10. configure power-down, self-refresh entry, exit parameters */
+	out_be32(&mmdc->mdpdc, priv->mdpdc);
+	out_be32(&mmdc->mapsr, MMDC_MAPSR_PWR_SAV_CTRL_STAT);
+
+	/* 11. ZQ config again? do nothing here */
+
+	/* 12. refresh scheme */
+	set_wait_for_bits_clear(&mmdc->mdref, priv->mdref,
+				MDREF_START_REFRESH);
+
+	/* 13. disable CON_REQ */
+	out_be32(&mmdc->mdscr, MDSCR_DISABLE_CFG_REQ);
+}
diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c
index d23e6e5b977..49352b30fb7 100644
--- a/drivers/ddr/fsl/interactive.c
+++ b/drivers/ddr/fsl/interactive.c
@@ -670,7 +670,7 @@ static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
 
 	print_option_table(options, n_opts, ddr);
 
-	for (i = 0; i < 32; i++)
+	for (i = 0; i < 64; i++)
 		printf("debug_%02d = 0x%08X\n", i+1, ddr->debug[i]);
 }
 
@@ -771,7 +771,7 @@ static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo,
 	if (handle_option_table(options, n_opts, ddr, regname, value_str))
 		return;
 
-	for (i = 0; i < 32; i++) {
+	for (i = 0; i < 64; i++) {
 		unsigned int value = simple_strtoul(value_str, NULL, 0);
 		sprintf(buf, "debug_%u", i + 1);
 		if (strcmp(buf, regname) == 0) {