diff options
| author | Wolfgang Denk <wd@denx.de> | 2010-01-12 23:47:03 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2010-01-12 23:47:03 +0100 |
| commit | 2ff6922280025c1315c53fa2eb4ab33f0c9591de (patch) | |
| tree | 8061843b797eac0669f51b3b14d361bdae1dbe3b /drivers/mtd/nand | |
| parent | f8b365ceb64e0b86bea243d783ff94687302cba9 (diff) | |
| parent | 06f95959bc5421e516a9a25012e303dea8833385 (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-arm
Diffstat (limited to 'drivers/mtd/nand')
| -rw-r--r-- | drivers/mtd/nand/davinci_nand.c | 27 |
1 files changed, 13 insertions, 14 deletions
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index d3c6e51ba80..bfc2acf59e7 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -179,26 +179,21 @@ static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int c static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode) { - int dummy; + u_int32_t val; - dummy = emif_regs->NANDF1ECC; + (void)readl(&(emif_regs->NANDFECC[CONFIG_SYS_NAND_CS - 2])); - /* FIXME: only chipselect 0 is supported for now */ - emif_regs->NANDFCR |= 1 << 8; + val = readl(&emif_regs->NANDFCR); + val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS); + val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS); + writel(val, &emif_regs->NANDFCR); } static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region) { u_int32_t ecc = 0; - if (region == 1) - ecc = emif_regs->NANDF1ECC; - else if (region == 2) - ecc = emif_regs->NANDF2ECC; - else if (region == 3) - ecc = emif_regs->NANDF3ECC; - else if (region == 4) - ecc = emif_regs->NANDF4ECC; + ecc = readl(&(emif_regs->NANDFECC[region - 1])); return(ecc); } @@ -320,8 +315,12 @@ static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode) * Start a new ECC calculation for reading or writing 512 bytes * of data. */ - val = (emif_regs->NANDFCR & ~(3 << 4)) | (1 << 12); - emif_regs->NANDFCR = val; + val = readl(&emif_regs->NANDFCR); + val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK; + val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS); + val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS); + val |= DAVINCI_NANDFCR_4BIT_ECC_START; + writel(val, &emif_regs->NANDFCR); break; case NAND_ECC_READSYN: val = emif_regs->NAND4BITECC1; |