Merge branch 'master' of git://git.denx.de/u-boot-net

1 files changed, 780 insertions, 784 deletions

diff --git a/drivers/net/enc28j60.c b/drivers/net/enc28j60.c
index 3238a502ca7..6c161b632f4 100644
--- a/drivers/net/enc28j60.c
+++ b/drivers/net/enc28j60.c
@@ -1,4 +1,9 @@
 /*
+ * (C) Copyright 2010
+ * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
+ * Martin Krause, Martin.Krause@tqs.de
+ * reworked original enc28j60.c
+ *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
@@ -6,7 +11,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -15,968 +20,959 @@
  * MA 02111-1307 USA
  */
 
-#include <config.h>
 #include <common.h>
 #include <net.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spi.h>
-
-/*
- * Control Registers in Bank 0
- */
-
-#define CTL_REG_ERDPTL	 0x00
-#define CTL_REG_ERDPTH	 0x01
-#define CTL_REG_EWRPTL	 0x02
-#define CTL_REG_EWRPTH	 0x03
-#define CTL_REG_ETXSTL	 0x04
-#define CTL_REG_ETXSTH	 0x05
-#define CTL_REG_ETXNDL	 0x06
-#define CTL_REG_ETXNDH	 0x07
-#define CTL_REG_ERXSTL	 0x08
-#define CTL_REG_ERXSTH	 0x09
-#define CTL_REG_ERXNDL	 0x0A
-#define CTL_REG_ERXNDH	 0x0B
-#define CTL_REG_ERXRDPTL 0x0C
-#define CTL_REG_ERXRDPTH 0x0D
-#define CTL_REG_ERXWRPTL 0x0E
-#define CTL_REG_ERXWRPTH 0x0F
-#define CTL_REG_EDMASTL  0x10
-#define CTL_REG_EDMASTH  0x11
-#define CTL_REG_EDMANDL  0x12
-#define CTL_REG_EDMANDH  0x13
-#define CTL_REG_EDMADSTL 0x14
-#define CTL_REG_EDMADSTH 0x15
-#define CTL_REG_EDMACSL  0x16
-#define CTL_REG_EDMACSH  0x17
-/* these are common in all banks */
-#define CTL_REG_EIE	 0x1B
-#define CTL_REG_EIR	 0x1C
-#define CTL_REG_ESTAT	 0x1D
-#define CTL_REG_ECON2	 0x1E
-#define CTL_REG_ECON1	 0x1F
-
-/*
- * Control Registers in Bank 1
- */
-
-#define CTL_REG_EHT0	0x00
-#define CTL_REG_EHT1	0x01
-#define CTL_REG_EHT2	0x02
-#define CTL_REG_EHT3	0x03
-#define CTL_REG_EHT4	0x04
-#define CTL_REG_EHT5	0x05
-#define CTL_REG_EHT6	0x06
-#define CTL_REG_EHT7	0x07
-#define CTL_REG_EPMM0	0x08
-#define CTL_REG_EPMM1	0x09
-#define CTL_REG_EPMM2	0x0A
-#define CTL_REG_EPMM3	0x0B
-#define CTL_REG_EPMM4	0x0C
-#define CTL_REG_EPMM5	0x0D
-#define CTL_REG_EPMM6	0x0E
-#define CTL_REG_EPMM7	0x0F
-#define CTL_REG_EPMCSL	0x10
-#define CTL_REG_EPMCSH	0x11
-#define CTL_REG_EPMOL	0x14
-#define CTL_REG_EPMOH	0x15
-#define CTL_REG_EWOLIE	0x16
-#define CTL_REG_EWOLIR	0x17
-#define CTL_REG_ERXFCON 0x18
-#define CTL_REG_EPKTCNT 0x19
-
-/*
- * Control Registers in Bank 2
- */
-
-#define CTL_REG_MACON1	 0x00
-#define CTL_REG_MACON2	 0x01
-#define CTL_REG_MACON3	 0x02
-#define CTL_REG_MACON4	 0x03
-#define CTL_REG_MABBIPG  0x04
-#define CTL_REG_MAIPGL	 0x06
-#define CTL_REG_MAIPGH	 0x07
-#define CTL_REG_MACLCON1 0x08
-#define CTL_REG_MACLCON2 0x09
-#define CTL_REG_MAMXFLL  0x0A
-#define CTL_REG_MAMXFLH  0x0B
-#define CTL_REG_MAPHSUP  0x0D
-#define CTL_REG_MICON	 0x11
-#define CTL_REG_MICMD	 0x12
-#define CTL_REG_MIREGADR 0x14
-#define CTL_REG_MIWRL	 0x16
-#define CTL_REG_MIWRH	 0x17
-#define CTL_REG_MIRDL	 0x18
-#define CTL_REG_MIRDH	 0x19
-
-/*
- * Control Registers in Bank 3
- */
-
-#define CTL_REG_MAADR1	0x00
-#define CTL_REG_MAADR0	0x01
-#define CTL_REG_MAADR3	0x02
-#define CTL_REG_MAADR2	0x03
-#define CTL_REG_MAADR5	0x04
-#define CTL_REG_MAADR4	0x05
-#define CTL_REG_EBSTSD	0x06
-#define CTL_REG_EBSTCON 0x07
-#define CTL_REG_EBSTCSL 0x08
-#define CTL_REG_EBSTCSH 0x09
-#define CTL_REG_MISTAT	0x0A
-#define CTL_REG_EREVID	0x12
-#define CTL_REG_ECOCON	0x15
-#define CTL_REG_EFLOCON 0x17
-#define CTL_REG_EPAUSL	0x18
-#define CTL_REG_EPAUSH	0x19
-
-
-/*
- * PHY Register
- */
-
-#define PHY_REG_PHID1 0x02
-#define PHY_REG_PHID2 0x03
-/* taken from the Linux driver */
-#define PHY_REG_PHCON1 0x00
-#define PHY_REG_PHCON2 0x10
-#define PHY_REG_PHLCON 0x14
-
-/*
- * Receive Filter Register (ERXFCON) bits
- */
-
-#define ENC_RFR_UCEN  0x80
-#define ENC_RFR_ANDOR 0x40
-#define ENC_RFR_CRCEN 0x20
-#define ENC_RFR_PMEN  0x10
-#define ENC_RFR_MPEN  0x08
-#define ENC_RFR_HTEN  0x04
-#define ENC_RFR_MCEN  0x02
-#define ENC_RFR_BCEN  0x01
+#include <spi.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include "enc28j60.h"
 
 /*
- * ECON1 Register Bits
+ * IMPORTANT: spi_claim_bus() and spi_release_bus()
+ * are called at begin and end of each of the following functions:
+ * enc_miiphy_read(), enc_miiphy_write(), enc_write_hwaddr(),
+ * enc_init(), enc_recv(), enc_send(), enc_halt()
+ * ALL other functions assume that the bus has already been claimed!
+ * Since NetReceive() might call enc_send() in return, the bus must be
+ * released, NetReceive() called and claimed again.
  */
 
-#define ENC_ECON1_TXRST  0x80
-#define ENC_ECON1_RXRST  0x40
-#define ENC_ECON1_DMAST  0x20
-#define ENC_ECON1_CSUMEN 0x10
-#define ENC_ECON1_TXRTS  0x08
-#define ENC_ECON1_RXEN	 0x04
-#define ENC_ECON1_BSEL1  0x02
-#define ENC_ECON1_BSEL0  0x01
-
 /*
- * ECON2 Register Bits
+ * Controller memory layout.
+ * We only allow 1 frame for transmission and reserve the rest
+ * for reception to handle as many broadcast packets as possible.
+ * Also use the memory from 0x0000 for receiver buffer. See errata pt. 5
+ * 0x0000 - 0x19ff 6656 bytes receive buffer
+ * 0x1a00 - 0x1fff 1536 bytes transmit buffer =
+ * control(1)+frame(1518)+status(7)+reserve(10).
  */
-#define ENC_ECON2_AUTOINC 0x80
-#define ENC_ECON2_PKTDEC  0x40
-#define ENC_ECON2_PWRSV   0x20
-#define ENC_ECON2_VRPS	  0x08
+#define ENC_RX_BUF_START	0x0000
+#define ENC_RX_BUF_END		0x19ff
+#define ENC_TX_BUF_START	0x1a00
+#define ENC_TX_BUF_END		0x1fff
+#define ENC_MAX_FRM_LEN		1518
+#define RX_RESET_COUNTER	1000
 
 /*
- * EIR Register Bits
+ * For non data transfer functions, like phy read/write, set hwaddr, init
+ * we do not need a full, time consuming init including link ready wait.
+ * This enum helps to bring the chip through the minimum necessary inits.
  */
-#define ENC_EIR_PKTIF  0x40
-#define ENC_EIR_DMAIF  0x20
-#define ENC_EIR_LINKIF 0x10
-#define ENC_EIR_TXIF   0x08
-#define ENC_EIR_WOLIF  0x04
-#define ENC_EIR_TXERIF 0x02
-#define ENC_EIR_RXERIF 0x01
+enum enc_initstate {none=0, setupdone, linkready};
+typedef struct enc_device {
+	struct eth_device	*dev;	/* back pointer */
+	struct spi_slave	*slave;
+	int			rx_reset_counter;
+	u16			next_pointer;
+	u8			bank;	/* current bank in enc28j60 */
+	enum enc_initstate	initstate;
+} enc_dev_t;
 
 /*
- * ESTAT Register Bits
+ * enc_bset:		set bits in a common register
+ * enc_bclr:		clear bits in a common register
+ *
+ * making the reg parameter u8 will give a compile time warning if the
+ * functions are called with a register not accessible in all Banks
  */
+static void enc_bset(enc_dev_t *enc, const u8 reg, const u8 data)
+{
+	u8 dout[2];
 
-#define ENC_ESTAT_INT	  0x80
-#define ENC_ESTAT_LATECOL 0x10
-#define ENC_ESTAT_RXBUSY  0x04
-#define ENC_ESTAT_TXABRT  0x02
-#define ENC_ESTAT_CLKRDY  0x01
+	dout[0] = CMD_BFS(reg);
+	dout[1] = data;
+	spi_xfer(enc->slave, 2 * 8, dout, NULL,
+		SPI_XFER_BEGIN | SPI_XFER_END);
+}
 
-/*
- * EIE Register Bits
- */
+static void enc_bclr(enc_dev_t *enc, const u8 reg, const u8 data)
+{
+	u8 dout[2];
 
-#define ENC_EIE_INTIE  0x80
-#define ENC_EIE_PKTIE  0x40
-#define ENC_EIE_DMAIE  0x20
-#define ENC_EIE_LINKIE 0x10
-#define ENC_EIE_TXIE   0x08
-#define ENC_EIE_WOLIE  0x04
-#define ENC_EIE_TXERIE 0x02
-#define ENC_EIE_RXERIE 0x01
+	dout[0] = CMD_BFC(reg);
+	dout[1] = data;
+	spi_xfer(enc->slave, 2 * 8, dout, NULL,
+		SPI_XFER_BEGIN | SPI_XFER_END);
+}
 
 /*
- * MACON1 Register Bits
+ * high byte of the register contains bank number:
+ * 0: no bank switch necessary
+ * 1: switch to bank 0
+ * 2: switch to bank 1
+ * 3: switch to bank 2
+ * 4: switch to bank 3
  */
-#define ENC_MACON1_LOOPBK  0x10
-#define ENC_MACON1_TXPAUS  0x08
-#define ENC_MACON1_RXPAUS  0x04
-#define ENC_MACON1_PASSALL 0x02
-#define ENC_MACON1_MARXEN  0x01
-
+static void enc_set_bank(enc_dev_t *enc, const u16 reg)
+{
+	u8 newbank = reg >> 8;
+
+	if (newbank == 0 || newbank == enc->bank)
+		return;
+	switch (newbank) {
+	case 1:
+		enc_bclr(enc, CTL_REG_ECON1,
+			ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1);
+		break;
+	case 2:
+		enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_BSEL0);
+		enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_BSEL1);
+		break;
+	case 3:
+		enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_BSEL0);
+		enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_BSEL1);
+		break;
+	case 4:
+		enc_bset(enc, CTL_REG_ECON1,
+			ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1);
+		break;
+	}
+	enc->bank = newbank;
+}
 
 /*
- * MACON2 Register Bits
+ * local functions to access SPI
+ *
+ * reg: register inside ENC28J60
+ * data: 8/16 bits to write
+ * c: number of retries
+ *
+ * enc_r8:		read 8 bits
+ * enc_r16:		read 16 bits
+ * enc_w8:		write 8 bits
+ * enc_w16:		write 16 bits
+ * enc_w8_retry:	write 8 bits, verify and retry
+ * enc_rbuf:		read from ENC28J60 into buffer
+ * enc_wbuf:		write from buffer into ENC28J60
  */
-#define ENC_MACON2_MARST   0x80
-#define ENC_MACON2_RNDRST  0x40
-#define ENC_MACON2_MARXRST 0x08
-#define ENC_MACON2_RFUNRST 0x04
-#define ENC_MACON2_MATXRST 0x02
-#define ENC_MACON2_TFUNRST 0x01
 
 /*
- * MACON3 Register Bits
+ * MAC and MII registers need a 3 byte SPI transfer to read,
+ * all other registers need a 2 byte SPI transfer.
  */
-#define ENC_MACON3_PADCFG2 0x80
-#define ENC_MACON3_PADCFG1 0x40
-#define ENC_MACON3_PADCFG0 0x20
-#define ENC_MACON3_TXCRCEN 0x10
-#define ENC_MACON3_PHDRLEN 0x08
-#define ENC_MACON3_HFRMEN  0x04
-#define ENC_MACON3_FRMLNEN 0x02
-#define ENC_MACON3_FULDPX  0x01
+static int enc_reg2nbytes(const u16 reg)
+{
+	/* check if MAC or MII register */
+	return ((reg >= CTL_REG_MACON1 && reg <= CTL_REG_MIRDH) ||
+		(reg >= CTL_REG_MAADR1 && reg <= CTL_REG_MAADR4) ||
+		(reg == CTL_REG_MISTAT)) ? 3 : 2;
+}
 
 /*
- * MICMD Register Bits
+ * Read a byte register
  */
-#define ENC_MICMD_MIISCAN 0x02
-#define ENC_MICMD_MIIRD   0x01
+static u8 enc_r8(enc_dev_t *enc, const u16 reg)
+{
+	u8 dout[3];
+	u8 din[3];
+	int nbytes = enc_reg2nbytes(reg);
+
+	enc_set_bank(enc, reg);
+	dout[0] = CMD_RCR(reg);
+	spi_xfer(enc->slave, nbytes * 8, dout, din,
+		SPI_XFER_BEGIN | SPI_XFER_END);
+	return din[nbytes-1];
+}
 
 /*
- * MISTAT Register Bits
+ * Read a L/H register pair and return a word.
+ * Must be called with the L register's address.
  */
-#define ENC_MISTAT_NVALID 0x04
-#define ENC_MISTAT_SCAN   0x02
-#define ENC_MISTAT_BUSY   0x01
+static u16 enc_r16(enc_dev_t *enc, const u16 reg)
+{
+	u8 dout[3];
+	u8 din[3];
+	u16 result;
+	int nbytes = enc_reg2nbytes(reg);
+
+	enc_set_bank(enc, reg);
+	dout[0] = CMD_RCR(reg);
+	spi_xfer(enc->slave, nbytes * 8, dout, din,
+		SPI_XFER_BEGIN | SPI_XFER_END);
+	result = din[nbytes-1];
+	dout[0]++; /* next register */
+	spi_xfer(enc->slave, nbytes * 8, dout, din,
+		SPI_XFER_BEGIN | SPI_XFER_END);
+	result |= din[nbytes-1] << 8;
+	return result;
+}
 
 /*
- * PHID1 and PHID2 values
+ * Write a byte register
  */
-#define ENC_PHID1_VALUE 0x0083
-#define ENC_PHID2_VALUE 0x1400
-#define ENC_PHID2_MASK	0xFC00
-
-
-#define ENC_SPI_SLAVE_CS 0x00010000	/* pin P1.16 */
-#define ENC_RESET	 0x00020000	/* pin P1.17 */
+static void enc_w8(enc_dev_t *enc, const u16 reg, const u8 data)
+{
+	u8 dout[2];
 
-#define FAILSAFE_VALUE 5000
+	enc_set_bank(enc, reg);
+	dout[0] = CMD_WCR(reg);
+	dout[1] = data;
+	spi_xfer(enc->slave, 2 * 8, dout, NULL,
+		SPI_XFER_BEGIN | SPI_XFER_END);
+}
 
 /*
- * Controller memory layout:
- *
- * 0x0000 - 0x17ff  6k bytes receive buffer
- * 0x1800 - 0x1fff  2k bytes transmit buffer
- */
-/* Use the lower memory for receiver buffer. See errata pt. 5 */
-#define ENC_RX_BUF_START 0x0000
-#define ENC_TX_BUF_START 0x1800
-/* taken from the Linux driver */
-#define ENC_RX_BUF_END   0x17ff
-#define ENC_TX_BUF_END   0x1fff
-
-/* maximum frame length */
-#define ENC_MAX_FRM_LEN 1518
-
-#define enc_enable() PUT32(IO1CLR, ENC_SPI_SLAVE_CS)
-#define enc_disable() PUT32(IO1SET, ENC_SPI_SLAVE_CS)
-#define enc_cfg_spi() spi_set_cfg(0, 0, 0); spi_set_clock(8);
-
-
-static unsigned char encReadReg (unsigned char regNo);
-static void encWriteReg (unsigned char regNo, unsigned char data);
-static void encWriteRegRetry (unsigned char regNo, unsigned char data, int c);
-static void encReadBuff (unsigned short length, unsigned char *pBuff);
-static void encWriteBuff (unsigned short length, unsigned char *pBuff);
-static void encBitSet (unsigned char regNo, unsigned char data);
-static void encBitClr (unsigned char regNo, unsigned char data);
-static void encReset (void);
-static void encInit (unsigned char *pEthAddr);
-static unsigned short phyRead (unsigned char addr);
-static void phyWrite(unsigned char, unsigned short);
-static void encPoll (void);
-static void encRx (void);
-
-#define m_nic_read(reg) encReadReg(reg)
-#define m_nic_write(reg, data) encWriteReg(reg, data)
-#define m_nic_write_retry(reg, data, count) encWriteRegRetry(reg, data, count)
-#define m_nic_read_data(len, buf) encReadBuff((len), (buf))
-#define m_nic_write_data(len, buf) encWriteBuff((len), (buf))
-
-/* bit field set */
-#define m_nic_bfs(reg, data) encBitSet(reg, data)
-
-/* bit field clear */
-#define m_nic_bfc(reg, data) encBitClr(reg, data)
-
-static unsigned char bank = 0;	/* current bank in enc28j60 */
-static unsigned char next_pointer_lsb;
-static unsigned char next_pointer_msb;
-
-static unsigned char buffer[ENC_MAX_FRM_LEN];
-static int rxResetCounter = 0;
-
-#define RX_RESET_COUNTER 1000;
-
-/*-----------------------------------------------------------------------------
- * Always returns 0
+ * Write a L/H register pair.
+ * Must be called with the L register's address.
  */
-int eth_init (bd_t * bis)
+static void enc_w16(enc_dev_t *enc, const u16 reg, const u16 data)
 {
-	unsigned char estatVal;
-	uchar enetaddr[6];
-
-	/* configure GPIO */
-	(*((volatile unsigned long *) IO1DIR)) |= ENC_SPI_SLAVE_CS;
-	(*((volatile unsigned long *) IO1DIR)) |= ENC_RESET;
-
-	/* CS and RESET active low */
-	PUT32 (IO1SET, ENC_SPI_SLAVE_CS);
-	PUT32 (IO1SET, ENC_RESET);
-
-	spi_init ();
-
-	/* taken from the Linux driver - dangerous stuff here! */
-	/* Wait for CLKRDY to become set (i.e., check that we can communicate with
-	   the ENC) */
-	do
-	{
-		estatVal = m_nic_read(CTL_REG_ESTAT);
-	} while ((estatVal & 0x08) || (~estatVal & ENC_ESTAT_CLKRDY));
-
-	/* initialize controller */
-	encReset ();
-	eth_getenv_enetaddr("ethaddr", enetaddr);
-	encInit (enetaddr);
-
-	m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXEN);	/* enable receive */
-
-	return 0;
+	u8 dout[2];
+
+	enc_set_bank(enc, reg);
+	dout[0] = CMD_WCR(reg);
+	dout[1] = data;
+	spi_xfer(enc->slave, 2 * 8, dout, NULL,
+		SPI_XFER_BEGIN | SPI_XFER_END);
+	dout[0]++; /* next register */
+	dout[1] = data >> 8;
+	spi_xfer(enc->slave, 2 * 8, dout, NULL,
+		SPI_XFER_BEGIN | SPI_XFER_END);
 }
 
-int eth_send (volatile void *packet, int length)
+/*
+ * Write a byte register, verify and retry
+ */
+static void enc_w8_retry(enc_dev_t *enc, const u16 reg, const u8 data, const int c)
 {
-	/* check frame length, etc. */
-	/* TODO: */
-
-	/* switch to bank 0 */
-	m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
-
-	/* set EWRPT */
-	m_nic_write (CTL_REG_EWRPTL, (ENC_TX_BUF_START & 0xff));
-	m_nic_write (CTL_REG_EWRPTH, (ENC_TX_BUF_START >> 8));
-
-	/* set ETXND */
-	m_nic_write (CTL_REG_ETXNDL, (length + ENC_TX_BUF_START) & 0xFF);
-	m_nic_write (CTL_REG_ETXNDH, (length + ENC_TX_BUF_START) >> 8);
-
-	/* set ETXST */
-	m_nic_write (CTL_REG_ETXSTL, ENC_TX_BUF_START & 0xFF);
-	m_nic_write (CTL_REG_ETXSTH, ENC_TX_BUF_START >> 8);
-
-	/* write packet */
-	m_nic_write_data (length, (unsigned char *) packet);
+	u8 dout[2];
+	u8 readback;
+	int i;
 
-	/* taken from the Linux driver */
-	/* Verify that the internal transmit logic has not been altered by excessive
-	   collisions.  See Errata B4 12 and 14.
-	 */
-	if (m_nic_read(CTL_REG_EIR) & ENC_EIR_TXERIF) {
-		m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_TXRST);
-		m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_TXRST);
+	enc_set_bank(enc, reg);
+	for (i = 0; i < c; i++) {
+		dout[0] = CMD_WCR(reg);
+		dout[1] = data;
+		spi_xfer(enc->slave, 2 * 8, dout, NULL,
+			SPI_XFER_BEGIN | SPI_XFER_END);
+		readback = enc_r8(enc, reg);
+		if (readback == data)
+			break;
+		/* wait 1ms */
+		udelay(1000);
+	}
+	if (i == c) {
+		printf("%s: write reg 0x%03x failed\n", enc->dev->name, reg);
 	}
-	m_nic_bfc(CTL_REG_EIR, (ENC_EIR_TXERIF | ENC_EIR_TXIF));
-
-	/* set ECON1.TXRTS */
-	m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_TXRTS);
-
-	return 0;
 }
 
-
-/*****************************************************************************
- * This function resets the receiver only. This function may be called from
- * interrupt-context.
+/*
+ * Read ENC RAM into buffer
  */
-static void encReceiverReset (void)
+static void enc_rbuf(enc_dev_t *enc, const u16 length, u8 *buf)
 {
-	unsigned char econ1;
-
-	econ1 = m_nic_read (CTL_REG_ECON1);
-	if ((econ1 & ENC_ECON1_RXRST) == 0) {
-		m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXRST);
-		rxResetCounter = RX_RESET_COUNTER;
-	}
+	u8 dout[1];
+
+	dout[0] = CMD_RBM;
+	spi_xfer(enc->slave, 8, dout, NULL, SPI_XFER_BEGIN);
+	spi_xfer(enc->slave, length * 8, NULL, buf, SPI_XFER_END);
+#ifdef DEBUG
+	puts("Rx:\n");
+	print_buffer(0, buf, 1, length, 0);
+#endif
 }
 
-/*****************************************************************************
- * receiver reset timer
+/*
+ * Write buffer into ENC RAM
  */
-static void encReceiverResetCallback (void)
+static void enc_wbuf(enc_dev_t *enc, const u16 length, const u8 *buf, const u8 control)
 {
-	m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_RXRST);
-	m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXEN);	/* enable receive */
+	u8 dout[2];
+	dout[0] = CMD_WBM;
+	dout[1] = control;
+	spi_xfer(enc->slave, 2 * 8, dout, NULL, SPI_XFER_BEGIN);
+	spi_xfer(enc->slave, length * 8, buf, NULL, SPI_XFER_END);
+#ifdef DEBUG
+	puts("Tx:\n");
+	print_buffer(0, buf, 1, length, 0);
+#endif
 }
 
-/*-----------------------------------------------------------------------------
- * Check for received packets. Call NetReceive for each packet. The return
- * value is ignored by the caller.
+/*
+ * Try to claim the SPI bus.
+ * Print error message on failure.
  */
-int eth_rx (void)
+static int enc_claim_bus(enc_dev_t *enc)
 {
-	if (rxResetCounter > 0 && --rxResetCounter == 0) {
-		encReceiverResetCallback ();
-	}
-
-	encPoll ();
-
-	return 0;
+	int rc = spi_claim_bus(enc->slave);
+	if (rc)
+		printf("%s: failed to claim SPI bus\n", enc->dev->name);
+	return rc;
 }
 
-void eth_halt (void)
+/*
+ * Release previously claimed SPI bus.
+ * This function is mainly for symmetry to enc_claim_bus().
+ * Let the toolchain decide to inline it...
+ */
+static void enc_release_bus(enc_dev_t *enc)
 {
-	m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_RXEN);	/* disable receive */
+	spi_release_bus(enc->slave);
 }
 
-/*****************************************************************************/
-
-static void encPoll (void)
+/*
+ * Read PHY register
+ */
+static u16 phy_read(enc_dev_t *enc, const u8 addr)
 {
-	unsigned char eir_reg;
-	volatile unsigned char estat_reg;
-	unsigned char pkt_cnt;
+	uint64_t etime;
+	u8 status;
 
-#ifdef CONFIG_USE_IRQ
-	/* clear global interrupt enable bit in enc28j60 */
-	m_nic_bfc (CTL_REG_EIE, ENC_EIE_INTIE);
-#endif
-	estat_reg = m_nic_read (CTL_REG_ESTAT);
-
-	eir_reg = m_nic_read (CTL_REG_EIR);
-
-	if (eir_reg & ENC_EIR_TXIF) {
-		/* clear TXIF bit in EIR */
-		m_nic_bfc (CTL_REG_EIR, ENC_EIR_TXIF);
+	enc_w8(enc, CTL_REG_MIREGADR, addr);
+	enc_w8(enc, CTL_REG_MICMD, ENC_MICMD_MIIRD);
+	/* 1 second timeout - only happens on hardware problem */
+	etime = get_ticks() + get_tbclk();
+	/* poll MISTAT.BUSY bit until operation is complete */
+	do
+	{
+		status = enc_r8(enc, CTL_REG_MISTAT);
+	} while (get_ticks() <= etime && (status & ENC_MISTAT_BUSY));
+	if (status & ENC_MISTAT_BUSY) {
+		printf("%s: timeout reading phy\n", enc->dev->name);
+		return 0;
 	}
+	enc_w8(enc, CTL_REG_MICMD, 0);
+	return enc_r16(enc, CTL_REG_MIRDL);
+}
 
-	/* We have to use pktcnt and not pktif bit, see errata pt. 6 */
+/*
+ * Write PHY register
+ */
+static void phy_write(enc_dev_t *enc, const u8 addr, const u16 data)
+{
+	uint64_t etime;
+	u8 status;
 
-	/* move to bank 1 */
-	m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1);
-	m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0);
+	enc_w8(enc, CTL_REG_MIREGADR, addr);
+	enc_w16(enc, CTL_REG_MIWRL, data);
+	/* 1 second timeout - only happens on hardware problem */
+	etime = get_ticks() + get_tbclk();
+	/* poll MISTAT.BUSY bit until operation is complete */
+	do
+	{
+		status = enc_r8(enc, CTL_REG_MISTAT);
+	} while (get_ticks() <= etime && (status & ENC_MISTAT_BUSY));
+	if (status & ENC_MISTAT_BUSY) {
+		printf("%s: timeout writing phy\n", enc->dev->name);
+		return;
+	}
+}
 
-	/* read pktcnt */
-	pkt_cnt = m_nic_read (CTL_REG_EPKTCNT);
+/*
+ * Verify link status, wait if necessary
+ *
+ * Note: with a 10 MBit/s only PHY there is no autonegotiation possible,
+ * half/full duplex is a pure setup matter. For the time being, this driver
+ * will setup in half duplex mode only.
+ */
+static int enc_phy_link_wait(enc_dev_t *enc)
+{
+	u16 status;
+	int duplex;
+	uint64_t etime;
+
+#ifdef CONFIG_ENC_SILENTLINK
+	/* check if we have a link, then just return */
+	status = phy_read(enc, PHY_REG_PHSTAT1);
+	if (status & ENC_PHSTAT1_LLSTAT)
+		return 0;
+#endif
 
-	if (pkt_cnt > 0) {
-		if ((eir_reg & ENC_EIR_PKTIF) == 0) {
-			/*printf("encPoll: pkt cnt > 0, but pktif not set\n"); */
+	/* wait for link with 1 second timeout */
+	etime = get_ticks() + get_tbclk();
+	while (get_ticks() <= etime) {
+		status = phy_read(enc, PHY_REG_PHSTAT1);
+		if (status & ENC_PHSTAT1_LLSTAT) {
+			/* now we have a link */
+			status = phy_read(enc, PHY_REG_PHSTAT2);
+			duplex = (status & ENC_PHSTAT2_DPXSTAT) ? 1 : 0;
+			printf("%s: link up, 10Mbps %s-duplex\n",
+				enc->dev->name, duplex ? "full" : "half");
+			return 0;
 		}
-		encRx ();
-		/* clear PKTIF bit in EIR, this should not need to be done but it
-		   seems like we get problems if we do not */
-		m_nic_bfc (CTL_REG_EIR, ENC_EIR_PKTIF);
+		udelay(1000);
 	}
 
-	if (eir_reg & ENC_EIR_RXERIF) {
-		printf ("encPoll: rx error\n");
-		m_nic_bfc (CTL_REG_EIR, ENC_EIR_RXERIF);
-	}
-	if (eir_reg & ENC_EIR_TXERIF) {
-		printf ("encPoll: tx error\n");
-		m_nic_bfc (CTL_REG_EIR, ENC_EIR_TXERIF);
-	}
-
-#ifdef CONFIG_USE_IRQ
-	/* set global interrupt enable bit in enc28j60 */
-	m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE);
-#endif
+	/* timeout occured */
+	printf("%s: link down\n", enc->dev->name);
+	return 1;
 }
 
-static void encRx (void)
+/*
+ * This function resets the receiver only.
+ */
+static void enc_reset_rx(enc_dev_t *enc)
 {
-	unsigned short pkt_len;
-	unsigned short copy_len;
-	unsigned short status;
-	unsigned char eir_reg;
-	unsigned char pkt_cnt = 0;
-	unsigned short rxbuf_rdpt;
+	u8 econ1;
 
-	/* switch to bank 0 */
-	m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
+	econ1 = enc_r8(enc, CTL_REG_ECON1);
+	if ((econ1 & ENC_ECON1_RXRST) == 0) {
+		enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXRST);
+		enc->rx_reset_counter = RX_RESET_COUNTER;
+	}
+}
 
-	m_nic_write (CTL_REG_ERDPTL, next_pointer_lsb);
-	m_nic_write (CTL_REG_ERDPTH, next_pointer_msb);
+/*
+ * Reset receiver and reenable it.
+ */
+static void enc_reset_rx_call(enc_dev_t *enc)
+{
+	enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_RXRST);
+	enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXEN);
+}
 
+/*
+ * Copy a packet from the receive ring and forward it to
+ * the protocol stack.
+ */
+static void enc_receive(enc_dev_t *enc)
+{
+	u8 *packet = (u8 *)NetRxPackets[0];
+	u16 pkt_len;
+	u16 copy_len;
+	u16 status;
+	u8 eir_reg;
+	u8 pkt_cnt = 0;
+	u16 rxbuf_rdpt;
+	u8 hbuf[6];
+
+	enc_w16(enc, CTL_REG_ERDPTL, enc->next_pointer);
 	do {
-		m_nic_read_data (6, buffer);
-		next_pointer_lsb = buffer[0];
-		next_pointer_msb = buffer[1];
-		pkt_len = buffer[2];
-		pkt_len |= (unsigned short) buffer[3] << 8;
-		status = buffer[4];
-		status |= (unsigned short) buffer[5] << 8;
-
+		enc_rbuf(enc, 6, hbuf);
+		enc->next_pointer = hbuf[0] | (hbuf[1] << 8);
+		pkt_len = hbuf[2] | (hbuf[3] << 8);
+		status = hbuf[4] | (hbuf[5] << 8);
+		debug("next_pointer=$%04x pkt_len=%u status=$%04x\n",
+			enc->next_pointer, pkt_len, status);
 		if (pkt_len <= ENC_MAX_FRM_LEN)
 			copy_len = pkt_len;
 		else
 			copy_len = 0;
-
 		if ((status & (1L << 7)) == 0) /* check Received Ok bit */
 			copy_len = 0;
-
-		/* taken from the Linux driver */
 		/* check if next pointer is resonable */
-		if ((((unsigned int)next_pointer_msb << 8) |
-			(unsigned int)next_pointer_lsb) >= ENC_TX_BUF_START)
+		if (enc->next_pointer >= ENC_TX_BUF_START)
 			copy_len = 0;
-
 		if (copy_len > 0) {
-			m_nic_read_data (copy_len, buffer);
+			enc_rbuf(enc, copy_len, packet);
 		}
-
 		/* advance read pointer to next pointer */
-		m_nic_write (CTL_REG_ERDPTL, next_pointer_lsb);
-		m_nic_write (CTL_REG_ERDPTH, next_pointer_msb);
-
+		enc_w16(enc, CTL_REG_ERDPTL, enc->next_pointer);
 		/* decrease packet counter */
-		m_nic_bfs (CTL_REG_ECON2, ENC_ECON2_PKTDEC);
-
-		/* taken from the Linux driver */
-		/* Only odd values should be written to ERXRDPTL,
+		enc_bset(enc, CTL_REG_ECON2, ENC_ECON2_PKTDEC);
+		/*
+		 * Only odd values should be written to ERXRDPTL,
 		 * see errata B4 pt.13
 		 */
-		rxbuf_rdpt = (next_pointer_msb << 8 | next_pointer_lsb) - 1;
-		if ((rxbuf_rdpt < (m_nic_read(CTL_REG_ERXSTH) << 8 |
-				m_nic_read(CTL_REG_ERXSTL))) || (rxbuf_rdpt >
-				(m_nic_read(CTL_REG_ERXNDH) << 8 |
-				m_nic_read(CTL_REG_ERXNDL)))) {
-			m_nic_write(CTL_REG_ERXRDPTL, m_nic_read(CTL_REG_ERXNDL));
-			m_nic_write(CTL_REG_ERXRDPTH, m_nic_read(CTL_REG_ERXNDH));
+		rxbuf_rdpt = enc->next_pointer - 1;
+		if ((rxbuf_rdpt < enc_r16(enc, CTL_REG_ERXSTL)) ||
+			(rxbuf_rdpt > enc_r16(enc, CTL_REG_ERXNDL))) {
+			enc_w16(enc, CTL_REG_ERXRDPTL,
+				enc_r16(enc, CTL_REG_ERXNDL));
 		} else {
-			m_nic_write(CTL_REG_ERXRDPTL, rxbuf_rdpt & 0xFF);
-			m_nic_write(CTL_REG_ERXRDPTH, rxbuf_rdpt >> 8);
+			enc_w16(enc, CTL_REG_ERXRDPTL, rxbuf_rdpt);
 		}
-
-		/* move to bank 1 */
-		m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1);
-		m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0);
-
 		/* read pktcnt */
-		pkt_cnt = m_nic_read (CTL_REG_EPKTCNT);
-
-		/* switch to bank 0 */
-		m_nic_bfc (CTL_REG_ECON1,
-			   (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
-
+		pkt_cnt = enc_r8(enc, CTL_REG_EPKTCNT);
 		if (copy_len == 0) {
-			eir_reg = m_nic_read (CTL_REG_EIR);
-			encReceiverReset ();
-			printf ("eth_rx: copy_len=0\n");
+			eir_reg = enc_r8(enc, CTL_REG_EIR);
+			enc_reset_rx(enc);
+			printf("%s: receive copy_len=0\n", enc->dev->name);
 			continue;
 		}
-
-		NetReceive ((unsigned char *) buffer, pkt_len);
-
-		eir_reg = m_nic_read (CTL_REG_EIR);
-	} while (pkt_cnt);	/* Use EPKTCNT not EIR.PKTIF flag, see errata pt. 6 */
-}
-
-static void encWriteReg (unsigned char regNo, unsigned char data)
-{
-	spi_lock ();
-	enc_cfg_spi ();
-	enc_enable ();
-
-	spi_write (0x40 | regNo);	/* write in regNo */
-	spi_write (data);
-
-	enc_disable ();
-	enc_enable ();
-
-	spi_write (0x1f);	/* write reg 0x1f */
-
-	enc_disable ();
-	spi_unlock ();
+		/*
+		 * Because NetReceive() might call enc_send(), we need to
+		 * release the SPI bus, call NetReceive(), reclaim the bus
+		 */
+		enc_release_bus(enc);
+		NetReceive(packet, pkt_len);
+		if (enc_claim_bus(enc))
+			return;
+		eir_reg = enc_r8(enc, CTL_REG_EIR);
+	} while (pkt_cnt);
+	/* Use EPKTCNT not EIR.PKTIF flag, see errata pt. 6 */
 }
 
-static void encWriteRegRetry (unsigned char regNo, unsigned char data, int c)
+/*
+ * Poll for completely received packets.
+ */
+static void enc_poll(enc_dev_t *enc)
 {
-	unsigned char readback;
-	int i;
-
-	spi_lock ();
+	u8 eir_reg;
+	u8 estat_reg;
+	u8 pkt_cnt;
 
-	for (i = 0; i < c; i++) {
-		enc_cfg_spi ();
-		enc_enable ();
-
-		spi_write (0x40 | regNo);	/* write in regNo */
-		spi_write (data);
-
-		enc_disable ();
-		enc_enable ();
-
-		spi_write (0x1f);	/* write reg 0x1f */
-
-		enc_disable ();
-
-		spi_unlock ();	/* we must unlock spi first */
-
-		readback = encReadReg (regNo);
-
-		spi_lock ();
-
-		if (readback == data)
-			break;
+#ifdef CONFIG_USE_IRQ
+	/* clear global interrupt enable bit in enc28j60 */
+	enc_bclr(enc, CTL_REG_EIE, ENC_EIE_INTIE);
+#endif
+	estat_reg = enc_r8(enc, CTL_REG_ESTAT);
+	eir_reg = enc_r8(enc, CTL_REG_EIR);
+	if (eir_reg & ENC_EIR_TXIF) {
+		/* clear TXIF bit in EIR */
+		enc_bclr(enc, CTL_REG_EIR, ENC_EIR_TXIF);
 	}
-	spi_unlock ();
-
-	if (i == c) {
-		printf ("enc28j60: write reg %d failed\n", regNo);
+	/* We have to use pktcnt and not pktif bit, see errata pt. 6 */
+	pkt_cnt = enc_r8(enc, CTL_REG_EPKTCNT);
+	if (pkt_cnt > 0) {
+		if ((eir_reg & ENC_EIR_PKTIF) == 0) {
+			debug("enc_poll: pkt cnt > 0, but pktif not set\n");
+		}
+		enc_receive(enc);
+		/*
+		 * clear PKTIF bit in EIR, this should not need to be done
+		 * but it seems like we get problems if we do not
+		 */
+		enc_bclr(enc, CTL_REG_EIR, ENC_EIR_PKTIF);
 	}
-}
-
-static unsigned char encReadReg (unsigned char regNo)
-{
-	unsigned char rxByte;
-
-	spi_lock ();
-	enc_cfg_spi ();
-	enc_enable ();
-
-	spi_write (0x1f);	/* read reg 0x1f */
-
-	bank = spi_read () & 0x3;
-
-	enc_disable ();
-	enc_enable ();
-
-	spi_write (regNo);
-	rxByte = spi_read ();
-
-	/* check if MAC or MII register */
-	if (((bank == 2) && (regNo <= 0x1a)) ||
-	    ((bank == 3) && (regNo <= 0x05 || regNo == 0x0a))) {
-		/* ignore first byte and read another byte */
-		rxByte = spi_read ();
+	if (eir_reg & ENC_EIR_RXERIF) {
+		printf("%s: rx error\n", enc->dev->name);
+		enc_bclr(enc, CTL_REG_EIR, ENC_EIR_RXERIF);
 	}
-
-	enc_disable ();
-	spi_unlock ();
-
-	return rxByte;
-}
-
-static void encReadBuff (unsigned short length, unsigned char *pBuff)
-{
-	spi_lock ();
-	enc_cfg_spi ();
-	enc_enable ();
-
-	spi_write (0x20 | 0x1a);	/* read buffer memory */
-
-	while (length--) {
-		if (pBuff != NULL)
-			*pBuff++ = spi_read ();
-		else
-			spi_write (0);
+	if (eir_reg & ENC_EIR_TXERIF) {
+		printf("%s: tx error\n", enc->dev->name);
+		enc_bclr(enc, CTL_REG_EIR, ENC_EIR_TXERIF);
 	}
-
-	enc_disable ();
-	spi_unlock ();
-}
-
-static void encWriteBuff (unsigned short length, unsigned char *pBuff)
-{
-	spi_lock ();
-	enc_cfg_spi ();
-	enc_enable ();
-
-	spi_write (0x60 | 0x1a);	/* write buffer memory */
-
-	spi_write (0x00);	/* control byte */
-
-	while (length--)
-		spi_write (*pBuff++);
-
-	enc_disable ();
-	spi_unlock ();
-}
-
-static void encBitSet (unsigned char regNo, unsigned char data)
-{
-	spi_lock ();
-	enc_cfg_spi ();
-	enc_enable ();
-
-	spi_write (0x80 | regNo);	/* bit field set */
-	spi_write (data);
-
-	enc_disable ();
-	spi_unlock ();
-}
-
-static void encBitClr (unsigned char regNo, unsigned char data)
-{
-	spi_lock ();
-	enc_cfg_spi ();
-	enc_enable ();
-
-	spi_write (0xA0 | regNo);	/* bit field clear */
-	spi_write (data);
-
-	enc_disable ();
-	spi_unlock ();
+#ifdef CONFIG_USE_IRQ
+	/* set global interrupt enable bit in enc28j60 */
+	enc_bset(enc, CTL_REG_EIE, ENC_EIE_INTIE);
+#endif
 }
 
-static void encReset (void)
+/*
+ * Completely Reset the ENC
+ */
+static void enc_reset(enc_dev_t *enc)
 {
-	spi_lock ();
-	enc_cfg_spi ();
-	enc_enable ();
-
-	spi_write (0xff);	/* soft reset */
-
-	enc_disable ();
-	spi_unlock ();
+	u8 dout[1];
 
+	dout[0] = CMD_SRC;
+	spi_xfer(enc->slave, 8, dout, NULL,
+		SPI_XFER_BEGIN | SPI_XFER_END);
 	/* sleep 1 ms. See errata pt. 2 */
-	udelay (1000);
+	udelay(1000);
 }
 
-static void encInit (unsigned char *pEthAddr)
-{
-	unsigned short phid1 = 0;
-	unsigned short phid2 = 0;
-
-	/* switch to bank 0 */
-	m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
-
+/*
+ * Initialisation data for most of the ENC registers
+ */
+static const u16 enc_initdata[] = {
 	/*
 	 * Setup the buffer space. The reset values are valid for the
 	 * other pointers.
+	 *
+	 * We shall not write to ERXST, see errata pt. 5. Instead we
+	 * have to make sure that ENC_RX_BUS_START is 0.
 	 */
-	/* We shall not write to ERXST, see errata pt. 5. Instead we
-	   have to make sure that ENC_RX_BUS_START is 0. */
-	m_nic_write_retry (CTL_REG_ERXSTL, (ENC_RX_BUF_START & 0xFF), 1);
-	m_nic_write_retry (CTL_REG_ERXSTH, (ENC_RX_BUF_START >> 8), 1);
-
-	/* taken from the Linux driver */
-	m_nic_write_retry (CTL_REG_ERXNDL, (ENC_RX_BUF_END & 0xFF), 1);
-	m_nic_write_retry (CTL_REG_ERXNDH, (ENC_RX_BUF_END >> 8), 1);
-
-	m_nic_write_retry (CTL_REG_ERDPTL, (ENC_RX_BUF_START & 0xFF), 1);
-	m_nic_write_retry (CTL_REG_ERDPTH, (ENC_RX_BUF_START >> 8), 1);
-
-	next_pointer_lsb = (ENC_RX_BUF_START & 0xFF);
-	next_pointer_msb = (ENC_RX_BUF_START >> 8);
-
-	/* verify identification */
-	phid1 = phyRead (PHY_REG_PHID1);
-	phid2 = phyRead (PHY_REG_PHID2);
-
-	if (phid1 != ENC_PHID1_VALUE
-	    || (phid2 & ENC_PHID2_MASK) != ENC_PHID2_VALUE) {
-		printf ("ERROR: failed to identify controller\n");
-		printf ("phid1 = %x, phid2 = %x\n",
-			phid1, (phid2 & ENC_PHID2_MASK));
-		printf ("should be phid1 = %x, phid2 = %x\n",
-			ENC_PHID1_VALUE, ENC_PHID2_VALUE);
-	}
-
+	CTL_REG_ERXSTL, ENC_RX_BUF_START,
+	CTL_REG_ERXSTH, ENC_RX_BUF_START >> 8,
+	CTL_REG_ERXNDL, ENC_RX_BUF_END,
+	CTL_REG_ERXNDH, ENC_RX_BUF_END >> 8,
+	CTL_REG_ERDPTL, ENC_RX_BUF_START,
+	CTL_REG_ERDPTH, ENC_RX_BUF_START >> 8,
 	/*
-	 * --- MAC Initialization ---
+	 * Set the filter to receive only good-CRC, unicast and broadcast
+	 * frames.
+	 * Note: some DHCP servers return their answers as broadcasts!
+	 * So its unwise to remove broadcast from this. This driver
+	 * might incur receiver overruns with packet loss on a broadcast
+	 * flooded network.
 	 */
-
-	/* Pull MAC out of Reset */
-
-	/* switch to bank 2 */
-	m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL0);
-	m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL1);
+	CTL_REG_ERXFCON, ENC_RFR_BCEN | ENC_RFR_UCEN | ENC_RFR_CRCEN,
 
 	/* enable MAC to receive frames */
-	/* added some bits from the Linux driver */
-	m_nic_write_retry (CTL_REG_MACON1
-		,(ENC_MACON1_MARXEN | ENC_MACON1_TXPAUS | ENC_MACON1_RXPAUS)
-		,10);
+	CTL_REG_MACON1,
+		ENC_MACON1_MARXEN | ENC_MACON1_TXPAUS | ENC_MACON1_RXPAUS,
 
 	/* configure pad, tx-crc and duplex */
-	/* added a bit from the Linux driver */
-	m_nic_write_retry (CTL_REG_MACON3
-		,(ENC_MACON3_PADCFG0 | ENC_MACON3_TXCRCEN | ENC_MACON3_FRMLNEN)
-		,10);
+	CTL_REG_MACON3,
+		ENC_MACON3_PADCFG0 | ENC_MACON3_TXCRCEN |
+		ENC_MACON3_FRMLNEN,
 
-	/* added 4 new lines from the Linux driver */
 	/* Allow infinite deferals if the medium is continously busy */
-	m_nic_write_retry(CTL_REG_MACON4, (1<<6) /*ENC_MACON4_DEFER*/, 10);
+	CTL_REG_MACON4, ENC_MACON4_DEFER,
 
 	/* Late collisions occur beyond 63 bytes */
-	m_nic_write_retry(CTL_REG_MACLCON2, 63, 10);
+	CTL_REG_MACLCON2, 63,
 
-	/* Set (low byte) Non-Back-to_Back Inter-Packet Gap. Recommended 0x12 */
-	m_nic_write_retry(CTL_REG_MAIPGL, 0x12, 10);
+	/*
+	 * Set (low byte) Non-Back-to_Back Inter-Packet Gap.
+	 * Recommended 0x12
+	 */
+	CTL_REG_MAIPGL, 0x12,
 
 	/*
-	* Set (high byte) Non-Back-to_Back Inter-Packet Gap. Recommended
-	* 0x0c for half-duplex. Nothing for full-duplex
-	*/
-	m_nic_write_retry(CTL_REG_MAIPGH, 0x0C, 10);
+	 * Set (high byte) Non-Back-to_Back Inter-Packet Gap.
+	 * Recommended 0x0c for half-duplex. Nothing for full-duplex
+	 */
+	CTL_REG_MAIPGH, 0x0C,
 
 	/* set maximum frame length */
-	m_nic_write_retry (CTL_REG_MAMXFLL, (ENC_MAX_FRM_LEN & 0xff), 10);
-	m_nic_write_retry (CTL_REG_MAMXFLH, (ENC_MAX_FRM_LEN >> 8), 10);
+	CTL_REG_MAMXFLL, ENC_MAX_FRM_LEN,
+	CTL_REG_MAMXFLH, ENC_MAX_FRM_LEN >> 8,
 
 	/*
-	 * Set MAC back-to-back inter-packet gap. Recommended 0x12 for half duplex
+	 * Set MAC back-to-back inter-packet gap.
+	 * Recommended 0x12 for half duplex
 	 * and 0x15 for full duplex.
 	 */
-	m_nic_write_retry (CTL_REG_MABBIPG, 0x12, 10);
+	CTL_REG_MABBIPG, 0x12,
 
-	/* set MAC address */
+	/* end of table */
+	0xffff
+};
 
-	/* switch to bank 3 */
-	m_nic_bfs (CTL_REG_ECON1, (ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1));
+/*
+ * Wait for the XTAL oscillator to become ready
+ */
+static int enc_clock_wait(enc_dev_t *enc)
+{
+	uint64_t etime;
 
-	m_nic_write_retry (CTL_REG_MAADR0, pEthAddr[5], 1);
-	m_nic_write_retry (CTL_REG_MAADR1, pEthAddr[4], 1);
-	m_nic_write_retry (CTL_REG_MAADR2, pEthAddr[3], 1);
-	m_nic_write_retry (CTL_REG_MAADR3, pEthAddr[2], 1);
-	m_nic_write_retry (CTL_REG_MAADR4, pEthAddr[1], 1);
-	m_nic_write_retry (CTL_REG_MAADR5, pEthAddr[0], 1);
+	/* one second timeout */
+	etime = get_ticks() + get_tbclk();
 
 	/*
-	* PHY Initialization taken from the Linux driver
+	 * Wait for CLKRDY to become set (i.e., check that we can
+	 * communicate with the ENC)
 	 */
+	do
+	{
+		if (enc_r8(enc, CTL_REG_ESTAT) & ENC_ESTAT_CLKRDY)
+			return 0;
+	} while (get_ticks() <= etime);
+
+	printf("%s: timeout waiting for CLKRDY\n", enc->dev->name);
+	return -1;
+}
+
+/*
+ * Write the MAC address into the ENC
+ */
+static int enc_write_macaddr(enc_dev_t *enc)
+{
+	unsigned char *p = enc->dev->enetaddr;
+
+	enc_w8_retry(enc, CTL_REG_MAADR5, *p++, 5);
+	enc_w8_retry(enc, CTL_REG_MAADR4, *p++, 5);
+	enc_w8_retry(enc, CTL_REG_MAADR3, *p++, 5);
+	enc_w8_retry(enc, CTL_REG_MAADR2, *p++, 5);
+	enc_w8_retry(enc, CTL_REG_MAADR1, *p++, 5);
+	enc_w8_retry(enc, CTL_REG_MAADR0, *p, 5);
+	return 0;
+}
+
+/*
+ * Setup most of the ENC registers
+ */
+static int enc_setup(enc_dev_t *enc)
+{
+	u16 phid1 = 0;
+	u16 phid2 = 0;
+	const u16 *tp;
+
+	/* reset enc struct values */
+	enc->next_pointer = ENC_RX_BUF_START;
+	enc->rx_reset_counter = RX_RESET_COUNTER;
+	enc->bank = 0xff;	/* invalidate current bank in enc28j60 */
+
+	/* verify PHY identification */
+	phid1 = phy_read(enc, PHY_REG_PHID1);
+	phid2 = phy_read(enc, PHY_REG_PHID2) & ENC_PHID2_MASK;
+	if (phid1 != ENC_PHID1_VALUE || phid2 != ENC_PHID2_VALUE) {
+		printf("%s: failed to identify PHY. Found %04x:%04x\n",
+			enc->dev->name, phid1, phid2);
+		return -1;
+	}
 
-	/* Prevent automatic loopback of data beeing transmitted by setting
-	   ENC_PHCON2_HDLDIS */
-	phyWrite(PHY_REG_PHCON2, (1<<8));
+	/* now program registers */
+	for (tp = enc_initdata; *tp != 0xffff; tp += 2)
+		enc_w8_retry(enc, tp[0], tp[1], 10);
+
+	/*
+	 * Prevent automatic loopback of data beeing transmitted by setting
+	 * ENC_PHCON2_HDLDIS
+	 */
+	phy_write(enc, PHY_REG_PHCON2, (1<<8));
 
-	/* LEDs configuration
+	/*
+	 * LEDs configuration
 	 * LEDA: LACFG = 0100 -> display link status
 	 * LEDB: LBCFG = 0111 -> display TX & RX activity
 	 * STRCH = 1 -> LED pulses
 	 */
-	phyWrite(PHY_REG_PHLCON, 0x0472);
+	phy_write(enc, PHY_REG_PHLCON, 0x0472);
 
 	/* Reset PDPXMD-bit => half duplex */
-	phyWrite(PHY_REG_PHCON1, 0);
-
-	/*
-	 * Receive settings
-	 */
+	phy_write(enc, PHY_REG_PHCON1, 0);
 
 #ifdef CONFIG_USE_IRQ
 	/* enable interrupts */
-	m_nic_bfs (CTL_REG_EIE, ENC_EIE_PKTIE);
-	m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXIE);
-	m_nic_bfs (CTL_REG_EIE, ENC_EIE_RXERIE);
-	m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXERIE);
-	m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE);
+	enc_bset(enc, CTL_REG_EIE, ENC_EIE_PKTIE);
+	enc_bset(enc, CTL_REG_EIE, ENC_EIE_TXIE);
+	enc_bset(enc, CTL_REG_EIE, ENC_EIE_RXERIE);
+	enc_bset(enc, CTL_REG_EIE, ENC_EIE_TXERIE);
+	enc_bset(enc, CTL_REG_EIE, ENC_EIE_INTIE);
 #endif
+
+	return 0;
 }
 
-/*****************************************************************************
- *
- * Description:
- *    Read PHY registers.
- *
- *    NOTE! This function will change to Bank 2.
- *
- * Params:
- *    [in] addr address of the register to read
- *
- * Returns:
- *    The value in the register
+/*
+ * Check if ENC has been initialized.
+ * If not, try to initialize it.
+ * Remember initialized state in struct.
  */
-static unsigned short phyRead (unsigned char addr)
+static int enc_initcheck(enc_dev_t *enc, const enum enc_initstate requiredstate)
 {
-	unsigned short ret = 0;
-
-	/* move to bank 2 */
-	m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL0);
-	m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL1);
+	if (enc->initstate >= requiredstate)
+		return 0;
+
+	if (enc->initstate < setupdone) {
+		/* Initialize the ENC only */
+		enc_reset(enc);
+		/* if any of functions fails, skip the rest and return an error */
+		if (enc_clock_wait(enc) || enc_setup(enc) || enc_write_macaddr(enc)) {
+			return -1;
+		}
+		enc->initstate = setupdone;
+	}
+	/* if that's all we need, return here */
+	if (enc->initstate >= requiredstate)
+		return 0;
 
-	/* write address to MIREGADR */
-	m_nic_write (CTL_REG_MIREGADR, addr);
+	/* now wait for link ready condition */
+	if (enc_phy_link_wait(enc)) {
+		return -1;
+	}
+	enc->initstate = linkready;
+	return 0;
+}
 
-	/* set MICMD.MIIRD */
-	m_nic_write (CTL_REG_MICMD, ENC_MICMD_MIIRD);
+#if defined(CONFIG_CMD_MII)
+/*
+ * Read a PHY register.
+ *
+ * This function is registered with miiphy_register().
+ */
+int enc_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value)
+{
+	struct eth_device *dev = eth_get_dev_by_name(devname);
+	enc_dev_t *enc;
+
+	if (!dev || phy_adr != 0)
+		return -1;
+
+	enc = dev->priv;
+	if (enc_claim_bus(enc))
+		return -1;
+	if (enc_initcheck(enc, setupdone)) {
+		enc_release_bus(enc);
+		return -1;
+	}
+	*value = phy_read(enc, reg);
+	enc_release_bus(enc);
+	return 0;
+}
 
-	/* taken from the Linux driver */
-	/* move to bank 3 */
-	m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL0);
-	m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1);
+/*
+ * Write a PHY register.
+ *
+ * This function is registered with miiphy_register().
+ */
+int enc_miiphy_write(const char *devname, u8 phy_adr, u8 reg, u16 value)
+{
+	struct eth_device *dev = eth_get_dev_by_name(devname);
+	enc_dev_t *enc;
+
+	if (!dev || phy_adr != 0)
+		return -1;
+
+	enc = dev->priv;
+	if (enc_claim_bus(enc))
+		return -1;
+	if (enc_initcheck(enc, setupdone)) {
+		enc_release_bus(enc);
+		return -1;
+	}
+	phy_write(enc, reg, value);
+	enc_release_bus(enc);
+	return 0;
+}
+#endif
 
-	/* poll MISTAT.BUSY bit until operation is complete */
-	while ((m_nic_read (CTL_REG_MISTAT) & ENC_MISTAT_BUSY) != 0) {
-		static int cnt = 0;
+/*
+ * Write hardware (MAC) address.
+ *
+ * This function entered into eth_device structure.
+ */
+static int enc_write_hwaddr(struct eth_device *dev)
+{
+	enc_dev_t *enc = dev->priv;
 
-		if (cnt++ >= 1000) {
-			/* GJ - this seems extremely dangerous! */
-			/* printf("#"); */
-			cnt = 0;
-		}
+	if (enc_claim_bus(enc))
+		return -1;
+	if (enc_initcheck(enc, setupdone)) {
+		enc_release_bus(enc);
+		return -1;
 	}
+	enc_release_bus(enc);
+	return 0;
+}
 
-	/* taken from the Linux driver */
-	/* move to bank 2 */
-	m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_BSEL0);
-	m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1);
+/*
+ * Initialize ENC28J60 for use.
+ *
+ * This function entered into eth_device structure.
+ */
+static int enc_init(struct eth_device *dev, bd_t *bis)
+{
+	enc_dev_t *enc = dev->priv;
 
-	/* clear MICMD.MIIRD */
-	m_nic_write (CTL_REG_MICMD, 0);
+	if (enc_claim_bus(enc))
+		return -1;
+	if (enc_initcheck(enc, linkready)) {
+		enc_release_bus(enc);
+		return -1;
+	}
+	/* enable receive */
+	enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXEN);
+	enc_release_bus(enc);
+	return 0;
+}
 
-	ret = (m_nic_read (CTL_REG_MIRDH) << 8);
-	ret |= (m_nic_read (CTL_REG_MIRDL) & 0xFF);
+/*
+ * Check for received packets.
+ *
+ * This function entered into eth_device structure.
+ */
+static int enc_recv(struct eth_device *dev)
+{
+	enc_dev_t *enc = dev->priv;
 
-	return ret;
+	if (enc_claim_bus(enc))
+		return -1;
+	if (enc_initcheck(enc, linkready)) {
+		enc_release_bus(enc);
+		return -1;
+	}
+	/* Check for dead receiver */
+	if (enc->rx_reset_counter > 0)
+		enc->rx_reset_counter--;
+	else
+		enc_reset_rx_call(enc);
+	enc_poll(enc);
+	enc_release_bus(enc);
+	return 0;
 }
 
-/*****************************************************************************
- *
- * Taken from the Linux driver.
- * Description:
- * Write PHY registers.
- *
- * NOTE! This function will change to Bank 3.
+/*
+ * Send a packet.
  *
- * Params:
- * [in] addr address of the register to write to
- * [in] data to be written
+ * This function entered into eth_device structure.
  *
- * Returns:
- *    None
+ * Should we wait here until we have a Link? Or shall we leave that to
+ * protocol retries?
  */
-static void phyWrite(unsigned char addr, unsigned short data)
+static int enc_send(
+	struct eth_device *dev,
+	volatile void *packet,
+	int length)
 {
-	/* move to bank 2 */
-	m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_BSEL0);
-	m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1);
+	enc_dev_t *enc = dev->priv;
+
+	if (enc_claim_bus(enc))
+		return -1;
+	if (enc_initcheck(enc, linkready)) {
+		enc_release_bus(enc);
+		return -1;
+	}
+	/* setup transmit pointers */
+	enc_w16(enc, CTL_REG_EWRPTL, ENC_TX_BUF_START);
+	enc_w16(enc, CTL_REG_ETXNDL, length + ENC_TX_BUF_START);
+	enc_w16(enc, CTL_REG_ETXSTL, ENC_TX_BUF_START);
+	/* write packet to ENC */
+	enc_wbuf(enc, length, (u8 *) packet, 0x00);
+	/*
+	 * Check that the internal transmit logic has not been altered
+	 * by excessive collisions. Reset transmitter if so.
+	 * See Errata B4 12 and 14.
+	 */
+	if (enc_r8(enc, CTL_REG_EIR) & ENC_EIR_TXERIF) {
+		enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_TXRST);
+		enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_TXRST);
+	}
+	enc_bclr(enc, CTL_REG_EIR, (ENC_EIR_TXERIF | ENC_EIR_TXIF));
+	/* start transmitting */
+	enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_TXRTS);
+	enc_release_bus(enc);
+	return 0;
+}
 
-	/* write address to MIREGADR */
-	m_nic_write(CTL_REG_MIREGADR, addr);
+/*
+ * Finish use of ENC.
+ *
+ * This function entered into eth_device structure.
+ */
+static void enc_halt(struct eth_device *dev)
+{
+	enc_dev_t *enc = dev->priv;
 
-	m_nic_write(CTL_REG_MIWRL, data & 0xff);
-	m_nic_write(CTL_REG_MIWRH, data >> 8);
+	if (enc_claim_bus(enc))
+		return;
+	/* Just disable receiver */
+	enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_RXEN);
+	enc_release_bus(enc);
+}
 
-	/* move to bank 3 */
-	m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL0);
-	m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1);
+/*
+ * This is the only exported function.
+ *
+ * It may be called several times with different bus:cs combinations.
+ */
+int enc28j60_initialize(unsigned int bus, unsigned int cs,
+	unsigned int max_hz, unsigned int mode)
+{
+	struct eth_device *dev;
+	enc_dev_t *enc;
 
-	/* poll MISTAT.BUSY bit until operation is complete */
-	while((m_nic_read(CTL_REG_MISTAT) & ENC_MISTAT_BUSY) != 0) {
-		static int cnt = 0;
+	/* try to allocate, check and clear eth_device object */
+	dev = malloc(sizeof(*dev));
+	if (!dev) {
+		return -1;
+	}
+	memset(dev, 0, sizeof(*dev));
 
-		if(cnt++ >= 1000) {
-			cnt = 0;
-		}
+	/* try to allocate, check and clear enc_dev_t object */
+	enc = malloc(sizeof(*enc));
+	if (!enc) {
+		free(dev);
+		return -1;
+	}
+	memset(enc, 0, sizeof(*enc));
+
+	/* try to setup the SPI slave */
+	enc->slave = spi_setup_slave(bus, cs, max_hz, mode);
+	if (!enc->slave) {
+		printf("enc28j60: invalid SPI device %i:%i\n", bus, cs);
+		free(enc);
+		free(dev);
+		return -1;
 	}
+
+	enc->dev = dev;
+	/* now fill the eth_device object */
+	dev->priv = enc;
+	dev->init = enc_init;
+	dev->halt = enc_halt;
+	dev->send = enc_send;
+	dev->recv = enc_recv;
+	dev->write_hwaddr = enc_write_hwaddr;
+	sprintf(dev->name, "enc%i.%i", bus, cs);
+	eth_register(dev);
+#if defined(CONFIG_CMD_MII)
+	miiphy_register(dev->name, enc_miiphy_read, enc_miiphy_write);
+#endif
+	return 0;
 }