diff options
| author | Bin Meng <bmeng.cn@gmail.com> | 2016-02-01 01:40:43 -0800 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2016-02-05 12:47:21 +0800 |
| commit | 384980c687ca38c028bdf40f59a38b3f52105884 (patch) | |
| tree | e9f70955a43852369d64b01eafb91c09e6b4e848 /drivers/pch | |
| parent | 3e389d8ba666c5c2ad42021c2087630c1e412954 (diff) | |
dm: pch: Add get_gpio_base op
x86 GPIO registers are accessed via I/O port whose base address is
configured in a PCI configuration register on the PCH device. Add
an op get_gpio_base to get the GPIO base address from PCH.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/pch')
| -rw-r--r-- | drivers/pch/pch-uclass.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/pch/pch-uclass.c b/drivers/pch/pch-uclass.c index b33d50201b8..48a3965a764 100644 --- a/drivers/pch/pch-uclass.c +++ b/drivers/pch/pch-uclass.c @@ -33,6 +33,17 @@ int pch_set_spi_protect(struct udevice *dev, bool protect) return ops->set_spi_protect(dev, protect); } +int pch_get_gpio_base(struct udevice *dev, u32 *gbasep) +{ + struct pch_ops *ops = pch_get_ops(dev); + + *gbasep = 0; + if (!ops->get_gpio_base) + return -ENOSYS; + + return ops->get_gpio_base(dev, gbasep); +} + static int pch_uclass_post_bind(struct udevice *bus) { /* |