diff options
| author | Tim Harvey <tharvey@gateworks.com> | 2014-08-07 22:57:29 -0700 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2014-08-20 12:37:15 +0200 |
| commit | 5a82e1a21d1229e7e3d1c64187735794019e9a1b (patch) | |
| tree | 375fe3d824eb4c617917df43ec035ba93b4d3d8d /drivers/pci | |
| parent | 0351ef97d7f8aef0ae03f80c43f2d6d7b97174e7 (diff) | |
pci: mx6: fix occasional link failures
According to the IMX6 reference manuals, REF_SSP_EN (Reference clock enable
for SS function) must remain deasserted until the reference clock is running
at the appropriate frequency.
Without this patch we find a high link failure rate (>5%) on certain
IMX6 boards at various temperatures.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/pcie_imx.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index c48737e6c9e..a3982c4553e 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -509,10 +509,6 @@ static int imx6_pcie_deassert_core_reset(void) imx6_pcie_toggle_power(); - /* Enable PCIe */ - clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); - setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN); - enable_pcie_clock(); /* @@ -521,6 +517,10 @@ static int imx6_pcie_deassert_core_reset(void) */ mdelay(50); + /* Enable PCIe */ + clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); + setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN); + imx6_pcie_toggle_reset(); return 0; |