diff options
| author | Tom Rini <trini@konsulko.com> | 2023-02-23 17:32:22 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-02-23 17:40:18 -0500 |
| commit | 0024e7f72b689f8c2df731a69e20f47b6f8dc5a7 (patch) | |
| tree | 03da9b68c29df4ffa5c181acca8ce6176636a410 /drivers/pwm/tegra_pwm.c | |
| parent | 0b58258a33280a536c5b1e5e90dfdf0b5b5852cc (diff) | |
| parent | 5a8fe1ee818e0f8a74fa088f6a3d705a01b6afbe (diff) | |
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-tegra
Diffstat (limited to 'drivers/pwm/tegra_pwm.c')
| -rw-r--r-- | drivers/pwm/tegra_pwm.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/pwm/tegra_pwm.c b/drivers/pwm/tegra_pwm.c index 36c35c608b2..95fc26458b8 100644 --- a/drivers/pwm/tegra_pwm.c +++ b/drivers/pwm/tegra_pwm.c @@ -20,19 +20,21 @@ static int tegra_pwm_set_config(struct udevice *dev, uint channel, { struct tegra_pwm_priv *priv = dev_get_priv(dev); struct pwm_ctlr *regs = priv->regs; + const u32 pwm_max_freq = dev_get_driver_data(dev); uint pulse_width; u32 reg; if (channel >= 4) return -EINVAL; debug("%s: Configure '%s' channel %u\n", __func__, dev->name, channel); - /* We ignore the period here and just use 32KHz */ - clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ, 32768); + + clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_PERIPH, pwm_max_freq); pulse_width = duty_ns * 255 / period_ns; reg = pulse_width << PWM_WIDTH_SHIFT; reg |= 1 << PWM_DIVIDER_SHIFT; + reg |= PWM_ENABLE_MASK; writel(reg, ®s[channel].control); debug("%s: pulse_width=%u\n", __func__, pulse_width); @@ -68,8 +70,8 @@ static const struct pwm_ops tegra_pwm_ops = { }; static const struct udevice_id tegra_pwm_ids[] = { - { .compatible = "nvidia,tegra124-pwm" }, - { .compatible = "nvidia,tegra20-pwm" }, + { .compatible = "nvidia,tegra20-pwm", .data = 48 * 1000000 }, + { .compatible = "nvidia,tegra114-pwm", .data = 408 * 1000000 }, { } }; |