Merge branch 'master' of git://git.denx.de/u-boot-rockchip

23 files changed, 1026 insertions, 124 deletions

diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index e404c0cdb90..c50aff2e93d 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -6,6 +6,7 @@
 
 obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
 obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o
+obj-$(CONFIG_ROCKCHIP_RK322X) += clk_rk322x.o
 obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
 obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
 obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o
diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c
new file mode 100644
index 00000000000..fdeb816e231
--- /dev/null
+++ b/drivers/clk/rockchip/clk_rk322x.c
@@ -0,0 +1,413 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk322x.h>
+#include <asm/arch/hardware.h>
+#include <dm/lists.h>
+#include <dt-bindings/clock/rk3228-cru.h>
+#include <linux/log2.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+	VCO_MAX_HZ	= 3200U * 1000000,
+	VCO_MIN_HZ	= 800 * 1000000,
+	OUTPUT_MAX_HZ	= 3200U * 1000000,
+	OUTPUT_MIN_HZ	= 24 * 1000000,
+};
+
+#define RATE_TO_DIV(input_rate, output_rate) \
+	((input_rate) / (output_rate) - 1);
+
+#define DIV_TO_RATE(input_rate, div)	((input_rate) / ((div) + 1))
+
+#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
+	.refdiv = _refdiv,\
+	.fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ), \
+	.postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
+	_Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) * \
+			 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz, \
+			 #hz "Hz cannot be hit with PLL "\
+			 "divisors on line " __stringify(__LINE__));
+
+/* use integer mode*/
+static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
+static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
+
+static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id,
+			 const struct pll_div *div)
+{
+	int pll_id = rk_pll_id(clk_id);
+	struct rk322x_pll *pll = &cru->pll[pll_id];
+
+	/* All PLLs have same VCO and output frequency range restrictions. */
+	uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
+	uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
+
+	debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n",
+	      pll, div->fbdiv, div->refdiv, div->postdiv1,
+	      div->postdiv2, vco_hz, output_hz);
+	assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
+	       output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
+
+	/* use integer mode */
+	rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
+	/* Power down */
+	rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT);
+
+	rk_clrsetreg(&pll->con0,
+		     PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
+		     (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv);
+	rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
+		     (div->postdiv2 << PLL_POSTDIV2_SHIFT |
+		     div->refdiv << PLL_REFDIV_SHIFT));
+
+	/* Power Up */
+	rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT);
+
+	/* waiting for pll lock */
+	while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
+		udelay(1);
+
+	return 0;
+}
+
+static void rkclk_init(struct rk322x_cru *cru)
+{
+	u32 aclk_div;
+	u32 hclk_div;
+	u32 pclk_div;
+
+	/* pll enter slow-mode */
+	rk_clrsetreg(&cru->cru_mode_con,
+		     GPLL_MODE_MASK | APLL_MODE_MASK,
+		     GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
+		     APLL_MODE_SLOW << APLL_MODE_SHIFT);
+
+	/* init pll */
+	rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
+	rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
+
+	/*
+	 * select apll as cpu/core clock pll source and
+	 * set up dependent divisors for PERI and ACLK clocks.
+	 * core hz : apll = 1:1
+	 */
+	aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
+	assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7);
+
+	pclk_div = APLL_HZ / CORE_PERI_HZ - 1;
+	assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);
+
+	rk_clrsetreg(&cru->cru_clksel_con[0],
+		     CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK,
+		     CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
+		     0 << CORE_DIV_CON_SHIFT);
+
+	rk_clrsetreg(&cru->cru_clksel_con[1],
+		     CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK,
+		     aclk_div << CORE_ACLK_DIV_SHIFT |
+		     pclk_div << CORE_PERI_DIV_SHIFT);
+
+	/*
+	 * select apll as pd_bus bus clock source and
+	 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
+	 */
+	aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
+	assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
+
+	pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1;
+	assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7);
+
+	hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1;
+	assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3);
+
+	rk_clrsetreg(&cru->cru_clksel_con[0],
+		     BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
+		     BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT |
+		     aclk_div << BUS_ACLK_DIV_SHIFT);
+
+	rk_clrsetreg(&cru->cru_clksel_con[1],
+		     BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK,
+		     pclk_div << BUS_PCLK_DIV_SHIFT |
+		     hclk_div << BUS_HCLK_DIV_SHIFT);
+
+	/*
+	 * select gpll as pd_peri bus clock source and
+	 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
+	 */
+	aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
+	assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
+
+	hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
+	assert((1 << hclk_div) * PERI_HCLK_HZ ==
+		PERI_ACLK_HZ && (hclk_div < 0x4));
+
+	pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
+	assert((1 << pclk_div) * PERI_PCLK_HZ ==
+		PERI_ACLK_HZ && pclk_div < 0x8);
+
+	rk_clrsetreg(&cru->cru_clksel_con[10],
+		     PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK |
+		     PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK,
+		     PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT |
+		     pclk_div << PERI_PCLK_DIV_SHIFT |
+		     hclk_div << PERI_HCLK_DIV_SHIFT |
+		     aclk_div << PERI_ACLK_DIV_SHIFT);
+
+	/* PLL enter normal-mode */
+	rk_clrsetreg(&cru->cru_mode_con,
+		     GPLL_MODE_MASK | APLL_MODE_MASK,
+		     GPLL_MODE_NORM << GPLL_MODE_SHIFT |
+		     APLL_MODE_NORM << APLL_MODE_SHIFT);
+}
+
+/* Get pll rate by id */
+static uint32_t rkclk_pll_get_rate(struct rk322x_cru *cru,
+				   enum rk_clk_id clk_id)
+{
+	uint32_t refdiv, fbdiv, postdiv1, postdiv2;
+	uint32_t con;
+	int pll_id = rk_pll_id(clk_id);
+	struct rk322x_pll *pll = &cru->pll[pll_id];
+	static u8 clk_shift[CLK_COUNT] = {
+		0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff,
+		GPLL_MODE_SHIFT, 0xff
+	};
+	static u32 clk_mask[CLK_COUNT] = {
+		0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff,
+		GPLL_MODE_MASK, 0xff
+	};
+	uint shift;
+	uint mask;
+
+	con = readl(&cru->cru_mode_con);
+	shift = clk_shift[clk_id];
+	mask = clk_mask[clk_id];
+
+	switch ((con & mask) >> shift) {
+	case GPLL_MODE_SLOW:
+		return OSC_HZ;
+	case GPLL_MODE_NORM:
+
+		/* normal mode */
+		con = readl(&pll->con0);
+		postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
+		fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
+		con = readl(&pll->con1);
+		postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
+		refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
+		return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
+	default:
+		return 32768;
+	}
+}
+
+static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate,
+				  int periph)
+{
+	uint src_rate;
+	uint div, mux;
+	u32 con;
+
+	switch (periph) {
+	case HCLK_EMMC:
+	case SCLK_EMMC:
+		con = readl(&cru->cru_clksel_con[11]);
+		mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
+		con = readl(&cru->cru_clksel_con[12]);
+		div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
+		break;
+	case HCLK_SDMMC:
+	case SCLK_SDMMC:
+		con = readl(&cru->cru_clksel_con[11]);
+		mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
+		div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
+	return DIV_TO_RATE(src_rate, div);
+}
+
+static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,
+				  int periph, uint freq)
+{
+	int src_clk_div;
+	int mux;
+
+	debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
+
+	/* mmc clock auto divide 2 in internal */
+	src_clk_div = (clk_general_rate / 2 + freq - 1) / freq;
+
+	if (src_clk_div > 0x7f) {
+		src_clk_div = (OSC_HZ / 2 + freq - 1) / freq;
+		mux = EMMC_SEL_24M;
+	} else {
+		mux = EMMC_SEL_GPLL;
+	}
+
+	switch (periph) {
+	case HCLK_EMMC:
+	case SCLK_EMMC:
+		rk_clrsetreg(&cru->cru_clksel_con[11],
+			     EMMC_PLL_MASK,
+			     mux << EMMC_PLL_SHIFT);
+		rk_clrsetreg(&cru->cru_clksel_con[12],
+			     EMMC_DIV_MASK,
+			     (src_clk_div - 1) << EMMC_DIV_SHIFT);
+		break;
+	case HCLK_SDMMC:
+	case SCLK_SDMMC:
+		rk_clrsetreg(&cru->cru_clksel_con[11],
+			     MMC0_PLL_MASK | MMC0_DIV_MASK,
+			     mux << MMC0_PLL_SHIFT |
+			     (src_clk_div - 1) << MMC0_DIV_SHIFT);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
+}
+
+static int rk322x_ddr_set_clk(struct rk322x_cru *cru, unsigned int set_rate)
+{
+	struct pll_div dpll_cfg;
+
+	/*  clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
+	switch (set_rate) {
+	case 400*MHz:
+		dpll_cfg = (struct pll_div)
+		{.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
+		break;
+	case 600*MHz:
+		dpll_cfg = (struct pll_div)
+		{.refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1};
+		break;
+	case 800*MHz:
+		dpll_cfg = (struct pll_div)
+		{.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
+		break;
+	}
+
+	/* pll enter slow-mode */
+	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
+		     DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
+	rkclk_set_pll(cru, CLK_DDR, &dpll_cfg);
+	/* PLL enter normal-mode */
+	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
+		     DPLL_MODE_NORM << DPLL_MODE_SHIFT);
+
+	return set_rate;
+}
+static ulong rk322x_clk_get_rate(struct clk *clk)
+{
+	struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
+	ulong rate, gclk_rate;
+
+	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
+	switch (clk->id) {
+	case 0 ... 63:
+		rate = rkclk_pll_get_rate(priv->cru, clk->id);
+		break;
+	case HCLK_EMMC:
+	case SCLK_EMMC:
+	case HCLK_SDMMC:
+	case SCLK_SDMMC:
+		rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return rate;
+}
+
+static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate)
+{
+	struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
+	ulong new_rate, gclk_rate;
+
+	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
+	switch (clk->id) {
+	case HCLK_EMMC:
+	case SCLK_EMMC:
+	case HCLK_SDMMC:
+	case SCLK_SDMMC:
+		new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
+						clk->id, rate);
+		break;
+	case CLK_DDR:
+		new_rate = rk322x_ddr_set_clk(priv->cru, rate);
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return new_rate;
+}
+
+static struct clk_ops rk322x_clk_ops = {
+	.get_rate	= rk322x_clk_get_rate,
+	.set_rate	= rk322x_clk_set_rate,
+};
+
+static int rk322x_clk_ofdata_to_platdata(struct udevice *dev)
+{
+	struct rk322x_clk_priv *priv = dev_get_priv(dev);
+
+	priv->cru = (struct rk322x_cru *)devfdt_get_addr(dev);
+
+	return 0;
+}
+
+static int rk322x_clk_probe(struct udevice *dev)
+{
+	struct rk322x_clk_priv *priv = dev_get_priv(dev);
+
+	rkclk_init(priv->cru);
+
+	return 0;
+}
+
+static int rk322x_clk_bind(struct udevice *dev)
+{
+	int ret;
+
+	/* The reset driver does not have a device node, so bind it here */
+	ret = device_bind_driver(gd->dm_root, "rk322x_sysreset", "reset", &dev);
+	if (ret)
+		debug("Warning: No RK3036 reset driver: ret=%d\n", ret);
+
+	return 0;
+}
+
+static const struct udevice_id rk322x_clk_ids[] = {
+	{ .compatible = "rockchip,rk3228-cru" },
+	{ }
+};
+
+U_BOOT_DRIVER(rockchip_rk322x_cru) = {
+	.name		= "clk_rk322x",
+	.id		= UCLASS_CLK,
+	.of_match	= rk322x_clk_ids,
+	.priv_auto_alloc_size = sizeof(struct rk322x_clk_priv),
+	.ofdata_to_platdata = rk322x_clk_ofdata_to_platdata,
+	.ops		= &rk322x_clk_ops,
+	.bind		= rk322x_clk_bind,
+	.probe		= rk322x_clk_probe,
+};
diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index 25a21e29d00..e7fcf89f734 100644
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -44,7 +44,7 @@ static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq)
 
 	ret = clk_set_rate(&priv->clk, freq);
 	if (ret < 0) {
-		printf("%s: err=%d\n", __func__, ret);
+		debug("%s: err=%d\n", __func__, ret);
 		return ret;
 	}
 
@@ -59,32 +59,28 @@ static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev)
 
 	host->name = dev->name;
 	host->ioaddr = (void *)devfdt_get_addr(dev);
-	host->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
-					"bus-width", 4);
+	host->buswidth = dev_read_u32_default(dev, "bus-width", 4);
 	host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
 	host->priv = dev;
 
 	/* use non-removeable as sdcard and emmc as judgement */
-	if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), "non-removable"))
+	if (dev_read_bool(dev, "non-removable"))
 		host->dev_index = 0;
 	else
 		host->dev_index = 1;
 
-	priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
-				    "fifo-depth", 0);
+	priv->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0);
+
 	if (priv->fifo_depth < 0)
 		return -EINVAL;
-	priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
-					  "fifo-mode");
+	priv->fifo_mode = dev_read_bool(dev, "fifo-mode");
 
 	/*
 	 * 'clock-freq-min-max' is deprecated
 	 * (see https://github.com/torvalds/linux/commit/b023030f10573de738bbe8df63d43acab64c9f7b)
 	 */
-	if (fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
-				 "clock-freq-min-max", priv->minmax, 2)) {
-		int val = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
-					  "max-frequency", -EINVAL);
+	if (dev_read_u32_array(dev, "clock-freq-min-max", priv->minmax, 2)) {
+		int val = dev_read_u32_default(dev, "max-frequency", -EINVAL);
 
 		if (val < 0)
 			return val;
@@ -119,13 +115,14 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
 	host->dev_index = 0;
 	priv->fifo_depth = dtplat->fifo_depth;
 	priv->fifo_mode = 0;
-	memcpy(priv->minmax, dtplat->clock_freq_min_max, sizeof(priv->minmax));
+	priv->minmax[0] = 400000;  /*  400 kHz */
+	priv->minmax[1] = dtplat->max_frequency;
 
 	ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
 	if (ret < 0)
 		return ret;
 #else
-	ret = clk_get_by_name(dev, "ciu", &priv->clk);
+	ret = clk_get_by_index(dev, 0, &priv->clk);
 	if (ret < 0)
 		return ret;
 #endif
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index 8985878d7e8..f31d329c81d 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -50,8 +50,7 @@ static int arasan_sdhci_probe(struct udevice *dev)
 	max_frequency = dtplat->max_frequency;
 	ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &clk);
 #else
-	max_frequency = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
-			"max-frequency", 0);
+	max_frequency = dev_read_u32_default(dev, "max-frequency", 0);
 	ret = clk_get_by_index(dev, 0, &clk);
 #endif
 	if (!ret) {
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index e8569e6fef5..521e4dde41f 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -760,15 +760,14 @@ int designware_eth_ofdata_to_platdata(struct udevice *dev)
 		pdata->max_speed = fdt32_to_cpu(*cell);
 
 #ifdef CONFIG_DM_GPIO
-	if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
-			    "snps,reset-active-low"))
+	if (dev_read_bool(dev, "snps,reset-active-low"))
 		reset_flags |= GPIOD_ACTIVE_LOW;
 
 	ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
 		&priv->reset_gpio, reset_flags);
 	if (ret == 0) {
-		ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
-			"snps,reset-delays-us", dw_pdata->reset_delays, 3);
+		ret = dev_read_u32_array(dev, "snps,reset-delays-us",
+					 dw_pdata->reset_delays, 3);
 	} else if (ret == -ENOENT) {
 		ret = 0;
 	}
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index 5e2ca763027..c9f9e839bad 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -43,18 +43,16 @@ struct rk_gmac_ops {
 static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
 {
 	struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
-	const void *blob = gd->fdt_blob;
-	int node = dev_of_offset(dev);
 
 	/* Check the new naming-style first... */
-	pdata->tx_delay = fdtdec_get_int(blob, node, "tx_delay", -ENOENT);
-	pdata->rx_delay = fdtdec_get_int(blob, node, "rx_delay", -ENOENT);
+	pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT);
+	pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT);
 
 	/* ... and fall back to the old naming style or default, if necessary */
 	if (pdata->tx_delay == -ENOENT)
-		pdata->tx_delay = fdtdec_get_int(blob, node, "tx-delay", 0x30);
+		pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30);
 	if (pdata->rx_delay == -ENOENT)
-		pdata->rx_delay = fdtdec_get_int(blob, node, "rx-delay", 0x10);
+		pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10);
 
 	return designware_eth_ofdata_to_platdata(dev);
 }
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index f948783170f..4ab0b3a5eba 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -178,6 +178,16 @@ config PINCTRL_ROCKCHIP_RK3188
 	  the GPIO definitions and pin control functions for each available
 	  multiplex function.
 
+config PINCTRL_ROCKCHIP_RK322X
+	bool "Rockchip rk322x pin control driver"
+	depends on DM
+	help
+	  Support pin multiplexing control on Rockchip rk322x SoCs.
+
+	  The driver is controlled by a device tree node which contains both
+	  the GPIO definitions and pin control functions for each available
+	  multiplex function.
+
 config PINCTRL_ROCKCHIP_RK3288
 	bool "Rockchip rk3288 pin control driver"
 	depends on DM
diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile
index a1c655d537d..5251771a106 100644
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -7,6 +7,7 @@
 
 obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3036) += pinctrl_rk3036.o
 obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3188) += pinctrl_rk3188.o
+obj-$(CONFIG_PINCTRL_ROCKCHIP_RK322X) += pinctrl_rk322x.o
 obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3288) += pinctrl_rk3288.o
 obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3328) += pinctrl_rk3328.o
 obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3368) += pinctrl_rk3368.o
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3036.c b/drivers/pinctrl/rockchip/pinctrl_rk3036.c
index 9215d6c96e2..94f6d7ad403 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3036.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3036.c
@@ -193,8 +193,7 @@ static int rk3036_pinctrl_get_periph_id(struct udevice *dev,
 	u32 cell[3];
 	int ret;
 
-	ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
-				   "interrupts", cell, ARRAY_SIZE(cell));
+	ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
 	if (ret < 0)
 		return -EINVAL;
 
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3188.c b/drivers/pinctrl/rockchip/pinctrl_rk3188.c
index 65c1f665ea9..692d8e298d0 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3188.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3188.c
@@ -370,8 +370,7 @@ static int rk3188_pinctrl_get_periph_id(struct udevice *dev,
 	u32 cell[3];
 	int ret;
 
-	ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
-				   "interrupts", cell, ARRAY_SIZE(cell));
+	ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
 	if (ret < 0)
 		return -EINVAL;
 
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk322x.c b/drivers/pinctrl/rockchip/pinctrl_rk322x.c
new file mode 100644
index 00000000000..7aaf4b5801a
--- /dev/null
+++ b/drivers/pinctrl/rockchip/pinctrl_rk322x.c
@@ -0,0 +1,294 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/grf_rk322x.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/periph.h>
+#include <dm/pinctrl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct rk322x_pinctrl_priv {
+	struct rk322x_grf *grf;
+};
+
+static void pinctrl_rk322x_pwm_config(struct rk322x_grf *grf, int pwm_id)
+{
+	u32 mux_con = readl(&grf->con_iomux);
+
+	switch (pwm_id) {
+	case PERIPH_ID_PWM0:
+		if (mux_con & CON_IOMUX_PWM0SEL_MASK)
+			rk_clrsetreg(&grf->gpio3c_iomux, GPIO3C5_MASK,
+				     GPIO3C5_PWM10 << GPIO3C5_SHIFT);
+		else
+			rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK,
+				     GPIO0D2_PWM0 << GPIO0D2_SHIFT);
+		break;
+	case PERIPH_ID_PWM1:
+		if (mux_con & CON_IOMUX_PWM1SEL_MASK)
+			rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D6_MASK,
+				     GPIO0D6_PWM11 << GPIO0D6_SHIFT);
+		else
+			rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D3_MASK,
+				     GPIO0D3_PWM1 << GPIO0D3_SHIFT);
+		break;
+	case PERIPH_ID_PWM2:
+		if (mux_con & CON_IOMUX_PWM2SEL_MASK)
+			rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B4_MASK,
+				     GPIO1B4_PWM12 << GPIO1B4_SHIFT);
+		else
+			rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D4_MASK,
+				     GPIO0D4_PWM2 << GPIO0D4_SHIFT);
+		break;
+	case PERIPH_ID_PWM3:
+		if (mux_con & CON_IOMUX_PWM3SEL_MASK)
+			rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B3_MASK,
+				     GPIO1B3_PWM13 << GPIO1B3_SHIFT);
+		else
+			rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D2_MASK,
+				     GPIO3D2_PWM3 << GPIO3D2_SHIFT);
+		break;
+	default:
+		debug("pwm id = %d iomux error!\n", pwm_id);
+		break;
+	}
+}
+
+static void pinctrl_rk322x_i2c_config(struct rk322x_grf *grf, int i2c_id)
+{
+	switch (i2c_id) {
+	case PERIPH_ID_I2C0:
+		rk_clrsetreg(&grf->gpio0a_iomux,
+			     GPIO0A1_MASK | GPIO0A0_MASK,
+			     GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT |
+			     GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT);
+
+		break;
+	case PERIPH_ID_I2C1:
+		rk_clrsetreg(&grf->gpio0a_iomux,
+			     GPIO0A3_MASK | GPIO0A2_MASK,
+			     GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT |
+			     GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT);
+		break;
+	case PERIPH_ID_I2C2:
+		rk_clrsetreg(&grf->gpio2c_iomux,
+			     GPIO2C5_MASK | GPIO2C4_MASK,
+			     GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT |
+			     GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT);
+		break;
+	case PERIPH_ID_I2C3:
+		rk_clrsetreg(&grf->gpio0a_iomux,
+			     GPIO0A7_MASK | GPIO0A6_MASK,
+			     GPIO0A7_I2C3_SDA << GPIO0A7_SHIFT |
+			     GPIO0A6_I2C3_SCL << GPIO0A6_SHIFT);
+
+		break;
+	}
+}
+
+static void pinctrl_rk322x_spi_config(struct rk322x_grf *grf, int cs)
+{
+	switch (cs) {
+	case 0:
+		rk_clrsetreg(&grf->gpio0b_iomux, GPIO0B6_MASK,
+			     GPIO0B6_SPI_CSN0 << GPIO0B6_SHIFT);
+		break;
+	case 1:
+		rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B4_MASK,
+			     GPIO1B4_SPI_CSN1 << GPIO1B4_SHIFT);
+		break;
+	}
+	rk_clrsetreg(&grf->gpio0b_iomux,
+		     GPIO0B1_MASK | GPIO0B3_MASK | GPIO0B5_MASK,
+		     GPIO0B5_SPI_RXD << GPIO0B5_SHIFT |
+		     GPIO0B3_SPI_TXD << GPIO0B3_SHIFT |
+		     GPIO0B1_SPI_CLK << GPIO0B1_SHIFT);
+}
+
+static void pinctrl_rk322x_uart_config(struct rk322x_grf *grf, int uart_id)
+{
+	u32 mux_con = readl(&grf->con_iomux);
+
+	switch (uart_id) {
+	case PERIPH_ID_UART1:
+		if (!(mux_con & CON_IOMUX_UART1SEL_MASK))
+			rk_clrsetreg(&grf->gpio1b_iomux,
+				     GPIO1B1_MASK | GPIO1B2_MASK,
+				     GPIO1B1_UART1_SOUT << GPIO1B1_SHIFT |
+				     GPIO1B2_UART1_SIN << GPIO1B2_SHIFT);
+		break;
+	case PERIPH_ID_UART2:
+		if (mux_con & CON_IOMUX_UART2SEL_MASK)
+			rk_clrsetreg(&grf->gpio1b_iomux,
+				     GPIO1B1_MASK | GPIO1B2_MASK,
+				     GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT |
+				     GPIO1B2_UART21_SIN << GPIO1B2_SHIFT);
+		else
+			rk_clrsetreg(&grf->gpio1c_iomux,
+				     GPIO1C3_MASK | GPIO1C2_MASK,
+				     GPIO1C3_UART2_SIN << GPIO1C3_SHIFT |
+				     GPIO1C2_UART2_SOUT << GPIO1C2_SHIFT);
+		break;
+	}
+}
+
+static void pinctrl_rk322x_sdmmc_config(struct rk322x_grf *grf, int mmc_id)
+{
+	switch (mmc_id) {
+	case PERIPH_ID_EMMC:
+		rk_clrsetreg(&grf->gpio1d_iomux, 0xffff,
+			     GPIO1D7_EMMC_D7 << GPIO1D7_SHIFT |
+			     GPIO1D6_EMMC_D6 << GPIO1D6_SHIFT |
+			     GPIO1D5_EMMC_D5 << GPIO1D5_SHIFT |
+			     GPIO1D4_EMMC_D4 << GPIO1D4_SHIFT |
+			     GPIO1D3_EMMC_D3 << GPIO1D3_SHIFT |
+			     GPIO1D2_EMMC_D2 << GPIO1D2_SHIFT |
+			     GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT |
+			     GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT);
+		rk_clrsetreg(&grf->gpio2a_iomux,
+			     GPIO2A5_MASK | GPIO2A7_MASK,
+			     GPIO2A5_EMMC_PWREN << GPIO2A5_SHIFT |
+			     GPIO2A7_EMMC_CLKOUT << GPIO2A7_SHIFT);
+		rk_clrsetreg(&grf->gpio1c_iomux,
+			     GPIO1C6_MASK | GPIO1C7_MASK,
+			     GPIO1C6_EMMC_CMD << GPIO1C6_SHIFT |
+			     GPIO1C7_EMMC_RSTNOUT << GPIO1C6_SHIFT);
+		break;
+	case PERIPH_ID_SDCARD:
+		rk_clrsetreg(&grf->gpio1b_iomux,
+			     GPIO1B6_MASK | GPIO1B7_MASK,
+			     GPIO1B6_SDMMC_PWREN << GPIO1B6_SHIFT |
+			     GPIO1B7_SDMMC_CMD << GPIO1B6_SHIFT);
+		rk_clrsetreg(&grf->gpio1c_iomux, 0xfff,
+			     GPIO1C5_SDMMC_D3 << GPIO1C5_SHIFT |
+			     GPIO1C4_SDMMC_D2 << GPIO1C4_SHIFT |
+			     GPIO1C3_SDMMC_D1 << GPIO1C3_SHIFT |
+			     GPIO1C2_SDMMC_D0 << GPIO1C2_SHIFT |
+			     GPIO1C1_SDMMC_DETN << GPIO1C1_SHIFT |
+			     GPIO1C0_SDMMC_CLKOUT << GPIO1C0_SHIFT);
+		break;
+	}
+}
+
+static int rk322x_pinctrl_request(struct udevice *dev, int func, int flags)
+{
+	struct rk322x_pinctrl_priv *priv = dev_get_priv(dev);
+
+	debug("%s: func=%x, flags=%x\n", __func__, func, flags);
+	switch (func) {
+	case PERIPH_ID_PWM0:
+	case PERIPH_ID_PWM1:
+	case PERIPH_ID_PWM2:
+	case PERIPH_ID_PWM3:
+		pinctrl_rk322x_pwm_config(priv->grf, func);
+		break;
+	case PERIPH_ID_I2C0:
+	case PERIPH_ID_I2C1:
+	case PERIPH_ID_I2C2:
+		pinctrl_rk322x_i2c_config(priv->grf, func);
+		break;
+	case PERIPH_ID_SPI0:
+		pinctrl_rk322x_spi_config(priv->grf, flags);
+		break;
+	case PERIPH_ID_UART0:
+	case PERIPH_ID_UART1:
+	case PERIPH_ID_UART2:
+		pinctrl_rk322x_uart_config(priv->grf, func);
+		break;
+	case PERIPH_ID_SDMMC0:
+	case PERIPH_ID_SDMMC1:
+		pinctrl_rk322x_sdmmc_config(priv->grf, func);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int rk322x_pinctrl_get_periph_id(struct udevice *dev,
+					struct udevice *periph)
+{
+	u32 cell[3];
+	int ret;
+
+	ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
+				   "interrupts", cell, ARRAY_SIZE(cell));
+	if (ret < 0)
+		return -EINVAL;
+
+	switch (cell[1]) {
+	case 12:
+		return PERIPH_ID_SDCARD;
+	case 14:
+		return PERIPH_ID_EMMC;
+	case 36:
+		return PERIPH_ID_I2C0;
+	case 37:
+		return PERIPH_ID_I2C1;
+	case 38:
+		return PERIPH_ID_I2C2;
+	case 49:
+		return PERIPH_ID_SPI0;
+	case 50:
+		return PERIPH_ID_PWM0;
+	case 55:
+		return PERIPH_ID_UART0;
+	case 56:
+		return PERIPH_ID_UART1;
+	case 57:
+		return PERIPH_ID_UART2;
+	}
+	return -ENOENT;
+}
+
+static int rk322x_pinctrl_set_state_simple(struct udevice *dev,
+					   struct udevice *periph)
+{
+	int func;
+
+	func = rk322x_pinctrl_get_periph_id(dev, periph);
+	if (func < 0)
+		return func;
+	return rk322x_pinctrl_request(dev, func, 0);
+}
+
+static struct pinctrl_ops rk322x_pinctrl_ops = {
+	.set_state_simple	= rk322x_pinctrl_set_state_simple,
+	.request	= rk322x_pinctrl_request,
+	.get_periph_id	= rk322x_pinctrl_get_periph_id,
+};
+
+static int rk322x_pinctrl_probe(struct udevice *dev)
+{
+	struct rk322x_pinctrl_priv *priv = dev_get_priv(dev);
+
+	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	debug("%s: grf=%p\n", __func__, priv->grf);
+	return 0;
+}
+
+static const struct udevice_id rk322x_pinctrl_ids[] = {
+	{ .compatible = "rockchip,rk322x-pinctrl" },
+	{ }
+};
+
+U_BOOT_DRIVER(pinctrl_rk322x) = {
+	.name		= "pinctrl_rk322x",
+	.id		= UCLASS_PINCTRL,
+	.of_match	= rk322x_pinctrl_ids,
+	.priv_auto_alloc_size = sizeof(struct rk322x_pinctrl_priv),
+	.ops		= &rk322x_pinctrl_ops,
+	.bind		= dm_scan_fdt_dev,
+	.probe		= rk322x_pinctrl_probe,
+};
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3288.c b/drivers/pinctrl/rockchip/pinctrl_rk3288.c
index cb13d30da8e..3c9ae974f47 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3288.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3288.c
@@ -402,6 +402,119 @@ static void pinctrl_rk3288_sdmmc_config(struct rk3288_grf *grf, int mmc_id)
 	}
 }
 
+static void pinctrl_rk3288_gmac_config(struct rk3288_grf *grf, int gmac_id)
+{
+	switch (gmac_id) {
+	case PERIPH_ID_GMAC:
+		rk_clrsetreg(&grf->gpio3dl_iomux,
+			     GPIO3D3_MASK << GPIO3D3_SHIFT |
+			     GPIO3D2_MASK << GPIO3D2_SHIFT |
+			     GPIO3D2_MASK << GPIO3D1_SHIFT |
+			     GPIO3D0_MASK << GPIO3D0_SHIFT,
+			     GPIO3D3_MAC_RXD3 << GPIO3D3_SHIFT |
+			     GPIO3D2_MAC_RXD2 << GPIO3D2_SHIFT |
+			     GPIO3D1_MAC_TXD3 << GPIO3D1_SHIFT |
+			     GPIO3D0_MAC_TXD2 << GPIO3D0_SHIFT);
+
+		rk_clrsetreg(&grf->gpio3dh_iomux,
+			     GPIO3D7_MASK << GPIO3D7_SHIFT |
+			     GPIO3D6_MASK << GPIO3D6_SHIFT |
+			     GPIO3D5_MASK << GPIO3D5_SHIFT |
+			     GPIO3D4_MASK << GPIO3D4_SHIFT,
+			     GPIO3D7_MAC_RXD1 << GPIO3D7_SHIFT |
+			     GPIO3D6_MAC_RXD0 << GPIO3D6_SHIFT |
+			     GPIO3D5_MAC_TXD1 << GPIO3D5_SHIFT |
+			     GPIO3D4_MAC_TXD0 << GPIO3D4_SHIFT);
+
+		/* switch the Tx pins to 12ma drive-strength */
+		rk_clrsetreg(&grf->gpio1_e[2][3],
+			     GPIO_BIAS_MASK |
+			     (GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(1)) |
+			     (GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(4)) |
+			     (GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(5)),
+			     (GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(0)) |
+			     (GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(1)) |
+			     (GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(4)) |
+			     (GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(5)));
+
+		/* Set normal pull for all GPIO3D pins */
+		rk_clrsetreg(&grf->gpio1_p[2][3],
+			     (GPIO_PULL_MASK << GPIO_PULL_SHIFT(0)) |
+			     (GPIO_PULL_MASK << GPIO_PULL_SHIFT(1)) |
+			     (GPIO_PULL_MASK << GPIO_PULL_SHIFT(2)) |
+			     (GPIO_PULL_MASK << GPIO_PULL_SHIFT(3)) |
+			     (GPIO_PULL_MASK << GPIO_PULL_SHIFT(4)) |
+			     (GPIO_PULL_MASK << GPIO_PULL_SHIFT(5)) |
+			     (GPIO_PULL_MASK << GPIO_PULL_SHIFT(5)) |
+			     (GPIO_PULL_MASK << GPIO_PULL_SHIFT(7)),
+			     (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(0)) |
+			     (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(1)) |
+			     (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(2)) |
+			     (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(3)) |
+			     (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(4)) |
+			     (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(5)) |
+			     (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(6)) |
+			     (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(7)));
+
+		rk_clrsetreg(&grf->gpio4al_iomux,
+			     GPIO4A3_MASK << GPIO4A3_SHIFT |
+			     GPIO4A1_MASK << GPIO4A1_SHIFT |
+			     GPIO4A0_MASK << GPIO4A0_SHIFT,
+			     GPIO4A3_MAC_CLK << GPIO4A3_SHIFT |
+			     GPIO4A1_MAC_TXDV << GPIO4A1_SHIFT |
+			     GPIO4A0_MAC_MDC << GPIO4A0_SHIFT);
+
+		rk_clrsetreg(&grf->gpio4ah_iomux,
+			     GPIO4A6_MASK << GPIO4A6_SHIFT |
+			     GPIO4A5_MASK << GPIO4A5_SHIFT |
+			     GPIO4A4_MASK << GPIO4A4_SHIFT,
+			     GPIO4A6_MAC_RXCLK << GPIO4A6_SHIFT |
+			     GPIO4A5_MAC_MDIO << GPIO4A5_SHIFT |
+			     GPIO4A4_MAC_TXEN << GPIO4A4_SHIFT);
+
+		/* switch GPIO4A4 to 12ma drive-strength */
+		rk_clrsetreg(&grf->gpio1_e[3][0],
+			     GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(4),
+			     GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(4));
+
+		/* Set normal pull for all GPIO4A pins */
+		rk_clrsetreg(&grf->gpio1_p[3][0],
+			     (GPIO_PULL_MASK << GPIO_PULL_SHIFT(0)) |
+			     (GPIO_PULL_MASK << GPIO_PULL_SHIFT(1)) |
+			     (GPIO_PULL_MASK << GPIO_PULL_SHIFT(2)) |
+			     (GPIO_PULL_MASK << GPIO_PULL_SHIFT(3)) |
+			     (GPIO_PULL_MASK << GPIO_PULL_SHIFT(4)) |
+			     (GPIO_PULL_MASK << GPIO_PULL_SHIFT(5)) |
+			     (GPIO_PULL_MASK << GPIO_PULL_SHIFT(5)) |
+			     (GPIO_PULL_MASK << GPIO_PULL_SHIFT(7)),
+			     (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(0)) |
+			     (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(1)) |
+			     (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(2)) |
+			     (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(3)) |
+			     (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(4)) |
+			     (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(5)) |
+			     (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(6)) |
+			     (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(7)));
+
+		/* switch GPIO4B1 to 12ma drive-strength */
+		rk_clrsetreg(&grf->gpio1_e[3][1],
+			     GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(1),
+			     GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(1));
+
+		/* Set pull normal for GPIO4B1, pull up for GPIO4B0 */
+		rk_clrsetreg(&grf->gpio1_p[3][1],
+			     (GPIO_PULL_MASK << GPIO_PULL_SHIFT(0)) |
+			     (GPIO_PULL_MASK << GPIO_PULL_SHIFT(1)),
+			     (GPIO_PULL_UP << GPIO_PULL_SHIFT(0)) |
+			     (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(1)));
+
+		break;
+	default:
+		printf("gmac id = %d iomux error!\n", gmac_id);
+		break;
+	}
+}
+
 #ifndef CONFIG_SPL_BUILD
 static void pinctrl_rk3288_hdmi_config(struct rk3288_grf *grf, int hdmi_id)
 {
@@ -465,6 +578,9 @@ static int rk3288_pinctrl_request(struct udevice *dev, int func, int flags)
 	case PERIPH_ID_SDMMC1:
 		pinctrl_rk3288_sdmmc_config(priv->grf, func);
 		break;
+	case PERIPH_ID_GMAC:
+		pinctrl_rk3288_gmac_config(priv->grf, func);
+		break;
 	default:
 		return -EINVAL;
 	}
@@ -479,12 +595,13 @@ static int rk3288_pinctrl_get_periph_id(struct udevice *dev,
 	u32 cell[3];
 	int ret;
 
-	ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
-				   "interrupts", cell, ARRAY_SIZE(cell));
+	ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
 	if (ret < 0)
 		return -EINVAL;
 
 	switch (cell[1]) {
+	case 27:
+		return PERIPH_ID_GMAC;
 	case 44:
 		return PERIPH_ID_SPI0;
 	case 45:
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3328.c b/drivers/pinctrl/rockchip/pinctrl_rk3328.c
index d0ffeb1f044..c74163e026a 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3328.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3328.c
@@ -184,13 +184,11 @@ static void pinctrl_rk3328_sdmmc_config(struct rk3328_grf_regs *grf,
 		if (com_iomux & IOMUX_SEL_SDMMC_MASK)
 			rk_clrsetreg(&grf->gpio0d_iomux,
 				     GPIO0D6_SEL_MASK,
-				     GPIO0D6_SDMMC0_PWRENM1
-				     << GPIO0D6_SEL_SHIFT);
+				     GPIO0D6_GPIO << GPIO0D6_SEL_SHIFT);
 		else
 			rk_clrsetreg(&grf->gpio2a_iomux,
 				     GPIO2A7_SEL_MASK,
-				     GPIO2A7_SDMMC0_PWRENM0
-				     << GPIO2A7_SEL_SHIFT);
+				     GPIO2A7_GPIO << GPIO2A7_SEL_SHIFT);
 		rk_clrsetreg(&grf->gpio1a_iomux,
 			     GPIO1A0_SEL_MASK,
 			     GPIO1A0_CARD_DATA_CLK_CMD_DETN
@@ -251,8 +249,7 @@ static int rk3328_pinctrl_get_periph_id(struct udevice *dev,
 	u32 cell[3];
 	int ret;
 
-	ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
-				   "interrupts", cell, ARRAY_SIZE(cell));
+	ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
 	if (ret < 0)
 		return -EINVAL;
 
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c b/drivers/pinctrl/rockchip/pinctrl_rk3399.c
index d93b90310b0..cab268c7d6c 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3399.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3399.c
@@ -350,8 +350,7 @@ static int rk3399_pinctrl_get_periph_id(struct udevice *dev,
 	u32 cell[3];
 	int ret;
 
-	ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
-				   "interrupts", cell, ARRAY_SIZE(cell));
+	ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
 	if (ret < 0)
 		return -EINVAL;
 
diff --git a/drivers/pinctrl/rockchip/pinctrl_rv1108.c b/drivers/pinctrl/rockchip/pinctrl_rv1108.c
index bdf3910a885..cda94f49575 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rv1108.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rv1108.c
@@ -108,8 +108,7 @@ static int rv1108_pinctrl_get_periph_id(struct udevice *dev,
 	u32 cell[3];
 	int ret;
 
-	ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
-				   "interrupts", cell, ARRAY_SIZE(cell));
+	ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
 	if (ret < 0)
 		return -EINVAL;
 
diff --git a/drivers/power/regulator/rk8xx.c b/drivers/power/regulator/rk8xx.c
index c1ece96b66f..7c0a3aaa895 100644
--- a/drivers/power/regulator/rk8xx.c
+++ b/drivers/power/regulator/rk8xx.c
@@ -30,6 +30,9 @@
 #define RK818_LDO_VSEL_MASK		0x1f
 #define RK818_LDO3_ON_VSEL_MASK	0xf
 #define RK818_BOOST_ON_VSEL_MASK	0xe0
+#define RK818_USB_ILIM_SEL_MASK		0x0f
+#define RK818_USB_CHG_SD_VSEL_MASK	0x70
+
 
 struct rk8xx_reg_info {
 	uint min_uv;
@@ -45,6 +48,14 @@ static const struct rk8xx_reg_info rk808_buck[] = {
 	{ 1800000, 100000, REG_BUCK4_ON_VSEL, RK808_BUCK4_VSEL_MASK, },
 };
 
+static const struct rk8xx_reg_info rk818_buck[] = {
+	{ 712500, 12500, REG_BUCK1_ON_VSEL, RK818_BUCK_VSEL_MASK, },
+	{ 712500, 12500, REG_BUCK2_ON_VSEL, RK818_BUCK_VSEL_MASK, },
+	{ 712500, 12500, -1, RK818_BUCK_VSEL_MASK, },
+	{ 1800000, 100000, REG_BUCK4_ON_VSEL, RK818_BUCK4_VSEL_MASK, },
+};
+
+#ifdef ENABLE_DRIVER
 static const struct rk8xx_reg_info rk808_ldo[] = {
 	{ 1800000, 100000, REG_LDO1_ON_VSEL, RK808_LDO_VSEL_MASK, },
 	{ 1800000, 100000, REG_LDO2_ON_VSEL, RK808_LDO_VSEL_MASK, },
@@ -56,13 +67,6 @@ static const struct rk8xx_reg_info rk808_ldo[] = {
 	{ 1800000, 100000, REG_LDO8_ON_VSEL, RK808_LDO_VSEL_MASK, },
 };
 
-static const struct rk8xx_reg_info rk818_buck[] = {
-	{ 712500, 12500, REG_BUCK1_ON_VSEL, RK818_BUCK_VSEL_MASK, },
-	{ 712500, 12500, REG_BUCK2_ON_VSEL, RK818_BUCK_VSEL_MASK, },
-	{ 712500, 12500, -1, RK818_BUCK_VSEL_MASK, },
-	{ 1800000, 100000, REG_BUCK4_ON_VSEL, RK818_BUCK4_VSEL_MASK, },
-};
-
 static const struct rk8xx_reg_info rk818_ldo[] = {
 	{ 1800000, 100000, REG_LDO1_ON_VSEL, RK818_LDO_VSEL_MASK, },
 	{ 1800000, 100000, REG_LDO2_ON_VSEL, RK818_LDO_VSEL_MASK, },
@@ -73,6 +77,15 @@ static const struct rk8xx_reg_info rk818_ldo[] = {
 	{ 800000, 100000, REG_LDO7_ON_VSEL, RK818_LDO_VSEL_MASK, },
 	{ 1800000, 100000, REG_LDO8_ON_VSEL, RK818_LDO_VSEL_MASK, },
 };
+#endif
+
+static const u16 rk818_chrg_cur_input_array[] = {
+	450, 800, 850, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000
+};
+
+static const uint rk818_chrg_shutdown_vsel_array[] = {
+	2780000, 2850000, 2920000, 2990000, 3060000, 3130000, 3190000, 3260000
+};
 
 static const struct rk8xx_reg_info *get_buck_reg(struct udevice *pmic,
 					     int num)
@@ -86,18 +99,6 @@ static const struct rk8xx_reg_info *get_buck_reg(struct udevice *pmic,
 	}
 }
 
-static const struct rk8xx_reg_info *get_ldo_reg(struct udevice *pmic,
-					     int num)
-{
-	struct rk8xx_priv *priv = dev_get_priv(pmic);
-	switch (priv->variant) {
-	case RK818_ID:
-		return &rk818_ldo[num];
-	default:
-		return &rk808_ldo[num];
-	}
-}
-
 static int _buck_set_value(struct udevice *pmic, int buck, int uvolt)
 {
 	const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck - 1);
@@ -133,6 +134,18 @@ static int _buck_set_enable(struct udevice *pmic, int buck, bool enable)
 }
 
 #ifdef ENABLE_DRIVER
+static const struct rk8xx_reg_info *get_ldo_reg(struct udevice *pmic,
+					     int num)
+{
+	struct rk8xx_priv *priv = dev_get_priv(pmic);
+	switch (priv->variant) {
+	case RK818_ID:
+		return &rk818_ldo[num];
+	default:
+		return &rk808_ldo[num];
+	}
+}
+
 static int buck_get_value(struct udevice *dev)
 {
 	int buck = dev->driver_data - 1;
@@ -351,3 +364,26 @@ int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt)
 
 	return _buck_set_enable(pmic, buck, true);
 }
+
+int rk818_spl_configure_usb_input_current(struct udevice *pmic, int current_ma)
+{
+	uint i;
+
+	for (i = 0; i < ARRAY_SIZE(rk818_chrg_cur_input_array); i++)
+		if (current_ma <= rk818_chrg_cur_input_array[i])
+			break;
+
+	return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_ILIM_SEL_MASK, i);
+}
+
+int rk818_spl_configure_usb_chrg_shutdown(struct udevice *pmic, int uvolt)
+{
+	uint i;
+
+	for (i = 0; i < ARRAY_SIZE(rk818_chrg_shutdown_vsel_array); i++)
+		if (uvolt <= rk818_chrg_shutdown_vsel_array[i])
+			break;
+
+	return pmic_clrsetbits(pmic, REG_USB_CTRL, RK818_USB_CHG_SD_VSEL_MASK,
+			       i);
+}
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 52c52c1ad14..e0e70244ce4 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -434,10 +434,8 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
 	plat->base = (unsigned long)map_physmem(addr, 0, MAP_NOCACHE);
 #endif
 
-	plat->reg_offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
-				     "reg-offset", 0);
-	plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
-					 "reg-shift", 0);
+	plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0);
+	plat->reg_shift = dev_read_u32_default(dev, "reg-shift", 0);
 
 	err = clk_get_by_index(dev, 0, &clk);
 	if (!err) {
@@ -450,9 +448,8 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
 	}
 
 	if (!plat->clock)
-		plat->clock = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
-					     "clock-frequency",
-					     CONFIG_SYS_NS16550_CLK);
+		plat->clock = dev_read_u32_default(dev, "clock-frequency",
+						   CONFIG_SYS_NS16550_CLK);
 	if (!plat->clock) {
 		debug("ns16550 clock not defined\n");
 		return -EINVAL;
diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index a8f0eb0be6f..7921ea0d754 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -182,8 +182,6 @@ static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 	struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
 	struct rockchip_spi_priv *priv = dev_get_priv(bus);
-	const void *blob = gd->fdt_blob;
-	int node = dev_of_offset(bus);
 	int ret;
 
 	plat->base = devfdt_get_addr(bus);
@@ -195,12 +193,13 @@ static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
 		return ret;
 	}
 
-	plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
-					 50000000);
-	plat->deactivate_delay_us = fdtdec_get_int(blob, node,
-					"spi-deactivate-delay", 0);
-	plat->activate_delay_us = fdtdec_get_int(blob, node,
-						 "spi-activate-delay", 0);
+	plat->frequency =
+		dev_read_u32_default(bus, "spi-max-frequency", 50000000);
+	plat->deactivate_delay_us =
+		dev_read_u32_default(bus, "spi-deactivate-delay", 0);
+	plat->activate_delay_us =
+		dev_read_u32_default(bus, "spi-activate-delay", 0);
+
 	debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
 	      __func__, (uint)plat->base, plat->frequency,
 	      plat->deactivate_delay_us);
diff --git a/drivers/sysreset/sysreset_rk322x.c b/drivers/sysreset/sysreset_rk322x.c
new file mode 100644
index 00000000000..5fce79b685f
--- /dev/null
+++ b/drivers/sysreset/sysreset_rk322x.c
@@ -0,0 +1,45 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk322x.h>
+#include <asm/arch/hardware.h>
+#include <linux/err.h>
+
+int rk322x_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+	struct rk322x_cru *cru = rockchip_get_cru();
+
+	if (IS_ERR(cru))
+		return PTR_ERR(cru);
+	switch (type) {
+	case SYSRESET_WARM:
+		writel(0xeca8, &cru->cru_glb_srst_snd_value);
+		break;
+	case SYSRESET_COLD:
+		writel(0xfdb9, &cru->cru_glb_srst_fst_value);
+		break;
+	default:
+		return -EPROTONOSUPPORT;
+	}
+
+	return -EINPROGRESS;
+}
+
+static struct sysreset_ops rk322x_sysreset = {
+	.request	= rk322x_sysreset_request,
+};
+
+U_BOOT_DRIVER(sysreset_rk322x) = {
+	.name	= "rk322x_sysreset",
+	.id	= UCLASS_SYSRESET,
+	.ops	= &rk322x_sysreset,
+};
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index b824eec41d9..bc2c1f17e58 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -34,6 +34,8 @@ config USB_XHCI_MVEBU
 config USB_XHCI_ROCKCHIP
 	bool "Support for Rockchip on-chip xHCI USB controller"
 	depends on ARCH_ROCKCHIP
+	depends on DM_REGULATOR
+	depends on DM_USB
 	default y
 	help
 	  Enables support for the on-chip xHCI controller on Rockchip SoCs.
@@ -199,3 +201,13 @@ config USB_UHCI_HCD
 if USB_UHCI_HCD
 
 endif # USB_UHCI_HCD
+
+config USB_DWC2
+	bool "DesignWare USB2 Core support"
+	select USB_HOST
+	---help---
+	  The DesignWare USB 2.0 controller is compliant with the
+	  USB-Implementers Forum (USB-IF) USB 2.0 specifications.
+	  Hi-Speed (480 Mbps), Full-Speed (12 Mbps), and Low-Speed (1.5 Mbps)
+	  operation is compliant to the controller Supplement. If you want to
+	  enable this controller in host mode, say Y.
diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index 841e596700c..64c42ac4715 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -43,6 +43,10 @@ struct dwc2_priv {
 	struct dwc2_core_regs *regs;
 	int root_hub_devnum;
 	bool ext_vbus;
+	/*
+	 * The hnp/srp capability must be disabled if the platform
+	 * does't support hnp/srp. Otherwise the force mode can't work.
+	 */
 	bool hnp_srp_disable;
 	bool oc_disable;
 };
@@ -1239,7 +1243,6 @@ static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
 {
 	struct dwc2_priv *priv = dev_get_priv(dev);
-	const void *prop;
 	fdt_addr_t addr;
 
 	addr = devfdt_get_addr(dev);
@@ -1247,15 +1250,8 @@ static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
 		return -EINVAL;
 	priv->regs = (struct dwc2_core_regs *)addr;
 
-	prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
-			   "disable-over-current", NULL);
-	if (prop)
-		priv->oc_disable = true;
-
-	prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
-			   "hnp-srp-disable", NULL);
-	if (prop)
-		priv->hnp_srp_disable = true;
+	priv->oc_disable = dev_read_bool(dev, "disable-over-current");
+	priv->hnp_srp_disable = dev_read_bool(dev, "hnp-srp-disable");
 
 	return 0;
 }
diff --git a/drivers/usb/host/xhci-rockchip.c b/drivers/usb/host/xhci-rockchip.c
index c4ae55fc390..ec55f4e59f7 100644
--- a/drivers/usb/host/xhci-rockchip.c
+++ b/drivers/usb/host/xhci-rockchip.c
@@ -48,7 +48,7 @@ static int xhci_usb_ofdata_to_platdata(struct udevice *dev)
 	 */
 	plat->hcd_base = devfdt_get_addr(dev);
 	if (plat->hcd_base == FDT_ADDR_T_NONE) {
-		debug("Can't get the XHCI register base address\n");
+		error("Can't get the XHCI register base address\n");
 		return -ENXIO;
 	}
 
@@ -62,17 +62,15 @@ static int xhci_usb_ofdata_to_platdata(struct udevice *dev)
 	}
 
 	if (plat->phy_base == FDT_ADDR_T_NONE) {
-		debug("Can't get the usbphy register address\n");
+		error("Can't get the usbphy register address\n");
 		return -ENXIO;
 	}
 
-#if defined(CONFIG_DM_USB) && defined(CONFIG_DM_REGULATOR)
 	/* Vbus regulator */
 	ret = device_get_supply_regulator(dev, "vbus-supply",
 					  &plat->vbus_supply);
 	if (ret)
-		debug("Can't get vbus supply\n");
-#endif
+		debug("Can't get VBus regulator!\n");
 
 	return 0;
 }
@@ -86,18 +84,15 @@ static void rockchip_dwc3_phy_setup(struct dwc3 *dwc3_reg,
 				    struct udevice *dev)
 {
 	u32 reg;
-	const void *blob = gd->fdt_blob;
 	u32 utmi_bits;
 
 	/* Set dwc3 usb2 phy config */
 	reg = readl(&dwc3_reg->g_usb2phycfg[0]);
 
-	if (fdtdec_get_bool(blob, dev_of_offset(dev),
-			    "snps,dis-enblslpm-quirk"))
+	if (dev_read_bool(dev, "snps,dis-enblslpm-quirk"))
 		reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 
-	utmi_bits = fdtdec_get_int(blob, dev_of_offset(dev),
-				   "snps,phyif-utmi-bits", -1);
+	utmi_bits = dev_read_u32_default(dev, "snps,phyif-utmi-bits", -1);
 	if (utmi_bits == 16) {
 		reg |= DWC3_GUSB2PHYCFG_PHYIF;
 		reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
@@ -108,12 +103,10 @@ static void rockchip_dwc3_phy_setup(struct dwc3 *dwc3_reg,
 		reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT;
 	}
 
-	if (fdtdec_get_bool(blob, dev_of_offset(dev),
-			    "snps,dis-u2-freeclk-exists-quirk"))
+	if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk"))
 		reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
 
-	if (fdtdec_get_bool(blob, dev_of_offset(dev),
-			    "snps,dis-u2-susphy-quirk"))
+	if (dev_read_bool(dev, "snps,dis-u2-susphy-quirk"))
 		reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 
 	writel(reg, &dwc3_reg->g_usb2phycfg[0]);
@@ -126,7 +119,7 @@ static int rockchip_xhci_core_init(struct rockchip_xhci *rkxhci,
 
 	ret = dwc3_core_init(rkxhci->dwc3_reg);
 	if (ret) {
-		debug("failed to initialize core\n");
+		error("failed to initialize core\n");
 		return ret;
 	}
 
@@ -155,15 +148,17 @@ static int xhci_usb_probe(struct udevice *dev)
 	hcor = (struct xhci_hcor *)((uint64_t)ctx->hcd +
 			HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase)));
 
-#if defined(CONFIG_DM_USB) && defined(CONFIG_DM_REGULATOR)
-	ret = regulator_set_enable(plat->vbus_supply, true);
-	if (ret)
-		debug("XHCI: Failed to enable vbus supply\n");
-#endif
+	if (plat->vbus_supply) {
+		ret = regulator_set_enable(plat->vbus_supply, true);
+		if (ret) {
+			error("XHCI: failed to set VBus supply\n");
+			return ret;
+		}
+	}
 
 	ret = rockchip_xhci_core_init(ctx, dev);
 	if (ret) {
-		debug("XHCI: failed to initialize controller\n");
+		error("XHCI: failed to initialize controller\n");
 		return ret;
 	}
 
@@ -183,13 +178,13 @@ static int xhci_usb_remove(struct udevice *dev)
 	if (ret)
 		return ret;
 
-#if defined(CONFIG_DM_USB) && defined(CONFIG_DM_REGULATOR)
-	ret = regulator_set_enable(plat->vbus_supply, false);
-	if (ret)
-		debug("XHCI: Failed to disable vbus supply\n");
-#endif
+	if (plat->vbus_supply) {
+		ret = regulator_set_enable(plat->vbus_supply, false);
+		if (ret)
+			error("XHCI: failed to set VBus supply\n");
+	}
 
-	return 0;
+	return ret;
 }
 
 static const struct udevice_id xhci_usb_ids[] = {
diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c
index ad003970d68..1199a30c1a5 100644
--- a/drivers/video/rockchip/rk_mipi.c
+++ b/drivers/video/rockchip/rk_mipi.c
@@ -40,7 +40,7 @@ DECLARE_GLOBAL_DATA_PTR;
  * @txesc_clk: clock for tx esc mode
  */
 struct rk_mipi_priv {
-	void __iomem *regs;
+	uintptr_t regs;
 	struct rk3399_grf_regs *grf;
 	struct udevice *panel;
 	struct mipi_dsi *dsi;
@@ -76,13 +76,13 @@ static int rk_mipi_read_timing(struct udevice *dev,
  *        use define in rk_mipi.h directly for this parameter
  *  @val: value that will be write to specified bits of register
  */
-static void rk_mipi_dsi_write(u32 regs, u32 reg, u32 val)
+static void rk_mipi_dsi_write(uintptr_t regs, u32 reg, u32 val)
 {
 	u32 dat;
 	u32 mask;
 	u32 offset = (reg >> OFFSET_SHIFT) & 0xff;
 	u32 bits = (reg >> BITS_SHIFT) & 0xff;
-	u64 addr = (reg >> ADDR_SHIFT) + regs;
+	uintptr_t addr = (reg >> ADDR_SHIFT) + regs;
 
 	/* Mask for specifiled bits,the corresponding bits will be clear */
 	mask = ~((0xffffffff << offset) & (0xffffffff >> (32 - offset - bits)));
@@ -108,7 +108,7 @@ static int rk_mipi_dsi_enable(struct udevice *dev,
 	int node, timing_node;
 	int val;
 	struct rk_mipi_priv *priv = dev_get_priv(dev);
-	u64 regs = (u64)priv->regs;
+	uintptr_t regs = priv->regs;
 	struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev);
 	u32 txbyte_clk = priv->txbyte_clk;
 	u32 txesc_clk = priv->txesc_clk;
@@ -224,7 +224,7 @@ static int rk_mipi_dsi_enable(struct udevice *dev,
 }
 
 /* rk mipi dphy write function. It is used to write test data to dphy */
-static void rk_mipi_phy_write(u32 regs, unsigned char test_code,
+static void rk_mipi_phy_write(uintptr_t regs, unsigned char test_code,
 			      unsigned char *test_data, unsigned char size)
 {
 	int i = 0;
@@ -253,7 +253,7 @@ static int rk_mipi_phy_enable(struct udevice *dev)
 {
 	int i;
 	struct rk_mipi_priv *priv = dev_get_priv(dev);
-	u64 regs = (u64)priv->regs;
+	uintptr_t regs = priv->regs;
 	u64 fbdiv;
 	u64 prediv = 1;
 	u32 max_fbdiv = 512;
@@ -437,14 +437,14 @@ static int rk_mipi_ofdata_to_platdata(struct udevice *dev)
 
 	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 	if (priv->grf <= 0) {
-		debug("%s: Get syscon grf failed (ret=%llu)\n",
-		      __func__, (u64)priv->grf);
+		debug("%s: Get syscon grf failed (ret=%p)\n",
+		      __func__, priv->grf);
 		return  -ENXIO;
 	}
-	priv->regs = (void *)devfdt_get_addr(dev);
+	priv->regs = devfdt_get_addr(dev);
 	if (priv->regs <= 0) {
-		debug("%s: Get MIPI dsi address failed (ret=%llu)\n", __func__,
-		      (u64)priv->regs);
+		debug("%s: Get MIPI dsi address failed (ret=%lu)\n", __func__,
+		      priv->regs);
 		return  -ENXIO;
 	}