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authorMarek Vasut <marek.vasut+renesas@gmail.com>2018-06-13 08:02:55 +0200
committerMarek Vasut <marex@denx.de>2018-11-02 15:57:13 +0100
commit0ff9e4800f21e4250ac8a6ca908de00851f896d8 (patch)
tree655e4447704202bfdde805aa3c939c852885b5c6 /drivers
parentfdaccfeb5e03e18c05be386b8a7c6be02be2cf15 (diff)
pinctrl: renesas: Fix DRV register offset
Use fixed 4bit size for generating the DRV register element mask, not the size of the value, which can be smaller. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/pinctrl/renesas/pfc.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c
index 90011537a85..b3a4ff9049d 100644
--- a/drivers/pinctrl/renesas/pfc.c
+++ b/drivers/pinctrl/renesas/pfc.c
@@ -591,7 +591,7 @@ static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
strength = strength / step - 1;
val = sh_pfc_read_raw_reg(reg, 32);
- val &= ~GENMASK(offset + size - 1, offset);
+ val &= ~GENMASK(offset + 4 - 1, offset);
val |= strength << offset;
if (unlock_reg)