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authorwdenk <wdenk>2003-07-14 22:13:32 +0000
committerwdenk <wdenk>2003-07-14 22:13:32 +0000
commit8564acf936726c5568d71e4fa93a0ae9814e0d07 (patch)
tree05fa981555adf1d333970f3d52d0683008fe3cfb /include/asm-ppc/processor.h
parent5702923e23238df6c6f62d53f73863462ae62f4e (diff)
* Patches by Yuli Barcohen, 13 Jul 2003:
- Correct flash and JFFS2 support for MPC8260ADS - fix PVR values and clock generation for PowerQUICC II family (8270/8275/8280) * Patch by Bernhard Kuhn, 08 Jul 2003: - add support for M68K targets * Patch by Ken Chou, 3 Jul: - Fix PCI config table for A3000 - Fix iobase for natsemi.c (PCI_BASE_ADDRESS_0 is the IO base register for DP83815) * Allow to enable "slow" POST routines by key press on power-on * Fix temperature dependend switching of LCD backlight on LWMON * Tweak output format for LWMON
Diffstat (limited to 'include/asm-ppc/processor.h')
-rw-r--r--include/asm-ppc/processor.h9
1 files changed, 8 insertions, 1 deletions
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 8835139c810..726102da268 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -524,8 +524,15 @@
#define PVR_860 PVR_821
#define PVR_7400 0x000C0000
#define PVR_8240 0x00810100
-#define PVR_8260 PVR_8240
+/*
+ * PowerQUICC II family processors report different PVR values depending
+ * on silicon process (HiP3, HiP4, HiP7, etc.)
+ */
+#define PVR_8260 PVR_8240
+#define PVR_8260_HIP3 0x00810101
+#define PVR_8260_HIP4 0x80811014
+#define PVR_8260_HIP7 0x80822011
/* I am just adding a single entry for 8260 boards. I think we may be
* able to combine mbx, fads, rpxlite, bseip, and classic into a single