diff options
| author | Sandeep Gopalpet <sandeep.kumar@freescale.com> | 2010-03-12 10:45:02 +0530 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2010-04-07 00:21:27 -0500 |
| commit | ff8473e90a018c2bb19a196176c1f2e9602d6354 (patch) | |
| tree | 52f1171686c26eacb52bbf3837f90abc3d86ea32 /include/asm-ppc | |
| parent | 216082754f6da5359ea0db9b0cc03ad531ac6e45 (diff) | |
85xx: Set HID1[mbdd] on e500v2 rev5.0 or greater
The HID1[MBDD] bit is new on rev5.0 or greater cores and will optimize
the performance of mbar/eieio instructions.
Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com>
Diffstat (limited to 'include/asm-ppc')
| -rw-r--r-- | include/asm-ppc/processor.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 2b027747155..9ec319ae170 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -265,6 +265,7 @@ #define HID1_RFXE (1<<17) /* Read Fault Exception Enable */ #define HID1_ASTME (1<<13) /* Address bus streaming mode */ #define HID1_ABE (1<<12) /* Address broadcast enable */ +#define HID1_MBDD (1<<6) /* optimized sync instruction */ #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ #ifndef CONFIG_BOOKE #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ |