diff options
author | Bartlomiej Sieka <tur@semihalf.com> | 2006-03-05 18:57:33 +0100 |
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committer | Bartlomiej Sieka <tur@semihalf.com> | 2006-03-05 18:57:33 +0100 |
commit | addb2e1650fdf872334478393f482dfdce965a61 (patch) | |
tree | c16d3de22d1e1040d3f8e6ecfaed20bf2f2c5ea6 /include/configs/CPCI405.h | |
parent | 038ccac511214b062c56f22b9413f784b86bcd87 (diff) |
Re-factoring the legacy NAND code (legacy NAND now only in board-specific
code and in SoC code). Boards using the old way have CFG_NAND_LEGACY and
BOARDLIBS = drivers/nand_legacy/libnand_legacy.a added. Build breakage for
NETTA.ERR and NETTA_ISDN - will go away when the new NAND support is
implemented for these boards.
Diffstat (limited to 'include/configs/CPCI405.h')
-rw-r--r-- | include/configs/CPCI405.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index efc3adaece2..047e2f1eef9 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -79,6 +79,8 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> +#define CFG_NAND_LEGACY + #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |