diff options
| author | Haiying Wang <Haiying.Wang@freescale.com> | 2009-05-20 12:30:37 -0400 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2009-06-12 17:17:01 -0500 |
| commit | f82107f637f167a77803c0933f9b24741a91c711 (patch) | |
| tree | 1000b15d369f48a04ecb46b258b397d287eda1bf /include/configs/MPC8569MDS.h | |
| parent | 750098d33bc362ac4263863e92da158cf011063f (diff) | |
85xx: Add RMII support for MPC8569MDS
This patch supports UCC working at RMII mode on PIB board, fixup fdt blob to
support rmii in kernel. It also changes the name of enable_mpc8569mds_qe_mdio to
enalbe_mpc8569mds_qe_uec which is more accurate.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include/configs/MPC8569MDS.h')
| -rw-r--r-- | include/configs/MPC8569MDS.h | 38 |
1 files changed, 34 insertions, 4 deletions
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 259cd572c9a..c97ea2fdcc0 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -282,6 +282,8 @@ extern unsigned long get_clock_freq(void); /* * QE UEC ethernet configuration */ +#define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */ +#undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */ #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) #define CONFIG_UEC_ETH @@ -294,11 +296,18 @@ extern unsigned long get_clock_freq(void); #ifdef CONFIG_UEC_ETH1 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE +#if defined(CONFIG_SYS_UCC_RGMII_MODE) #define CONFIG_SYS_UEC1_TX_CLK QE_CLK12 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 7 #define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID -#endif +#elif defined(CONFIG_SYS_UCC_RMII_MODE) +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */ +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */ +#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII +#endif /* CONFIG_SYS_UCC_RGMII_MODE */ +#endif /* CONFIG_UEC_ETH1 */ #define CONFIG_UEC_ETH2 /* GETH2 */ #define CONFIG_HAS_ETH1 @@ -306,11 +315,18 @@ extern unsigned long get_clock_freq(void); #ifdef CONFIG_UEC_ETH2 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE +#if defined(CONFIG_SYS_UCC_RGMII_MODE) #define CONFIG_SYS_UEC2_TX_CLK QE_CLK17 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC2_PHY_ADDR 1 #define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID -#endif +#elif defined(CONFIG_SYS_UCC_RMII_MODE) +#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */ +#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */ +#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_100_RMII +#endif /* CONFIG_SYS_UCC_RGMII_MODE */ +#endif /* CONFIG_UEC_ETH2 */ #define CONFIG_UEC_ETH3 /* GETH3 */ #define CONFIG_HAS_ETH2 @@ -318,11 +334,18 @@ extern unsigned long get_clock_freq(void); #ifdef CONFIG_UEC_ETH3 #define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */ #define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE +#if defined(CONFIG_SYS_UCC_RGMII_MODE) #define CONFIG_SYS_UEC3_TX_CLK QE_CLK12 #define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC3_PHY_ADDR 2 #define CONFIG_SYS_UEC3_INTERFACE_MODE ENET_1000_RGMII_ID -#endif +#elif defined(CONFIG_SYS_UCC_RMII_MODE) +#define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */ +#define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */ +#define CONFIG_SYS_UEC3_INTERFACE_MODE ENET_100_RMII +#endif /* CONFIG_SYS_UCC_RGMII_MODE */ +#endif /* CONFIG_UEC_ETH3 */ #define CONFIG_UEC_ETH4 /* GETH4 */ #define CONFIG_HAS_ETH3 @@ -330,11 +353,18 @@ extern unsigned long get_clock_freq(void); #ifdef CONFIG_UEC_ETH4 #define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */ #define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE +#if defined(CONFIG_SYS_UCC_RGMII_MODE) #define CONFIG_SYS_UEC4_TX_CLK QE_CLK17 #define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC4_PHY_ADDR 3 #define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_1000_RGMII_ID -#endif +#elif defined(CONFIG_SYS_UCC_RMII_MODE) +#define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */ +#define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */ +#define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_100_RMII +#endif /* CONFIG_SYS_UCC_RGMII_MODE */ +#endif /* CONFIG_UEC_ETH4 */ #endif /* CONFIG_QE */ #if defined(CONFIG_PCI) |