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authorTsiChung Liew <tsicliew@gmail.com>2010-03-11 22:12:53 -0600
committerTsiChung Liew <tsicliew@gmail.com>2010-03-24 11:09:37 -0500
commitdd9f054ede433de73b137987fb3dc066e8d24ebb (patch)
treec4bafde866a253612976f0f3f8805093360c5c44 /include/configs/TASREG.h
parentf628e2f72daee810aa568619b6629da68ad042d6 (diff)
ColdFire: Cache update for all platforms
The CF will call cache functions in lib_m68/cache.c and the cache settings are defined in platform configuration file. Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
Diffstat (limited to 'include/configs/TASREG.h')
-rw-r--r--include/configs/TASREG.h11
1 files changed, 11 insertions, 0 deletions
diff --git a/include/configs/TASREG.h b/include/configs/TASREG.h
index 25f3a26f35f..b69f015c7cd 100644
--- a/include/configs/TASREG.h
+++ b/include/configs/TASREG.h
@@ -252,6 +252,17 @@
*/
#define CONFIG_SYS_CACHELINE_SIZE 16
+#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+ CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
+ CF_CACR_DBWE)
+
/*-----------------------------------------------------------------------
* Memory bank definitions
*/