rename CFG_ macros to CONFIG_SYS

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

1 files changed, 170 insertions, 170 deletions

diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 7b062f41ace..2961a1b2a0f 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -38,7 +38,7 @@
 #define CONFIG_TQM834X		1	/* TQM834X board specific */
 
 /* IMMR Base Addres Register, use Freescale default: 0xff400000 */
-#define CFG_IMMR		0xff400000
+#define CONFIG_SYS_IMMR		0xff400000
 
 /* System clock. Primary input clock when in PCI host mode */
 #define CONFIG_83XX_CLKIN	66666000	/* 66,666 MHz */
@@ -52,7 +52,7 @@
  * External Local Bus rate is
  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  */
-#define CFG_LCRR		(LCRR_DBYP | LCRR_CLKDIV_8)
+#define CONFIG_SYS_LCRR		(LCRR_DBYP | LCRR_CLKDIV_8)
 
 /* board pre init: do not call, nothing to do */
 #undef CONFIG_BOARD_EARLY_INIT_F
@@ -63,141 +63,141 @@
 /*
  * DDR Setup
  */
-#define CFG_DDR_BASE		0x00000000	/* DDR is system memory*/
-#define CFG_SDRAM_BASE		CFG_DDR_BASE
-#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
+#define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
 #define DDR_CASLAT_25				/* CASLAT set to 2.5 */
 #undef CONFIG_DDR_ECC				/* only for ECC DDR module */
 #undef CONFIG_SPD_EEPROM			/* do not use SPD EEPROM for DDR setup */
 
-#undef CFG_DRAM_TEST				/* memory test, takes time */
-#define CFG_MEMTEST_START	0x00000000	/* memtest region */
-#define CFG_MEMTEST_END		0x00100000
+#undef CONFIG_SYS_DRAM_TEST				/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00100000
 
 /*
  * FLASH on the Local Bus
  */
-#define CFG_FLASH_CFI				/* use the Common Flash Interface */
+#define CONFIG_SYS_FLASH_CFI				/* use the Common Flash Interface */
 #define CONFIG_FLASH_CFI_DRIVER			/* use the CFI driver */
-#undef CFG_FLASH_CHECKSUM
-#define CFG_FLASH_BASE		0x80000000	/* start of FLASH   */
-#define CFG_FLASH_SIZE		8		/* FLASH size in MB */
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_BASE		0x80000000	/* start of FLASH   */
+#define CONFIG_SYS_FLASH_SIZE		8		/* FLASH size in MB */
 
 /* buffered writes in the AMD chip set is not supported yet */
-#undef CFG_FLASH_USE_BUFFER_WRITE
+#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 
 /*
  * FLASH bank number detection
  */
 
 /*
- * When CFG_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash
+ * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash
  * banks has to be determined at runtime and stored in a gloabl variable
- * tqm834x_num_flash_banks. The value of CFG_MAX_FLASH_BANKS_DETECT is only
- * used instead of CFG_MAX_FLASH_BANKS to allocate the array flash_info, and
+ * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is only
+ * used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array flash_info, and
  * should be made sufficiently large to accomodate the number of banks that
  * might actually be detected.  Since most (all?) Flash related functions use
- * CFG_MAX_FLASH_BANKS as the number of actual banks on the board, it is
+ * CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on the board, it is
  * defined as tqm834x_num_flash_banks.
  */
-#define CFG_MAX_FLASH_BANKS_DETECT	2
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	2
 #ifndef __ASSEMBLY__
 extern int tqm834x_num_flash_banks;
 #endif
-#define CFG_MAX_FLASH_BANKS (tqm834x_num_flash_banks)
+#define CONFIG_SYS_MAX_FLASH_BANKS (tqm834x_num_flash_banks)
 
-#define CFG_MAX_FLASH_SECT		512	/* max sectors per device */
+#define CONFIG_SYS_MAX_FLASH_SECT		512	/* max sectors per device */
 
 /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
-#define CFG_BR0_PRELIM		((CFG_FLASH_BASE & BR_BA) | \
+#define CONFIG_SYS_BR0_PRELIM		((CONFIG_SYS_FLASH_BASE & BR_BA) | \
 					BR_MS_GPCM | BR_PS_32 | BR_V)
 
 /* FLASH timing (0x0000_0c54) */
-#define CFG_OR_TIMING_FLASH	(OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | \
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | \
 					OR_GPCM_SCY_5 | OR_GPCM_TRLX)
 
-#define CFG_PRELIM_OR_AM	0xc0000000	/* OR addr mask: 1 GiB */
+#define CONFIG_SYS_PRELIM_OR_AM	0xc0000000	/* OR addr mask: 1 GiB */
 
-#define CFG_OR0_PRELIM		(CFG_PRELIM_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM		(CONFIG_SYS_PRELIM_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 
-#define CFG_LBLAWAR0_PRELIM	0x8000001D	/* 1 GiB window size (2^(size + 1)) */
+#define CONFIG_SYS_LBLAWAR0_PRELIM	0x8000001D	/* 1 GiB window size (2^(size + 1)) */
 
-#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE	/* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE	/* Window base at flash base */
 
 /* disable remaining mappings */
-#define CFG_BR1_PRELIM		0x00000000
-#define CFG_OR1_PRELIM		0x00000000
-#define CFG_LBLAWBAR1_PRELIM	0x00000000
-#define CFG_LBLAWAR1_PRELIM	0x00000000
-
-#define CFG_BR2_PRELIM		0x00000000
-#define CFG_OR2_PRELIM		0x00000000
-#define CFG_LBLAWBAR2_PRELIM	0x00000000
-#define CFG_LBLAWAR2_PRELIM	0x00000000
-
-#define CFG_BR3_PRELIM		0x00000000
-#define CFG_OR3_PRELIM		0x00000000
-#define CFG_LBLAWBAR3_PRELIM	0x00000000
-#define CFG_LBLAWAR3_PRELIM	0x00000000
-
-#define CFG_BR4_PRELIM		0x00000000
-#define CFG_OR4_PRELIM		0x00000000
-#define CFG_LBLAWBAR4_PRELIM	0x00000000
-#define CFG_LBLAWAR4_PRELIM	0x00000000
-
-#define CFG_BR5_PRELIM		0x00000000
-#define CFG_OR5_PRELIM		0x00000000
-#define CFG_LBLAWBAR5_PRELIM	0x00000000
-#define CFG_LBLAWAR5_PRELIM	0x00000000
-
-#define CFG_BR6_PRELIM		0x00000000
-#define CFG_OR6_PRELIM		0x00000000
-#define CFG_LBLAWBAR6_PRELIM	0x00000000
-#define CFG_LBLAWAR6_PRELIM	0x00000000
-
-#define CFG_BR7_PRELIM		0x00000000
-#define CFG_OR7_PRELIM		0x00000000
-#define CFG_LBLAWBAR7_PRELIM	0x00000000
-#define CFG_LBLAWAR7_PRELIM	0x00000000
+#define CONFIG_SYS_BR1_PRELIM		0x00000000
+#define CONFIG_SYS_OR1_PRELIM		0x00000000
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	0x00000000
+#define CONFIG_SYS_LBLAWAR1_PRELIM	0x00000000
+
+#define CONFIG_SYS_BR2_PRELIM		0x00000000
+#define CONFIG_SYS_OR2_PRELIM		0x00000000
+#define CONFIG_SYS_LBLAWBAR2_PRELIM	0x00000000
+#define CONFIG_SYS_LBLAWAR2_PRELIM	0x00000000
+
+#define CONFIG_SYS_BR3_PRELIM		0x00000000
+#define CONFIG_SYS_OR3_PRELIM		0x00000000
+#define CONFIG_SYS_LBLAWBAR3_PRELIM	0x00000000
+#define CONFIG_SYS_LBLAWAR3_PRELIM	0x00000000
+
+#define CONFIG_SYS_BR4_PRELIM		0x00000000
+#define CONFIG_SYS_OR4_PRELIM		0x00000000
+#define CONFIG_SYS_LBLAWBAR4_PRELIM	0x00000000
+#define CONFIG_SYS_LBLAWAR4_PRELIM	0x00000000
+
+#define CONFIG_SYS_BR5_PRELIM		0x00000000
+#define CONFIG_SYS_OR5_PRELIM		0x00000000
+#define CONFIG_SYS_LBLAWBAR5_PRELIM	0x00000000
+#define CONFIG_SYS_LBLAWAR5_PRELIM	0x00000000
+
+#define CONFIG_SYS_BR6_PRELIM		0x00000000
+#define CONFIG_SYS_OR6_PRELIM		0x00000000
+#define CONFIG_SYS_LBLAWBAR6_PRELIM	0x00000000
+#define CONFIG_SYS_LBLAWAR6_PRELIM	0x00000000
+
+#define CONFIG_SYS_BR7_PRELIM		0x00000000
+#define CONFIG_SYS_OR7_PRELIM		0x00000000
+#define CONFIG_SYS_LBLAWBAR7_PRELIM	0x00000000
+#define CONFIG_SYS_LBLAWAR7_PRELIM	0x00000000
 
 /*
  * Monitor config
  */
-#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#define CFG_RAMBOOT
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
 #else
-#undef  CFG_RAMBOOT
+#undef  CONFIG_SYS_RAMBOOT
 #endif
 
 #define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK	1
-#define CFG_INIT_RAM_ADDR	0x20000000	/* Initial RAM address */
-#define CFG_INIT_RAM_END	0x1000		/* End of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END	0x1000		/* End of used area in RAM*/
 
-#define CFG_GBL_DATA_SIZE	0x100		/* num bytes initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	0x100		/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(256 * 1024) /* Reserve 256 kB for malloc */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024) /* Reserve 256 kB for malloc */
 
 /*
  * Serial Port
  */
 #define CONFIG_CONS_INDEX	1
 #undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE	1
-#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CFG_BAUDRATE_TABLE  \
+#define CONFIG_SYS_BAUDRATE_TABLE  \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-#define CFG_NS16550_COM1	(CFG_IMMR + 0x4500)
-#define CFG_NS16550_COM2	(CFG_IMMR + 0x4600)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
 
 /*
  * I2C
@@ -205,27 +205,27 @@ extern int tqm834x_num_flash_banks;
 #define CONFIG_HARD_I2C				/* I2C with hardware support	*/
 #undef CONFIG_SOFT_I2C				/* I2C bit-banged		*/
 #define CONFIG_FSL_I2C
-#define CFG_I2C_SPEED			400000	/* I2C speed: 400KHz		*/
-#define CFG_I2C_SLAVE			0x7F	/* slave address		*/
-#define CFG_I2C_OFFSET			0x3000
+#define CONFIG_SYS_I2C_SPEED			400000	/* I2C speed: 400KHz		*/
+#define CONFIG_SYS_I2C_SLAVE			0x7F	/* slave address		*/
+#define CONFIG_SYS_I2C_OFFSET			0x3000
 
 /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
-#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x			*/
-#define CFG_I2C_EEPROM_ADDR_LEN		2	/* 16 bit			*/
-#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* 32 bytes per write		*/
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	12	/* 10ms +/- 20%			*/
-#define CFG_I2C_MULTI_EEPROMS		1       /* more than one eeprom		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x			*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2	/* 16 bit			*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* 32 bytes per write		*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	12	/* 10ms +/- 20%			*/
+#define CONFIG_SYS_I2C_MULTI_EEPROMS		1       /* more than one eeprom		*/
 
 /* I2C RTC */
 #define CONFIG_RTC_DS1337			/* use ds1337 rtc via i2c	*/
-#define CFG_I2C_RTC_ADDR		0x68	/* at address 0x68		*/
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68	/* at address 0x68		*/
 
 /* I2C SYSMON (LM75) */
 #define CONFIG_DTT_LM75			1	/* ON Semi's LM75		*/
 #define CONFIG_DTT_SENSORS		{0}	/* Sensor addresses		*/
-#define CFG_DTT_MAX_TEMP		70
-#define CFG_DTT_LOW_TEMP		-30
-#define CFG_DTT_HYSTERESIS		3
+#define CONFIG_SYS_DTT_MAX_TEMP		70
+#define CONFIG_SYS_DTT_LOW_TEMP		-30
+#define CONFIG_SYS_DTT_HYSTERESIS		3
 
 /*
  * TSEC
@@ -233,10 +233,10 @@ extern int tqm834x_num_flash_banks;
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_MII
 
-#define CFG_TSEC1_OFFSET	0x24000
-#define CFG_TSEC1		(CFG_IMMR + CFG_TSEC1_OFFSET)
-#define CFG_TSEC2_OFFSET	0x25000
-#define CFG_TSEC2		(CFG_IMMR + CFG_TSEC2_OFFSET)
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
+#define CONFIG_SYS_TSEC1		(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET	0x25000
+#define CONFIG_SYS_TSEC2		(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
 
 #if defined(CONFIG_TSEC_ENET)
 
@@ -272,24 +272,24 @@ extern int tqm834x_num_flash_banks;
 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 
 /* PCI1 host bridge */
-#define CFG_PCI1_MEM_BASE       0xc0000000
-#define CFG_PCI1_MEM_PHYS       CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE       0x20000000      /* 512M */
-#define CFG_PCI1_IO_BASE        0xe2000000
-#define CFG_PCI1_IO_PHYS        CFG_PCI1_IO_BASE
-#define CFG_PCI1_IO_SIZE        0x1000000       /* 16M */
+#define CONFIG_SYS_PCI1_MEM_BASE       0xc0000000
+#define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE       0x20000000      /* 512M */
+#define CONFIG_SYS_PCI1_IO_BASE        0xe2000000
+#define CONFIG_SYS_PCI1_IO_PHYS        CONFIG_SYS_PCI1_IO_BASE
+#define CONFIG_SYS_PCI1_IO_SIZE        0x1000000       /* 16M */
 
 #undef CONFIG_EEPRO100
 #define CONFIG_EEPRO100
 #undef CONFIG_TULIP
 
 #if !defined(CONFIG_PCI_PNP)
-	#define PCI_ENET0_IOADDR	CFG_PCI1_IO_BASE
-	#define PCI_ENET0_MEMADDR	CFG_PCI1_MEM_BASE
+	#define PCI_ENET0_IOADDR	CONFIG_SYS_PCI1_IO_BASE
+	#define PCI_ENET0_MEMADDR	CONFIG_SYS_PCI1_MEM_BASE
 	#define PCI_IDSEL_NUMBER	0x1c    /* slot0 (IDSEL) = 28 */
 #endif
 
-#define CFG_PCI_SUBSYS_VENDORID		0x1957  /* Freescale */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID		0x1957  /* Freescale */
 
 #endif	/* CONFIG_PCI */
 
@@ -298,20 +298,20 @@ extern int tqm834x_num_flash_banks;
  */
 #define CONFIG_ENV_OVERWRITE
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	#define CONFIG_ENV_IS_IN_FLASH	1
-	#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
 	#define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
 	#define CONFIG_ENV_SIZE		0x2000
 #else
-	#define CFG_NO_FLASH		1	/* Flash is not usable now */
+	#define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
 	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
-	#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
 	#define CONFIG_ENV_SIZE		0x2000
 #endif
 
 #define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
-#define CFG_LOADS_BAUD_CHANGE		1	/* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE		1	/* allow baudrate change */
 
 /*
  * BOOTP options
@@ -340,7 +340,7 @@ extern int tqm834x_num_flash_banks;
     #define CONFIG_CMD_PCI
 #endif
 
-#if defined(CFG_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT)
     #undef CONFIG_CMD_ENV
     #undef CONFIG_CMD_LOADS
 #endif
@@ -348,26 +348,26 @@ extern int tqm834x_num_flash_banks;
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP				/* undef to save memory	*/
-#define CFG_LOAD_ADDR		0x2000000	/* default load address */
-#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP				/* undef to save memory	*/
+#define CONFIG_SYS_LOAD_ADDR		0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt */
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
-#ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #endif
 
 #if defined(CONFIG_CMD_KGDB)
-	#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+	#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
 #else
-	#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+	#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
 #endif
 
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS		16		/* max number of command args */
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
-#define CFG_HZ			1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1ms ticks */
 
 #undef CONFIG_WATCHDOG				/* watchdog disabled */
 
@@ -376,9 +376,9 @@ extern int tqm834x_num_flash_banks;
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
 
-#define CFG_HRCW_LOW (\
+#define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
 	HRCWL_CSB_TO_CLKIN_4X1 |\
@@ -386,7 +386,7 @@ extern int tqm834x_num_flash_banks;
 	HRCWL_CORE_TO_CSB_2X1)
 
 #if defined(PCI_64BIT)
-#define CFG_HRCW_HIGH (\
+#define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_HOST |\
 	HRCWH_64_BIT_PCI |\
 	HRCWH_PCI1_ARBITER_ENABLE |\
@@ -399,7 +399,7 @@ extern int tqm834x_num_flash_banks;
 	HRCWH_TSEC1M_IN_GMII |\
 	HRCWH_TSEC2M_IN_GMII )
 #else
-#define CFG_HRCW_HIGH (\
+#define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_PCI_HOST |\
 	HRCWH_32_BIT_PCI |\
 	HRCWH_PCI1_ARBITER_ENABLE |\
@@ -414,67 +414,67 @@ extern int tqm834x_num_flash_banks;
 #endif
 
 /* System IO Config */
-#define CFG_SICRH	SICRH_TSOBI1
-#define CFG_SICRL	SICRL_LDP_A
+#define CONFIG_SYS_SICRH	SICRH_TSOBI1
+#define CONFIG_SYS_SICRL	SICRL_LDP_A
 
 /* i-cache and d-cache disabled */
-#define CFG_HID0_INIT	0x000000000
-#define CFG_HID0_FINAL	CFG_HID0_INIT
-#define CFG_HID2	HID2_HBE
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	CONFIG_SYS_HID0_INIT
+#define CONFIG_SYS_HID2	HID2_HBE
 
 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
 
 /* DDR 0 - 512M */
-#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_IBAT1L	(CFG_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U	(CFG_SDRAM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* stack in DCACHE @ 512M (no backing mem) */
-#define CFG_IBAT2L	(CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT2U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 
 /* PCI */
 #ifdef CONFIG_PCI
-#define CFG_IBAT3L	(CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT3U	(CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_IBAT4L	(CFG_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT4U	(CFG_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_IBAT5L	(CFG_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT5U	(CFG_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP)
 #else
-#define CFG_IBAT3L	(0)
-#define CFG_IBAT3U	(0)
-#define CFG_IBAT4L	(0)
-#define CFG_IBAT4U	(0)
-#define CFG_IBAT5L	(0)
-#define CFG_IBAT5U	(0)
+#define CONFIG_SYS_IBAT3L	(0)
+#define CONFIG_SYS_IBAT3U	(0)
+#define CONFIG_SYS_IBAT4L	(0)
+#define CONFIG_SYS_IBAT4U	(0)
+#define CONFIG_SYS_IBAT5L	(0)
+#define CONFIG_SYS_IBAT5U	(0)
 #endif
 
 /* IMMRBAR */
-#define CFG_IBAT6L	(CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT6U	(CFG_IMMR | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_IMMR | BATU_BL_1M | BATU_VS | BATU_VP)
 
 /* FLASH */
-#define CFG_IBAT7L	(CFG_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT7U	(CFG_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CFG_DBAT0L	CFG_IBAT0L
-#define CFG_DBAT0U	CFG_IBAT0U
-#define CFG_DBAT1L	CFG_IBAT1L
-#define CFG_DBAT1U	CFG_IBAT1U
-#define CFG_DBAT2L	CFG_IBAT2L
-#define CFG_DBAT2U	CFG_IBAT2U
-#define CFG_DBAT3L	CFG_IBAT3L
-#define CFG_DBAT3U	CFG_IBAT3U
-#define CFG_DBAT4L	CFG_IBAT4L
-#define CFG_DBAT4U	CFG_IBAT4U
-#define CFG_DBAT5L	CFG_IBAT5L
-#define CFG_DBAT5U	CFG_IBAT5U
-#define CFG_DBAT6L	CFG_IBAT6L
-#define CFG_DBAT6U	CFG_IBAT6U
-#define CFG_DBAT7L	CFG_IBAT7L
-#define CFG_DBAT7U	CFG_IBAT7U
+#define CONFIG_SYS_IBAT7L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT7U	(CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
 
 /*
  * Internal Definitions