diff options
| author | Stefan Roese <sr@denx.de> | 2007-06-19 16:42:31 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-06-19 16:42:31 +0200 |
| commit | df8a24cdd30151505cf57bbee5289e91bf53bd1b (patch) | |
| tree | ff5305f90f000aead5a0cbf3a8e3501ea6102021 /include/configs/acadia.h | |
| parent | 86ba99e34194394052d24c04dc40d1263d29a26f (diff) | |
[ppc4xx] Fix problem with NAND booting on AMCC Acadia
The latest changes showed a problem with the location of the NAND-SPL
image in the OCM and the init-data area (incl. cache). This patch
fixes this problem.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include/configs/acadia.h')
| -rw-r--r-- | include/configs/acadia.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/configs/acadia.h b/include/configs/acadia.h index 0f447b004a0..517d130d5ca 100644 --- a/include/configs/acadia.h +++ b/include/configs/acadia.h @@ -75,7 +75,7 @@ #define CFG_TEMP_STACK_OCM 1 /* OCM as init ram */ /* On Chip Memory location */ -#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_ADDR 0xf8000000 #define CFG_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */ #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SRAM */ #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ @@ -159,7 +159,7 @@ */ #define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ #define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ -#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_DATA_ADDR + (12 << 10)) /* Copy SPL here*/ +#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_DATA_ADDR + (16 << 10)) /* Copy SPL here*/ #define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ #define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */ #define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST) |