diff options
| author | Mario Six <mario.six@gdsys.cc> | 2019-01-21 09:18:01 +0100 |
|---|---|---|
| committer | Mario Six <mario.six@gdsys.cc> | 2019-05-21 07:52:33 +0200 |
| commit | a8f975391f2452bc7a51eeafd030c85c32e1aca5 (patch) | |
| tree | 8b5bc02ac3891c277a8cae70dcf951f86c705f65 /include/configs/ids8313.h | |
| parent | 87ee51048eae94eb5c075b6c900d4da5e9531cf4 (diff) | |
mpc83xx: Simplify BR,OR lines
Re-format all BR,OR #define lines into single lines. This makes them
harder to read, but accessible to semi-automatic replacement.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Diffstat (limited to 'include/configs/ids8313.h')
| -rw-r--r-- | include/configs/ids8313.h | 47 |
1 files changed, 11 insertions, 36 deletions
diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 871b91f2183..61f64ebbbc0 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -142,17 +142,10 @@ #define CONFIG_SYS_FLASH_BASE 0xFF800000 #define CONFIG_SYS_FLASH_SIZE 8 -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\ - BR_PS_8 |\ - BR_MS_GPCM |\ - BR_V) - -#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB |\ - OR_GPCM_SCY_10 |\ - OR_GPCM_EHTR |\ - OR_GPCM_TRLX |\ - OR_GPCM_CSNT |\ - OR_GPCM_EAD) +/* FLASH */ +#define CONFIG_SYS_BR0_PRELIM (0xFF800000 | BR_PS_8 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB | OR_GPCM_SCY_10 | OR_GPCM_EHTR_SET | OR_GPCM_TRLX_SET | OR_GPCM_CSNT | OR_GPCM_EAD) + #define CONFIG_SYS_MAX_FLASH_BANKS 1 #define CONFIG_SYS_MAX_FLASH_SECT 128 @@ -170,21 +163,9 @@ #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) #define NAND_CACHE_PAGES 64 -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE) |\ - BR_DECC_CHK_GEN |\ - BR_PS_8 |\ - BR_MS_FCM |\ - BR_V) - -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB |\ - OR_FCM_PGS |\ - OR_FCM_CSCT |\ - OR_FCM_CST |\ - OR_FCM_CHT |\ - OR_FCM_SCY_4 |\ - OR_FCM_TRLX |\ - OR_FCM_EHTR |\ - OR_FCM_RST) +/* NAND */ +#define CONFIG_SYS_BR1_PRELIM (0xE1000000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_PGS | OR_FCM_CSCT | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_4 | OR_FCM_TRLX | OR_FCM_EHTR | OR_FCM_RST) /* * MRAM setup @@ -194,11 +175,8 @@ #define CONFIG_SYS_OR_TIMING_MRAM -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_MRAM_BASE |\ - BR_PS_8 |\ - BR_MS_GPCM |\ - BR_V) - +/* MRAM */ +#define CONFIG_SYS_BR2_PRELIM (0xE2000000 | BR_PS_8 | BR_MS_GPCM | BR_V) #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | OR_GPCM_SCY_7 | OR_GPCM_TRLX_SET) /* @@ -209,11 +187,8 @@ #define CONFIG_SYS_OR_TIMING_MRAM -#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CPLD_BASE |\ - BR_PS_8 |\ - BR_MS_GPCM |\ - BR_V) - +/* CPLD */ +#define CONFIG_SYS_BR3_PRELIM (0xE3000000 | BR_PS_8 | BR_MS_GPCM | BR_V) #define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_SCY_1 | OR_GPCM_TRLX_SET) /* |