diff options
| author | Ye Li <ye.li@nxp.com> | 2017-08-09 22:26:19 -0500 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2017-11-03 02:37:08 +0800 |
| commit | 588bab19a0d24a507153d67e0ebb9e062eb13e4f (patch) | |
| tree | 2eac369c6b5494e867066d909c5be4e1ba699ac7 /include/configs/imx8qm_arm2.h | |
| parent | 4b5cfdea95c6dfbb0aac6c9fbf60ebc08869d658 (diff) | |
MLK-16181 imx8qm/qxp: Add dcache flush to M4 boot commands
For booting M4 running in DDR, we use fatload to load the image to DDR first.
The fatload will do a copy for block size unaligned data in the tail. Since the DDR
area is cachable, so this cause a memory coherence issue. Need to use dcache flush
command before booting the M4 core.
This patch enables the CONFIG_CMD_CACHE and add the dcache flush to M4 boot commands
no matter the M4 runs in DDR or TCM.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'include/configs/imx8qm_arm2.h')
| -rw-r--r-- | include/configs/imx8qm_arm2.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/configs/imx8qm_arm2.h b/include/configs/imx8qm_arm2.h index 4f98189af0..7af14e19f4 100644 --- a/include/configs/imx8qm_arm2.h +++ b/include/configs/imx8qm_arm2.h @@ -99,8 +99,8 @@ "m4_1_image=m4_1.bin\0" \ "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \ "loadm4image_1=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \ - "m4boot_0=run loadm4image_0; bootaux ${loadaddr} 0\0" \ - "m4boot_1=run loadm4image_1; bootaux ${loadaddr} 1\0" \ + "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ + "m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" \ #ifdef CONFIG_NAND_BOOT #define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs) " |