diff options
| author | Tom Rini <trini@konsulko.com> | 2018-12-10 17:12:52 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-12-10 17:19:59 -0500 |
| commit | d94604d558cda9f89722c967d6f8d6269a2db21c (patch) | |
| tree | 2ccba6dac6920892a2075ab6d0f2b7e6d99c1cb5 /include/configs/ls1043ardb.h | |
| parent | 2918f58faa565bcf89ac8c9e827a2e290ea96f55 (diff) | |
| parent | 4909b89ec763f0c7030fa8474f9b6c5df866b01f (diff) | |
Merge tag 'fsl-qoriq-for-v2019.01-rc2' of git://git.denx.de/u-boot-fsl-qoriq
Add TFA boot flow for some Layerscape platforms
Add support for lx2160a SoC
[trini: Add a bunch of missing MAINTAINERS entries]
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'include/configs/ls1043ardb.h')
| -rw-r--r-- | include/configs/ls1043ardb.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 54e6eef417b..a0d39878b85 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -162,6 +162,25 @@ #define CONFIG_SYS_CPLD_FTIM3 0x0 /* IFC Timing Params */ +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 + +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#else #ifdef CONFIG_NAND_BOOT #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR @@ -199,6 +218,7 @@ #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 #endif +#endif #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT #define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR @@ -227,6 +247,14 @@ #define CONFIG_ENV_OVERWRITE #endif +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET 0x500000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x500000) +#define CONFIG_ENV_SECT_SIZE 0x20000 +#else #if defined(CONFIG_NAND_BOOT) #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_OFFSET (24 * CONFIG_SYS_NAND_BLOCK_SIZE) @@ -239,6 +267,7 @@ #define CONFIG_ENV_SECT_SIZE 0x20000 #define CONFIG_ENV_SIZE 0x20000 #endif +#endif /* FMan */ #ifndef SPL_NO_FMAN |