pm9263 converted to at91 soc access

Signed-off-by: Asen Dimov <dimov@ronetix.at>

1 files changed, 43 insertions, 44 deletions

diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
index f854f3874d8..9735e6a0797 100644
--- a/include/configs/pm9263.h
+++ b/include/configs/pm9263.h
@@ -28,8 +28,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_AT91_LEGACY
-
 /* ARM asynchronous clock */
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
@@ -49,41 +47,37 @@
 
 /* clocks */
 #define CONFIG_SYS_MOR_VAL						\
-		(AT91_PMC_MOSCEN |					\
+		(AT91_PMC_MOR_MOSCEN |					\
 		 (255 << 8))		/* Main Oscillator Start-up Time */
 #define CONFIG_SYS_PLLAR_VAL						\
-		(AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
-		 AT91_PMC_OUT |						\
-		 AT91_PMC_PLLCOUNT |	/* PLL Counter */		\
+		(AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
+		 AT91_PMC_PLLXR_OUT(3) |				\
+		 AT91_PMC_PLLXR_PLLCOUNT(0x3f) |	/* PLL Counter */\
 		 (2 << 28) |		/* PLL Clock Frequency Range */	\
 		 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
 
 #if (MAIN_PLL_DIV == 2)
 /* PCK/2 = MCK Master Clock from PLLA */
 #define	CONFIG_SYS_MCKR1_VAL		\
-		(AT91_PMC_CSS_SLOW |	\
-		 AT91_PMC_PRES_1 |	\
-		 AT91SAM9_PMC_MDIV_2 |	\
-		 AT91_PMC_PDIV_1)
+		(AT91_PMC_MCKR_CSS_SLOW |	\
+		 AT91_PMC_MCKR_PRES_1 |	\
+		 AT91_PMC_MCKR_MDIV_2)
 /* PCK/2 = MCK Master Clock from PLLA */
 #define	CONFIG_SYS_MCKR2_VAL		\
-		(AT91_PMC_CSS_PLLA |	\
-		 AT91_PMC_PRES_1 |	\
-		 AT91SAM9_PMC_MDIV_2 |	\
-		 AT91_PMC_PDIV_1)
+		(AT91_PMC_MCKR_CSS_PLLA |	\
+		 AT91_PMC_MCKR_PRES_1 |	\
+		 AT91_PMC_MCKR_MDIV_2)
 #else
 /* PCK/4 = MCK Master Clock from PLLA */
 #define	CONFIG_SYS_MCKR1_VAL			\
-		(AT91_PMC_CSS_SLOW |		\
-		 AT91_PMC_PRES_1 |		\
-		 AT91RM9200_PMC_MDIV_3 |	\
-		 AT91_PMC_PDIV_1)
+		(AT91_PMC_MCKR_CSS_SLOW |		\
+		 AT91_PMC_MCKR_PRES_1 |		\
+		 AT91_PMC_MCKR_MDIV_4)
 /* PCK/4 = MCK Master Clock from PLLA */
 #define	CONFIG_SYS_MCKR2_VAL			\
-		(AT91_PMC_CSS_PLLA |		\
-		 AT91_PMC_PRES_1 |		\
-		 AT91RM9200_PMC_MDIV_3 |	\
-		 AT91_PMC_PDIV_1)
+		(AT91_PMC_MCKR_CSS_PLLA |		\
+		 AT91_PMC_MCKR_PRES_1 |		\
+		 AT91_PMC_MCKR_MDIV_4)
 #endif
 /* define PDC[31:16] as DATA[31:16] */
 #define CONFIG_SYS_PIOD_PDR_VAL1	0xFFFF0000
@@ -91,8 +85,8 @@
 #define CONFIG_SYS_PIOD_PPUDR_VAL	0xFFFF0000
 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
 #define CONFIG_SYS_MATRIX_EBI0CSA_VAL					\
-	(AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V |	\
-	 AT91_MATRIX_EBI0_CS1A_SDRAMC)
+	(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V |	\
+	 AT91_MATRIX_CSA_EBI_CS1A)
 
 /* SDRAM */
 /* SDRAMC_MR Mode register */
@@ -135,32 +129,32 @@
 
 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
 #define CONFIG_SYS_SMC0_SETUP0_VAL					\
-		(AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) |	\
-		 AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
+		(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |	\
+		 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
 #define CONFIG_SYS_SMC0_PULSE0_VAL					\
-		(AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) |	\
-		 AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
+		(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |	\
+		 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
 #define CONFIG_SYS_SMC0_CYCLE0_VAL	\
-		(AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
+		(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
 #define CONFIG_SYS_SMC0_MODE0_VAL				\
-		(AT91_SMC_READMODE | AT91_SMC_WRITEMODE |	\
-		 AT91_SMC_DBW_16 |				\
-		 AT91_SMC_TDFMODE |				\
-		 AT91_SMC_TDF_(6))
+		(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |	\
+		 AT91_SMC_MODE_DBW_16 |				\
+		 AT91_SMC_MODE_TDF |				\
+		 AT91_SMC_MODE_TDF_CYCLE(6))
 
 /* user reset enable */
 #define CONFIG_SYS_RSTC_RMR_VAL			\
 		(AT91_RSTC_KEY |		\
-		AT91_RSTC_PROCRST |		\
-		AT91_RSTC_RSTTYP_WAKEUP |	\
-		AT91_RSTC_RSTTYP_WATCHDOG)
+		AT91_RSTC_CR_PROCRST |		\
+		AT91_RSTC_MR_ERSTL(1) |	\
+		AT91_RSTC_MR_ERSTL(2))
 
 /* Disable Watchdog */
 #define CONFIG_SYS_WDTC_WDMR_VAL				\
-		(AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |	\
-		 AT91_WDT_WDV |					\
-		 AT91_WDT_WDDIS |				\
-		 AT91_WDT_WDD)
+		(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT |	\
+		 AT91_WDT_MR_WDV(0xfff) |					\
+		 AT91_WDT_MR_WDDIS |				\
+		 AT91_WDT_MR_WDD(0xfff))
 
 #define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs */
 #define CONFIG_SETUP_MEMORY_TAGS 1
@@ -196,8 +190,8 @@
 
 /* LED */
 #define CONFIG_AT91_LED
-#define	CONFIG_RED_LED		AT91_PIN_PB7	/* this is the power led */
-#define	CONFIG_GREEN_LED	AT91_PIN_PB8	/* this is the user1 led */
+#define	CONFIG_RED_LED		AT91_PIO_PORTB, 7	/* this is the power led */
+#define	CONFIG_GREEN_LED	AT91_PIO_PORTB, 8	/* this is the user1 led */
 
 #define CONFIG_BOOTDELAY	3
 
@@ -258,8 +252,8 @@
 #define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
 /* our CLE is AD22 */
 #define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PD15
-#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PB30
+#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIO_PORTD, 15
+#define CONFIG_SYS_NAND_READY_PIN	AT91_PIO_PORTB, 30
 
 #endif
 
@@ -273,6 +267,11 @@
 /* PSRAM */
 #define	PHYS_PSRAM			0x70000000
 #define	PHYS_PSRAM_SIZE			0x00400000	/* 4MB */
+/* Slave EBI1, PSRAM connected */
+#define CONFIG_PSRAM_SCFG		(AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY	| \
+					 AT91_MATRIX_SCFG_FIXED_DEFMSTR(5)	| \
+					 AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED	| \
+					 AT91_MATRIX_SCFG_SLOT_CYCLE(255))
 
 /* Ethernet */
 #define CONFIG_MACB			1