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authorPeter Tyser <ptyser@xes-inc.com>2010-04-12 22:28:09 -0500
committerWolfgang Denk <wd@denx.de>2010-04-13 09:13:16 +0200
commit8d1f268204b07e172f3cb5cee0a3974d605b0b98 (patch)
treec3359e920cc886e7060fb099bf933496aca37153 /include/configs/quad100hd.h
parent819833af39a91fa1c1e8252862bbda6f5a602f7b (diff)
ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Diffstat (limited to 'include/configs/quad100hd.h')
-rw-r--r--include/configs/quad100hd.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/include/configs/quad100hd.h b/include/configs/quad100hd.h
index 403837e14b0..2472187520a 100644
--- a/include/configs/quad100hd.h
+++ b/include/configs/quad100hd.h
@@ -233,7 +233,7 @@
* Definitions for initial stack pointer and data area (in data cache)
*/
/* use on chip memory (OCM) for temperary stack until sdram is tested */
-/* see ./cpu/ppc4xx/start.S */
+/* see ./arch/ppc/cpu/ppc4xx/start.S */
#define CONFIG_SYS_TEMP_STACK_OCM 1
/* On Chip Memory location */
@@ -251,7 +251,7 @@
* Taken from PPCBoot board/icecube/icecube.h
*/
-/* see ./cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */
+/* see ./arch/ppc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */
#define CONFIG_SYS_EBC_PB0AP 0x04002480
/* AMD NOR flash - this corresponds to FLASH_BASE so may be correct */
#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000
@@ -269,7 +269,7 @@
*
* Taken in part from PPCBoot board/icecube/icecube.h
*/
-/* see ./cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */
+/* see ./arch/ppc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */
#define CONFIG_SYS_GPIO0_OSRH 0x55555550
#define CONFIG_SYS_GPIO0_OSRL 0x00000110
#define CONFIG_SYS_GPIO0_ISR1H 0x00000000