diff options
| author | Paul Gortmaker <paul.gortmaker@windriver.com> | 2011-12-30 23:53:06 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2012-01-11 13:58:07 -0600 |
| commit | af35be6ac962a737005737ab479da93cac2f596f (patch) | |
| tree | ea2b5c6badc2fd034f6855ae91df33da4f168440 /include/configs/sbc8548.h | |
| parent | 1667013ddfa95007c242d7772fb38e3e3bf72b48 (diff) | |
Revert "SBC8548: fix address mask to allow 64M flash"
This reverts commit ccf1ad535ae1c0dc2d466235c668adbdfe3a55b7.
The commit "SBC8548: fix address mask to allow 64M flash"
essentially made this change:
* OR6:
- * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0
+ * Addr Mask = 64M = OR6[0:16] = 1111 1000 0000 0000 0
But this makes no sense, as section 13.3.1.2.1 in the
MPC8548ERM v2 clearly indicates the masks:
1111_1111_1000_0000_0 8 Mbytes
1111_1100_0000_0000_0 64 Mbytes
1111_1000_0000_0000_0 128 Mbytes
So the original value was correct, and the commit was invalid,
causing a 128MB mapping for a 64MB flash device. The problem
rears its head when trying to configure u-boot to have access
to both flash, since the default memory map is:
FB80_0000 – FF7F_FFFF 32-bits 64MB FLASH SODIMM
FF80_0000 – FFFF_FFFF 8-bits 8MB FLASH
By extending the mapping of the 64MB flash to 128MB, it now
conflicts with the normal 8MB boot flash, causing issues.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include/configs/sbc8548.h')
| -rw-r--r-- | include/configs/sbc8548.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index ba7612c5a1c..7c26207ab91 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -173,7 +173,7 @@ * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0 * * OR6: - * Addr Mask = 64M = OR6[0:16] = 1111 1000 0000 0000 0 + * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0 * XAM = OR6[17:18] = 11 * CSNT = OR6[20] = 1 * ACS = half cycle delay = OR6[21:22] = 11 @@ -182,7 +182,7 @@ * EAD = use external address latch delay = OR6[31] = 1 * * 0 4 8 12 16 20 24 28 - * 1111 1000 0000 0000 0110 1110 0110 0101 = f8006e65 OR6 + * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR6 */ #define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */ @@ -193,7 +193,7 @@ #define CONFIG_SYS_BR6_PRELIM 0xfb801801 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 -#define CONFIG_SYS_OR6_PRELIM 0xf8006e65 +#define CONFIG_SYS_OR6_PRELIM 0xfc006e65 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ CONFIG_SYS_ALT_FLASH} |