riscv: dts: sync mpfs-icicle devicetree with linux

The "notable" disappearances are:
- the pac193x stanza - there's nothing in mainline linux w.r.t. bindings
  for this & what is going to appear in mainline linux is going to be
  incompatible with what is currently in U-Boot.
- operating points - these operating points should not be set at the
  soc.dtsi level as they may not be possible depending on the design
  programmed to the FPGA
- clock output names - there are defines for the clock indices, these
  should not be needed
- the dt maintainers in linux NAKed using defines for IRQ numbers
- the qspi nand, which is not part of the icicle's default configuration
  is removed.

Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Rick Chen <rick@andestech.com>

1 files changed, 0 insertions, 17 deletions

diff --git a/include/dt-bindings/interrupt-controller/riscv-hart.h b/include/dt-bindings/interrupt-controller/riscv-hart.h
deleted file mode 100644
index c4331b8521b..00000000000
--- a/include/dt-bindings/interrupt-controller/riscv-hart.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/* Copyright (c) 2020-2021 Microchip Technology Inc */
-
-#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H
-#define _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H
-
-#define HART_INT_U_SOFT   0
-#define HART_INT_S_SOFT   1
-#define HART_INT_M_SOFT   3
-#define HART_INT_U_TIMER  4
-#define HART_INT_S_TIMER  5
-#define HART_INT_M_TIMER  7
-#define HART_INT_U_EXT    8
-#define HART_INT_S_EXT    9
-#define HART_INT_M_EXT    11
-
-#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H */