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authorChe-Liang Chiou <clchiou@chromium.org>2011-08-11 17:58:58 +0800
committerSimon Glass <sjg@chromium.org>2011-08-29 10:59:37 -0700
commit046ef6142cfcb42150486f45fdd4fba95e0367fc (patch)
tree1620ff58efae592aea38ccdceac0e6bafb7a50f4 /include/fdt_decode.h
parent8d920268a376a12087d846ee58190a4d2b0f5794 (diff)
CHROMIUM: decode GPIO configs through <&gpio ...>
cros_gpio module used a ad-hoc format of GPIO config, and it should use <&gpio ...> instead. This patch changes the format of GPIO config. Note: In between calls to gpio_direction_input() (in fdt_setup_gpio()) and calls to gpio_get_value(), you have to insert a small delay if the input source is connected to the GPIO through a sufficiently large series resister (say, 200K ohm) so that the RC time constant for charging the gate capacitance on the input is non-trivial. As a matter of fact, I tested on Kaen and Aebl, and found only write protect GPIO needs this delay, and the delay time is less than 10 us. And we may safely hide this delay by decoupling the initialization and reading of GPIOs. BUG=none TEST=Run "vboot_test gpio" on Kaen and Aebl, and check GPIO readings TEST=Run "crossystem" on Kaen and Aebl after boot, and check GPIO readings Change-Id: Ib4d93c2ce156eb09ffc24a3882f83490d25c1e91 Reviewed-on: http://gerrit.chromium.org/gerrit/5726 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Tested-by: Che-Liang Chiou <clchiou@chromium.org>
Diffstat (limited to 'include/fdt_decode.h')
-rw-r--r--include/fdt_decode.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/fdt_decode.h b/include/fdt_decode.h
index 3a6a7087ba..4c4de444d4 100644
--- a/include/fdt_decode.h
+++ b/include/fdt_decode.h
@@ -94,6 +94,7 @@ enum {
FDT_GPIO_OUTPUT = 1 << 0, /* set as output (else input) */
FDT_GPIO_HIGH = 1 << 1, /* set output as high (else low) */
+ FDT_GPIO_ACTIVE_LOW = 1 << 2, /* input is active low (else high) */
};
/* This is the state of a GPIO pin. For now it only handles output pins */