diff options
| author | Rupjyoti Sarmah <rsarmah@appliedmicro.com> | 2010-03-24 16:52:02 +0530 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2010-03-24 14:27:01 +0100 |
| commit | c550afada5fcad426aa6a219a329feb9eedae8b2 (patch) | |
| tree | 99a4b5a26fa904d1852b9662f9643add3ffa806e /include/ppc440.h | |
| parent | 7027d5622d56ee2292713773044fb6352e431f31 (diff) | |
ppc4xx fix unstable 440EPx bootstrap options
440EPx fixed bootstrap options A, B, D, and E sets PLL FWDVA to a value = 1.
This results in the PLLOUTB being greater than the CPU clock frequency
resulting unstable 440EPx operation resulting in various software hang
conditions.
This patch reprograms the FWDVA satisfying the requirement of setting FWDVB
to a value greater than 1 while using one of the four deafult bootstrap options.
Signed-off-by: Rupjyoti Sarmah <rsarmah@amcc.com>
Acked-by : Victor Gallardo <vgallardo@appliedmicro.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include/ppc440.h')
| -rw-r--r-- | include/ppc440.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/ppc440.h b/include/ppc440.h index e60fa13905e..5f87d2c600e 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -68,6 +68,12 @@ #define CPR0_SPCID 0x0120 #define CPR0_ICFG 0x0140 +/* 440EPX boot strap options */ +#define BOOT_STRAP_OPTION_A 0x00000000 +#define BOOT_STRAP_OPTION_B 0x00000001 +#define BOOT_STRAP_OPTION_D 0x00000003 +#define BOOT_STRAP_OPTION_E 0x00000004 + /* 440gx sdr register definations */ #define SDR0_SDSTP0 0x0020 /* */ #define SDR0_SDSTP1 0x0021 /* */ |