Merge with /home/wd/git/u-boot/master

Code cleanup.

40 files changed, 1061 insertions, 790 deletions

diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 5d36b84b07c..83ae5e3e13c 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -1009,7 +1009,7 @@ typedef void		(*ExcpHndlr) (void) ;
  *    - GPIO
  *    - Data Flash DF_* pins defined.
  */
-#define GPIO0		__REG(0x40e10124) 
+#define GPIO0		__REG(0x40e10124)
 #define GPIO1		__REG(0x40e10128)
 #define GPIO2		__REG(0x40e1012c)
 #define GPIO3		__REG(0x40e10130)
@@ -2058,8 +2058,6 @@ typedef void		(*ExcpHndlr) (void) ;
 #define MDCNFG_DCSE1	0x2		/* SDRAM CS 1 Enable */
 #define MDCNFG_DCSE0	0x1		/* SDRAM CS 0 Enable */
 
-	
-
 
 /* Data Flash Controller Registers */
 
diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h
index 9841893899a..d03c05bf349 100644
--- a/include/configs/ASH405.h
+++ b/include/configs/ASH405.h
@@ -132,6 +132,9 @@
  * NAND-FLASH stuff
  *-----------------------------------------------------------------------
  */
+
+#define CFG_NAND_LEGACY
+
 #define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
 #define SECTORSIZE 512
 
diff --git a/include/configs/BMW.h b/include/configs/BMW.h
index 050054d274c..3bd43d83693 100644
--- a/include/configs/BMW.h
+++ b/include/configs/BMW.h
@@ -69,6 +69,10 @@
 				CFG_CMD_DOC	| \
 				CFG_CMD_ELF	| \
 				0 )
+
+/* CFG_CMD_DOC required legacy NAND support */
+#define CFG_NAND_LEGACY
+
 #if 0
 #define CONFIG_COMMANDS	        (CONFIG_CMD_DFL	| CFG_CMD_DHCP | \
 				 CFG_CMD_PCI | CFG_CMD_DOC | CFG_CMD_DATE)
diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h
index 6025886e3ea..1cca2859f4b 100644
--- a/include/configs/CMS700.h
+++ b/include/configs/CMS700.h
@@ -81,6 +81,8 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
+#define CFG_NAND_LEGACY
+
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h
index efc3adaece2..047e2f1eef9 100644
--- a/include/configs/CPCI405.h
+++ b/include/configs/CPCI405.h
@@ -79,6 +79,8 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
+#define CFG_NAND_LEGACY
+
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h
index 1347f2afcae..d756f447f7f 100644
--- a/include/configs/CPCI4052.h
+++ b/include/configs/CPCI4052.h
@@ -100,6 +100,8 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
+#define CFG_NAND_LEGACY
+
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h
index 9d52815092f..852d94a410a 100644
--- a/include/configs/CPCI405AB.h
+++ b/include/configs/CPCI405AB.h
@@ -87,6 +87,9 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
+#define CFG_NAND_LEGACY
+
+
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h
index 946a0fd1945..2260327c3f8 100644
--- a/include/configs/CPCI405DT.h
+++ b/include/configs/CPCI405DT.h
@@ -98,6 +98,8 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
+#define CFG_NAND_LEGACY
+
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h
index 1632f374c3c..244e45a7505 100644
--- a/include/configs/CPCI750.h
+++ b/include/configs/CPCI750.h
@@ -12,7 +12,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -57,7 +57,7 @@
 
 #define CONFIG_CPCI750		1	/* this is an CPCI750 board	*/
 
-#define CONFIG_BAUDRATE		9600 	/* console baudrate = 9600	*/
+#define CONFIG_BAUDRATE		9600	/* console baudrate = 9600	*/
 
 #undef	CONFIG_ECC			/* enable ECC support */
 
@@ -84,19 +84,19 @@
  * for your console driver.
  *
  * what to do:
- * to use the DUART, undef CONFIG_MPSC.  If you have hacked a serial
+ * to use the DUART, undef CONFIG_MPSC.	 If you have hacked a serial
  * cable onto the second DUART channel, change the CFG_DUART port from 1
  * to 0 below.
  *
  * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
  * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
  */
-#define	CONFIG_MPSC
+#define CONFIG_MPSC
 #define CONFIG_MPSC_PORT	0
 
 /* to change the default ethernet port, use this define (options: 0, 1, 2) */
 #define CONFIG_NET_MULTI
-#define MV_ETH_DEVS             1
+#define MV_ETH_DEVS		1
 #define CONFIG_ETHER_PORT	0
 
 #undef CONFIG_ETHER_PORT_MII	/* use RMII */
@@ -118,38 +118,38 @@
 
 #define CONFIG_SERIAL		"AA000001"
 #define CONFIG_SERVERIP		"10.0.0.79"
-#define CONFIG_ROOTPATH	        "/export/nfs_cpci750/%s"
+#define CONFIG_ROOTPATH		"/export/nfs_cpci750/%s"
 
 #define CONFIG_TESTDRAMDATA	y
-#define CONFIG_TESTDRAMADDRESS  n
+#define CONFIG_TESTDRAMADDRESS	n
 #define CONFIG_TESETDRAMWALK	n
 
 /* ----------------------------------------------------------------------------- */
 
 
-#define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
-#define	CFG_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
+#define CONFIG_LOADS_ECHO	0	/* echo off for serial download */
+#define CFG_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-#undef	CONFIG_ALTIVEC                  /* undef to disable             */
+#undef	CONFIG_ALTIVEC			/* undef to disable		*/
 
 #define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
 				 CONFIG_BOOTP_BOOTFILESIZE)
 
 
-#define CONFIG_COMMANDS	(CONFIG_CMD_DFL    \
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL	   \
 			 | CFG_CMD_ASKENV  \
-			 | CFG_CMD_I2C     \
+			 | CFG_CMD_I2C	   \
 			 | CFG_CMD_CACHE   \
 			 | CFG_CMD_EEPROM  \
-			 | CFG_CMD_PCI     \
+			 | CFG_CMD_PCI	   \
 			 | CFG_CMD_ELF	   \
 			 | CFG_CMD_DATE	   \
-			 | CFG_CMD_NET     \
-			 | CFG_CMD_PING    \
-			 | CFG_CMD_IDE     \
-			 | CFG_CMD_FAT     \
-			 | CFG_CMD_EXT2    \
+			 | CFG_CMD_NET	   \
+			 | CFG_CMD_PING	   \
+			 | CFG_CMD_IDE	   \
+			 | CFG_CMD_FAT	   \
+			 | CFG_CMD_EXT2	   \
 					)
 
 #define CONFIG_DOS_PARTITION
@@ -159,7 +159,7 @@
 
 #define CONFIG_USE_CPCIDVI
 
-#ifdef  CONFIG_USE_CPCIDVI
+#ifdef	CONFIG_USE_CPCIDVI
 #define CONFIG_VIDEO
 #define CONFIG_VIDEO_CT69000
 #define CONFIG_CFB_CONSOLE
@@ -174,23 +174,23 @@
  */
 #define CFG_I2C_EEPROM_ADDR_LEN 2
 #define CFG_I2C_MULTI_EEPROMS
-#define CFG_I2C_SPEED   80000		/* I2C speed default */
+#define CFG_I2C_SPEED	80000		/* I2C speed default */
 
 #define CFG_GT_DUAL_CPU			/* also for JTAG even with one cpu */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 
 /*#define CFG_MEMTEST_START	0x00400000*/	/* memtest works on	*/
 /*#define CFG_MEMTEST_END		0x00C00000*/	/* 4 ... 12 MB in DRAM	*/
-/*#define CFG_MEMTEST_END		0x07c00000*/	/* 4 ... 124 MB in DRAM	*/
+/*#define CFG_MEMTEST_END		0x07c00000*/	/* 4 ... 124 MB in DRAM */
 
 /*
 #define CFG_DRAM_TEST
@@ -198,21 +198,21 @@
  *   CFG_DRAM_TEST - enables the following tests.
  *
  *   CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines
- *                        Environment variable 'test_dram_data' must be
- *                        set to 'y'.
+ *			  Environment variable 'test_dram_data' must be
+ *			  set to 'y'.
  *   CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
- *                        addressable. Environment variable
- *                        'test_dram_address' must be set to 'y'.
+ *			  addressable. Environment variable
+ *			  'test_dram_address' must be set to 'y'.
  *   CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
- *                        This test takes about 6 minutes to test 64 MB.
- *                        Environment variable 'test_dram_walk' must be
- *                        set to 'y'.
+ *			  This test takes about 6 minutes to test 64 MB.
+ *			  Environment variable 'test_dram_walk' must be
+ *			  set to 'y'.
  */
 #define CFG_DRAM_TEST
 #if defined(CFG_DRAM_TEST)
 #define CFG_MEMTEST_START		0x00400000	/* memtest works on	*/
 /*#define CFG_MEMTEST_END		0x00C00000*/	/* 4 ... 12 MB in DRAM	*/
-#define CFG_MEMTEST_END		0x07c00000	/* 4 ... 124 MB in DRAM	*/
+#define CFG_MEMTEST_END		0x07c00000	/* 4 ... 124 MB in DRAM */
 #define CFG_DRAM_TEST_DATA
 #define CFG_DRAM_TEST_ADDRESS
 #define CFG_DRAM_TEST_WALK
@@ -221,10 +221,10 @@
 #define CONFIG_DISPLAY_MEMMAP		/* at the end of the bootprocess show the memory map */
 #undef CFG_DISPLAY_DIMM_SPD_CONTENT	/* show SPD content during boot */
 
-#define	CFG_LOAD_ADDR		0x00300000	/* default load address	*/
+#define CFG_LOAD_ADDR		0x00300000	/* default load address */
 
-#define	CFG_HZ			1000		/* decr freq: 1ms ticks	*/
-#define CFG_BUS_HZ		133000000	/* 133 MHz (CPU = 5*Bus = 666MHz)	 	*/
+#define CFG_HZ			1000		/* decr freq: 1ms ticks */
+#define CFG_BUS_HZ		133000000	/* 133 MHz (CPU = 5*Bus = 666MHz)		*/
 #define CFG_BUS_CLK		CFG_BUS_HZ
 
 #define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
@@ -251,7 +251,7 @@
  * To an unused memory region. The stack will remain in cache until RAM
  * is initialized
 */
-#undef    CFG_INIT_RAM_LOCK
+#undef	  CFG_INIT_RAM_LOCK
 /* #define CFG_INIT_RAM_ADDR	0x40000000*/ /* unused memory region */
 /* #define CFG_INIT_RAM_ADDR	0xfba00000*/ /* unused memory region */
 #define CFG_INIT_RAM_ADDR	0xf1080000 /* unused memory region */
@@ -261,7 +261,7 @@
 
 #define RELOCATE_INTERNAL_RAM_ADDR
 #ifdef RELOCATE_INTERNAL_RAM_ADDR
-/*#define CFG_INTERNAL_RAM_ADDR	0xfba00000*/
+/*#define CFG_INTERNAL_RAM_ADDR 0xfba00000*/
 #define CFG_INTERNAL_RAM_ADDR	0xf1080000
 #endif
 
@@ -270,16 +270,16 @@
  * (Set up by the startup code)
  * Please note that CFG_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_SDRAM_BASE		0x00000000
 /* Dummies for BAT 4-7 */
-#define	CFG_SDRAM1_BASE		0x10000000	/* each 256 MByte */
-#define	CFG_SDRAM2_BASE		0x20000000
-#define	CFG_SDRAM3_BASE		0x30000000
-#define	CFG_SDRAM4_BASE		0x40000000
+#define CFG_SDRAM1_BASE		0x10000000	/* each 256 MByte */
+#define CFG_SDRAM2_BASE		0x20000000
+#define CFG_SDRAM3_BASE		0x30000000
+#define CFG_SDRAM4_BASE		0x40000000
 #define CFG_RESET_ADDRESS	0xfff00100
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
 #define CFG_MONITOR_BASE	0xfff00000
-#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 256 kB for malloc */
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 256 kB for malloc */
 
 /*-----------------------------------------------------------------------
  * FLASH related
@@ -289,15 +289,15 @@
 #define CFG_FLASH_CFI		1	   /* Flash is CFI conformant		*/
 #define CFG_FLASH_PROTECTION	1	   /* use hardware protection		*/
 #define CFG_FLASH_USE_BUFFER_WRITE 1	   /* use buffered writes (20x faster)	*/
-#define CFG_FLASH_BASE		0xfc000000 /* start of flash banks              */
+#define CFG_FLASH_BASE		0xfc000000 /* start of flash banks		*/
 #define CFG_MAX_FLASH_BANKS	4	   /* max number of memory banks	*/
-#define CFG_FLASH_INCREMENT     0x01000000 /* size of  flash bank               */
-#define CFG_MAX_FLASH_SECT	128	   /* max number of sectors on one chip	*/
-#define CFG_FLASH_BANKS_LIST  { CFG_FLASH_BASE,                            \
-                                CFG_FLASH_BASE + 1*CFG_FLASH_INCREMENT,    \
-                                CFG_FLASH_BASE + 2*CFG_FLASH_INCREMENT,    \
-                                CFG_FLASH_BASE + 3*CFG_FLASH_INCREMENT }
-#define CFG_FLASH_EMPTY_INFO    1          /* show if bank is empty             */
+#define CFG_FLASH_INCREMENT	0x01000000 /* size of  flash bank		*/
+#define CFG_MAX_FLASH_SECT	128	   /* max number of sectors on one chip */
+#define CFG_FLASH_BANKS_LIST  { CFG_FLASH_BASE,				   \
+				CFG_FLASH_BASE + 1*CFG_FLASH_INCREMENT,	   \
+				CFG_FLASH_BASE + 2*CFG_FLASH_INCREMENT,	   \
+				CFG_FLASH_BASE + 3*CFG_FLASH_INCREMENT }
+#define CFG_FLASH_EMPTY_INFO	1	   /* show if bank is empty		*/
 
 /* areas to map different things with the GT in physical space */
 #define CFG_DRAM_BANKS		4
@@ -308,20 +308,20 @@
 /* Peripheral Device section */
 
 /*******************************************************/
-/* We have on the cpci750 Board :                      */
-/* GT-Chipset Register Area                            */
-/* GT-Chipset internal SRAM 256k                       */
-/* SRAM on external device module                      */
-/* Real time clock on external device module           */
-/* dobble UART on external device module               */
-/* Data flash on external device module                */
-/* Boot flash on external device module                */
+/* We have on the cpci750 Board :		       */
+/* GT-Chipset Register Area			       */
+/* GT-Chipset internal SRAM 256k		       */
+/* SRAM on external device module		       */
+/* Real time clock on external device module	       */
+/* dobble UART on external device module	       */
+/* Data flash on external device module		       */
+/* Boot flash on external device module		       */
 /*******************************************************/
 #define CFG_DFL_GT_REGS		0x14000000				/* boot time GT_REGS */
-#define  CFG_CPCI750_RESET_ADDR	0x14000000				/* After power on Reset the CPCI750 is here */
+#define	 CFG_CPCI750_RESET_ADDR 0x14000000				/* After power on Reset the CPCI750 is here */
 
-#undef 	MARVEL_STANDARD_CFG
-#ifndef 	MARVEL_STANDARD_CFG
+#undef	MARVEL_STANDARD_CFG
+#ifndef		MARVEL_STANDARD_CFG
 /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
 #define CFG_GT_REGS		0xf1000000				/* GT Registers will be mapped here */
 /*#define CFG_DEV_BASE		0xfc000000*/				/* GT Devices CS start here */
@@ -333,11 +333,11 @@
 #define CFG_DEV2_SPACE		0xfe000000				/* DEV_CS2 flash 3     */
 #define CFG_DEV3_SPACE		0xf0000000				/* DEV_CS3 nvram/can   */
 
-#define CFG_BOOT_SIZE		_16M 					/* cpci750 flash 0     */
-#define CFG_DEV0_SIZE		_16M 					/* cpci750 flash 1     */
-#define CFG_DEV1_SIZE		_16M 					/* cpci750 flash 2     */
-#define CFG_DEV2_SIZE		_16M 					/* cpci750 flash 3     */
-#define CFG_DEV3_SIZE		_16M 					/* cpci750 nvram/can   */
+#define CFG_BOOT_SIZE		_16M					/* cpci750 flash 0     */
+#define CFG_DEV0_SIZE		_16M					/* cpci750 flash 1     */
+#define CFG_DEV1_SIZE		_16M					/* cpci750 flash 2     */
+#define CFG_DEV2_SIZE		_16M					/* cpci750 flash 3     */
+#define CFG_DEV3_SIZE		_16M					/* cpci750 nvram/can   */
 
 /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
 #endif
@@ -346,22 +346,22 @@
 #define CFG_DEV0_PAR		0x8FDFFFFF				/* 16 bit flash */
 #define CFG_DEV1_PAR		0x8FDFFFFF				/* 16 bit flash */
 #define CFG_DEV2_PAR		0x8FDFFFFF				/* 16 bit flash */
-#define CFG_DEV3_PAR		0x8FCFFFFF				/* nvram/can    */
+#define CFG_DEV3_PAR		0x8FCFFFFF				/* nvram/can	*/
 #define CFG_BOOT_PAR		0x8FDFFFFF				/* 16 bit flash */
 
-	/*   c    4    a      8     2     4    1      c		*/
-	/* 33 22|2222|22 22|111 1|11 11|1 1  |    |		*/
+	/*   c	  4    a      8	    2	  4    1      c		*/
+	/* 33 22|2222|22 22|111 1|11 11|1 1  |	  |		*/
 	/* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210	*/
 	/* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100	*/
 	/*  3| 0|.... ..| 2| 4 |  0 |  4 |  8  |  3  | 4	*/
 
 
 /* MPP Control MV64360 Appendix P P. 632*/
-#define CFG_MPP_CONTROL_0	0x00002222	/*                                   */
-#define CFG_MPP_CONTROL_1	0x11110000	/*                                   */
-#define CFG_MPP_CONTROL_2	0x11111111	/*                                   */
-#define CFG_MPP_CONTROL_3	0x00001111     	/*                                   */
-/* #define CFG_SERIAL_PORT_MUX	0x00000102*/	/*                                   */
+#define CFG_MPP_CONTROL_0	0x00002222	/*				     */
+#define CFG_MPP_CONTROL_1	0x11110000	/*				     */
+#define CFG_MPP_CONTROL_2	0x11111111	/*				     */
+#define CFG_MPP_CONTROL_3	0x00001111	/*				     */
+/* #define CFG_SERIAL_PORT_MUX	0x00000102*/	/*				     */
 
 
 #define CFG_GPP_LEVEL_CONTROL	0xffffffff	/* 1111 1111 1111 1111 1111 1111 1111 1111*/
@@ -378,12 +378,12 @@
 				   ECC disable
 				   non registered DRAM */
 				/* 31:26   25:22  21:20 19 18 17 16 */
-				/* 100001 0000   010   0   0   0  0 */
+				/* 100001 0000	 010   0   0   0  0 */
 				/* refresh_count=0x400
 				   phisical interleaving disable
 				   virtual interleaving enable */
 				/* 15 14 13:0 */
-				/* 0  1  0x400 */
+				/* 0  1	 0x400 */
 # define CFG_SDRAM_CONFIG	0x58200400	/* 0x1400  copied from Dink32 bzw. VxWorks*/
 
 
@@ -392,14 +392,14 @@
  *-----------------------------------------------------------------------
  */
 
-#define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
 
-#define CONFIG_PCI                      /* include pci support          */
-#define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
-#define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
-#define CONFIG_PCI_SCAN_SHOW            /* show devices on bus          */
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+#define CONFIG_PCI_SCAN_SHOW		/* show devices on bus		*/
 
 /* PCI MEMORY MAP section */
 #define CFG_PCI0_MEM_BASE	0x80000000
@@ -433,21 +433,21 @@
  * IDE/ATA stuff
  *-----------------------------------------------------------------------
  */
-#undef  CONFIG_IDE_8xx_DIRECT           /* no pcmcia interface required */
-#undef  CONFIG_IDE_LED                  /* no led for ide supported     */
-#define CONFIG_IDE_RESET                /* no reset for ide supported   */
-#define CONFIG_IDE_PREINIT              /* check for units              */
+#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+#define CONFIG_IDE_RESET		/* no reset for ide supported	*/
+#define CONFIG_IDE_PREINIT		/* check for units		*/
 
-#define CFG_IDE_MAXBUS          2               /* max. 1 IDE busses    */
-#define CFG_IDE_MAXDEVICE       (CFG_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */
+#define CFG_IDE_MAXBUS		2		/* max. 1 IDE busses	*/
+#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */
 
-#define CFG_ATA_BASE_ADDR       0
-#define CFG_ATA_IDE0_OFFSET     0
-#define CFG_ATA_IDE1_OFFSET     0
+#define CFG_ATA_BASE_ADDR	0
+#define CFG_ATA_IDE0_OFFSET	0
+#define CFG_ATA_IDE1_OFFSET	0
 
-#define CFG_ATA_DATA_OFFSET     0x0000  /* Offset for data I/O                  */
-#define CFG_ATA_REG_OFFSET      0x0000  /* Offset for normal register accesses  */
-#define CFG_ATA_ALT_OFFSET      0x0000  /* Offset for alternate registers       */
+#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
 
 
 /*----------------------------------------------------------------------
@@ -551,7 +551,7 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8<<20)	/* Initial Memory map for Linux */
+#define CFG_BOOTMAPSZ		(8<<20) /* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
@@ -563,23 +563,23 @@
 #define CFG_FLASH_LOCK_TOUT	500	/* Timeout for Flash Lock (in ms) */
 
 #if 0
-#define	CFG_ENV_IS_IN_FLASH	0
-#define	CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
+#define CFG_ENV_IS_IN_FLASH	0
+#define CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
 #define CFG_ENV_SECT_SIZE	0x10000
 #define CFG_ENV_ADDR		0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
-/* #define CFG_ENV_ADDR    (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */
+/* #define CFG_ENV_ADDR	   (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */
 #endif
 
 #define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
 #define CFG_EEPROM_PAGE_WRITE_BITS 5
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
-#define CFG_I2C_EEPROM_ADDR     0x050
+#define CFG_I2C_EEPROM_ADDR	0x050
 #define CFG_ENV_OFFSET		0x200	/* environment starts at the beginning of the EEPROM */
 #define CFG_ENV_SIZE		0x600	/* 2048 bytes may be used for env vars*/
 
 #define CFG_NVRAM_BASE_ADDR	0xf0000000		/* NVRAM base address	*/
 #define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
-#define CFG_VXWORKS_MAC_PTR     (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-0x40)
+#define CFG_VXWORKS_MAC_PTR	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-0x40)
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
@@ -601,7 +601,7 @@
 #if defined (CONFIG_750CX) || defined (CONFIG_750FX)
 #define L2_INIT 0
 #else
-#define L2_INIT  	(L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
+#define L2_INIT		(L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
 			L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
 #endif
 
@@ -612,9 +612,9 @@
  *
  * Boot Flags
  */
-#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM	0x02		/* Software reboot		    */
 
-#define CFG_BOARD_ASM_INIT      1
+#define CFG_BOARD_ASM_INIT	1
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h
index 16a9ea5dd71..1e9a99eed33 100644
--- a/include/configs/CPU86.h
+++ b/include/configs/CPU86.h
@@ -178,6 +178,8 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
+#define CFG_NAND_LEGACY
+
 /*
  * Miscellaneous configurable options
  */
diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h
index a23d7e50b7b..9a98e5c191e 100644
--- a/include/configs/CPU87.h
+++ b/include/configs/CPU87.h
@@ -189,6 +189,8 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
+#define CFG_NAND_LEGACY
+
 /*
  * Miscellaneous configurable options
  */
diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h
index de8f7ae7112..6613f90a770 100644
--- a/include/configs/GEN860T.h
+++ b/include/configs/GEN860T.h
@@ -284,6 +284,8 @@
  */
 #include <cmd_confdefs.h>
 
+#define CFG_NAND_LEGACY
+
 /*
  * Verbose help from command monitor.
  */
diff --git a/include/configs/HH405.h b/include/configs/HH405.h
index 4f62b8ae8ac..dc40ebc861d 100644
--- a/include/configs/HH405.h
+++ b/include/configs/HH405.h
@@ -130,6 +130,8 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
+#define CFG_NAND_LEGACY
+
 #undef  CONFIG_BZIP2	 /* include support for bzip2 compressed images */
 #undef  CONFIG_WATCHDOG			/* watchdog disabled		*/
 
diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h
index eb627e881dd..f84e356216b 100644
--- a/include/configs/HUB405.h
+++ b/include/configs/HUB405.h
@@ -135,6 +135,8 @@
  * NAND-FLASH stuff
  *-----------------------------------------------------------------------
  */
+#define CFG_NAND_LEGACY
+
 #define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
 #define SECTORSIZE 512
 
diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h
index db2147b481a..1f01e7be0b0 100644
--- a/include/configs/MIP405.h
+++ b/include/configs/MIP405.h
@@ -87,6 +87,8 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS  (if any) */
 #include <cmd_confdefs.h>
 
+#define CFG_NAND_LEGACY
+
 #define	 CFG_HUSH_PARSER
 #define	 CFG_PROMPT_HUSH_PS2 "> "
 /**************************************************************
diff --git a/include/configs/NETPHONE.h b/include/configs/NETPHONE.h
index bf4c899592f..444f721cc85 100644
--- a/include/configs/NETPHONE.h
+++ b/include/configs/NETPHONE.h
@@ -491,6 +491,7 @@
 /****************************************************************/
 
 /* NAND */
+#define CFG_NAND_LEGACY
 #define CFG_NAND_BASE		NAND_BASE
 #define CONFIG_MTD_NAND_ECC_JFFS2
 #define CONFIG_MTD_NAND_VERIFY_WRITE
diff --git a/include/configs/NETTA2.h b/include/configs/NETTA2.h
index 529cb4cbae2..e20e72495cc 100644
--- a/include/configs/NETTA2.h
+++ b/include/configs/NETTA2.h
@@ -491,6 +491,7 @@
 /****************************************************************/
 
 /* NAND */
+#define CFG_NAND_LEGACY
 #define CFG_NAND_BASE		NAND_BASE
 #define CONFIG_MTD_NAND_ECC_JFFS2
 #define CONFIG_MTD_NAND_VERIFY_WRITE
diff --git a/include/configs/NETVIA.h b/include/configs/NETVIA.h
index dc6b15fcdc4..e30be0987aa 100644
--- a/include/configs/NETVIA.h
+++ b/include/configs/NETVIA.h
@@ -387,6 +387,8 @@
 
 /*****************************************************************************/
 
+#define CFG_NAND_LEGACY
+
 #if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
 
 /* NAND */
diff --git a/include/configs/PCIPPC2.h b/include/configs/PCIPPC2.h
index d03706e1936..3a97fbcbde8 100644
--- a/include/configs/PCIPPC2.h
+++ b/include/configs/PCIPPC2.h
@@ -77,6 +77,7 @@
  */
 #include <cmd_confdefs.h>
 
+#define CFG_NAND_LEGACY
 
 /*
  * Miscellaneous configurable options
diff --git a/include/configs/PCIPPC6.h b/include/configs/PCIPPC6.h
index 92b2f7cf839..130beb78e63 100644
--- a/include/configs/PCIPPC6.h
+++ b/include/configs/PCIPPC6.h
@@ -79,6 +79,7 @@
  */
 #include <cmd_confdefs.h>
 
+#define CFG_NAND_LEGACY
 
 /*
  * Miscellaneous configurable options
diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h
index 9668fb0ce2f..091b768a992 100644
--- a/include/configs/PIP405.h
+++ b/include/configs/PIP405.h
@@ -69,6 +69,8 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS  (if any) */
 #include <cmd_confdefs.h>
 
+#define CFG_NAND_LEGACY
+
 #define	 CFG_HUSH_PARSER
 #define	 CFG_PROMPT_HUSH_PS2 "> "
 /**************************************************************
diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
index 54ecfa4c5e3..dd5d8316804 100644
--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -160,6 +160,8 @@
  * NAND-FLASH stuff
  *-----------------------------------------------------------------------
  */
+#define CFG_NAND_LEGACY
+
 #define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
 #define SECTORSIZE 512
 
diff --git a/include/configs/PM520.h b/include/configs/PM520.h
index e73ad5100c2..9c241e67e73 100644
--- a/include/configs/PM520.h
+++ b/include/configs/PM520.h
@@ -101,6 +101,8 @@
 #define ADD_DOC_CMD             0
 #else
 #define ADD_DOC_CMD             CFG_CMD_DOC
+/* DoC requires legacy NAND for now */
+#define CFG_NAND_LEGACY
 #endif
 
 /*
diff --git a/include/configs/PM826.h b/include/configs/PM826.h
index 6e5e3bbe18c..88fdb51adef 100644
--- a/include/configs/PM826.h
+++ b/include/configs/PM826.h
@@ -180,6 +180,8 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
+#define CFG_NAND_LEGACY
+
 /*
  * Disk-On-Chip configuration
  */
diff --git a/include/configs/PM828.h b/include/configs/PM828.h
index 982a1f81430..37ee9771b52 100644
--- a/include/configs/PM828.h
+++ b/include/configs/PM828.h
@@ -183,6 +183,7 @@
 /*
  * Disk-On-Chip configuration
  */
+#define CFG_NAND_LEGACY
 
 #define CFG_DOC_SHORT_TIMEOUT
 #define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices	*/
diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h
index c406c8f4bc1..e1155e2e438 100644
--- a/include/configs/PPChameleonEVB.h
+++ b/include/configs/PPChameleonEVB.h
@@ -188,36 +188,31 @@
  * NAND-FLASH stuff
  *-----------------------------------------------------------------------
  */
+/*
+ * nand device 1 on dave (PPChameleonEVB) needs more time,
+ * so we just introduce additional wait in nand_wait(),
+ * effectively for both devices.
+ */
+#define PPCHAMELON_NAND_TIMER_HACK
 
-/* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */
-#define CONFIG_NEW_NAND_CODE
 #define CFG_NAND0_BASE 0xFF400000
 #define CFG_NAND1_BASE 0xFF000000
 #define CFG_NAND_BASE_LIST	{ CFG_NAND0_BASE, CFG_NAND1_BASE }
 #define NAND_BIG_DELAY_US	25
 #define CFG_MAX_NAND_DEVICE	2	/* Max number of NAND devices */
-#define SECTORSIZE 512
-#define NAND_NO_RB
 
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define NAND_ChipID_UNKNOWN	0x00
-#define NAND_MAX_FLOORS 1
 #define NAND_MAX_CHIPS 1
 
 #define CFG_NAND0_CE  (0x80000000 >> 1)	 /* our CE is GPIO1 */
+#define CFG_NAND0_RDY (0x80000000 >> 4)	 /* our RDY is GPIO4 */
 #define CFG_NAND0_CLE (0x80000000 >> 2)	 /* our CLE is GPIO2 */
 #define CFG_NAND0_ALE (0x80000000 >> 3)	 /* our ALE is GPIO3 */
-#define CFG_NAND0_RDY (0x80000000 >> 4)	 /* our RDY is GPIO4 */
 
 #define CFG_NAND1_CE  (0x80000000 >> 14)  /* our CE is GPIO14 */
+#define CFG_NAND1_RDY (0x80000000 >> 31)  /* our RDY is GPIO31 */
 #define CFG_NAND1_CLE (0x80000000 >> 15)  /* our CLE is GPIO15 */
 #define CFG_NAND1_ALE (0x80000000 >> 16)  /* our ALE is GPIO16 */
-#define CFG_NAND1_RDY (0x80000000 >> 31)  /* our RDY is GPIO31 */
 
-#ifdef CONFIG_NEW_NAND_CODE
 #define MACRO_NAND_DISABLE_CE(nandptr) do \
 { \
 	switch((unsigned long)nandptr) \
@@ -293,83 +288,17 @@
 		break; \
 	} \
 } while(0)
-#else
-#define NAND_DISABLE_CE(nand) do \
-{ \
-	switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
-	{ \
-	    case CFG_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
-		break; \
-	    case CFG_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \
-		break; \
-	} \
-} while(0)
-
-#define NAND_ENABLE_CE(nand) do \
-{ \
-	switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
-	{ \
-	    case CFG_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
-		break; \
-	    case CFG_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \
-		break; \
-	} \
-} while(0)
-
-#define NAND_CTL_CLRALE(nandptr) do \
-{ \
-	switch((unsigned long)nandptr) \
-	{ \
-	    case CFG_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \
-		break; \
-	    case CFG_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \
-		break; \
-	} \
-} while(0)
 
-#define NAND_CTL_SETALE(nandptr) do \
-{ \
-	switch((unsigned long)nandptr) \
-	{ \
-	    case CFG_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \
-		break; \
-	    case CFG_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \
-		break; \
-	} \
-} while(0)
+#if 0
+#define SECTORSIZE 512
+#define NAND_NO_RB
 
-#define NAND_CTL_CLRCLE(nandptr) do \
-{ \
-	switch((unsigned long)nandptr) \
-	{ \
-	    case CFG_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \
-		break; \
-	    case CFG_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \
-		break; \
-	} \
-} while(0)
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
 
-#define NAND_CTL_SETCLE(nandptr) do { \
-	switch((unsigned long)nandptr) { \
-	case CFG_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
-		break; \
-	case CFG_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \
-		break; \
-	} \
-} while(0)
-#endif /* !CONFIG_NEW_NAND_CODE */
+#define NAND_ChipID_UNKNOWN	0x00
+#define NAND_MAX_FLOORS 1
 
 #ifdef NAND_NO_RB
 /* constant delay (see also tR in the datasheet) */
@@ -385,7 +314,7 @@
 #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
-
+#endif
 /*-----------------------------------------------------------------------
  * PCI stuff
  *-----------------------------------------------------------------------
diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h
index 242c837a3b8..21945a343cd 100644
--- a/include/configs/RBC823.h
+++ b/include/configs/RBC823.h
@@ -326,6 +326,8 @@
 /************************************************************
  * Disk-On-Chip configuration
  ************************************************************/
+#define CFG_NAND_LEGACY
+
 #define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices		*/
 #define CFG_DOC_SHORT_TIMEOUT
 #define CFG_DOC_SUPPORT_2000
diff --git a/include/configs/SXNI855T.h b/include/configs/SXNI855T.h
index c1c765f39d0..a8454d99fc0 100644
--- a/include/configs/SXNI855T.h
+++ b/include/configs/SXNI855T.h
@@ -183,6 +183,7 @@
 */
 
 /* NAND flash support */
+#define CFG_NAND_LEGACY
 #define CONFIG_MTD_NAND_ECC_JFFS2
 #define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices	*/
 #define SECTORSIZE 512
diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h
index 3ca137e53ac..96f3d26cc5e 100644
--- a/include/configs/VOH405.h
+++ b/include/configs/VOH405.h
@@ -141,6 +141,8 @@
  * NAND-FLASH stuff
  *-----------------------------------------------------------------------
  */
+#define CFG_NAND_LEGACY
+
 #define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
 #define SECTORSIZE 512
 
diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h
index d92f81f78ee..faf855d2492 100644
--- a/include/configs/WUH405.h
+++ b/include/configs/WUH405.h
@@ -133,6 +133,8 @@
  * NAND-FLASH stuff
  *-----------------------------------------------------------------------
  */
+#define CFG_NAND_LEGACY
+
 #define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
 #define SECTORSIZE 512
 
diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h
index eacc74446ce..6d3282150d7 100644
--- a/include/configs/bamboo.h
+++ b/include/configs/bamboo.h
@@ -43,6 +43,7 @@
  * 2nd ethernet port you have to "undef" the following define.
  */
 #define CONFIG_BAMBOO_NAND      1       /* enable nand flash support    */
+#define CFG_NAND_LEGACY
 
 /*-----------------------------------------------------------------------
  * Base addresses -- Note these are effective addresses where the
diff --git a/include/configs/delta.h b/include/configs/delta.h
index 8c848c35be6..8e5e6128f04 100644
--- a/include/configs/delta.h
+++ b/include/configs/delta.h
@@ -172,7 +172,7 @@
 #define SECTORSIZE 		512
 #define NAND_DELAY_US		25	/* mk@tbd: could be 0, I guess */
 
-/* nand timeout values */	
+/* nand timeout values */
 #define CFG_NAND_PROG_ERASE_TO	3000
 #define CFG_NAND_OTHER_TO	100
 #define CFG_NAND_SENDCMD_RETRY	3
diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h
new file mode 100644
index 00000000000..d4dee3b77a1
--- /dev/null
+++ b/include/configs/mcc200.h
@@ -0,0 +1,281 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5200
+#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU		*/
+#define CONFIG_MCC200		1	/* ... on MCC200 board			*/
+
+#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33MHz		*/
+
+#define CONFIG_MISC_INIT_R
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH 	*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot	     		*/
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs 			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value 	*/
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1			*/
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CONFIG_MII		1
+
+#define CONFIG_DOS_PARTITION
+
+/* USB */
+#define CONFIG_USB_OHCI
+#define ADD_USB_CMD             CFG_CMD_USB | CFG_CMD_FAT
+#define CONFIG_USB_STORAGE
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				ADD_USB_CMD	| \
+				CFG_CMD_BEDBUG	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_FAT	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=mcc200\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_6xx\0"					\
+	"bootfile=/tftpboot/mcc200/uImage\0"				\
+	"baudrate=115200\0"						\
+	"load=tftp 200000 /tftpboot/mcc200/u-boot.bin\0"		\
+	"update=protect off FFF00000 +${filesize};"			\
+		"era FFF00000 +${filesize};"				\
+		"cp.b 200000 FFF00000 ${filesize}\0"		        \
+	"serverip=192.168.1.1\0"					\
+	"ipaddr=192.168.133.144\0"					\
+	"netmask=255.255.0.0\0"						\
+	"unlock=yes\0"							\
+	"ethaddr=00:02:44:7D:73:3B\0"					\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CFG_IPBSPEED_133   		/* define for 133MHz speed */
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */
+
+#define CFG_I2C_SPEED		100000 /* 100 kHz */
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR		0x58
+#define CFG_I2C_EEPROM_ADDR_LEN		1
+#define CFG_EEPROM_PAGE_WRITE_BITS	4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_PCF8563
+#define CFG_I2C_RTC_ADDR		0x51
+
+/*
+ * Flash configuration (8,16 or 32 MB)
+ * TEXT base always at 0xFFF00000
+ * ENV_ADDR always at  0xFFF40000
+ * FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!)
+ *               0xFE000000 for 32 MB
+ *               0xFF000000 for 16 MB
+ *               0xFF800000 for  8 MB
+ */
+#define CFG_FLASH_BASE		0xfc000000
+#define CFG_FLASH_SIZE		0x04000000
+
+#define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
+#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
+
+#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CFG_FLASH_PROTECTION	1	/* hardware flash protection		*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/
+
+#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+
+#define CFG_ENV_SECT_SIZE	0x40000 	/* size of one complete sector	*/
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+#define CONFIG_ENV_OVERWRITE	1	/* allow modification of vendor params */
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR		0xf0000000
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_DEFAULT_MBAR	0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+
+
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE    TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#   define CFG_RAMBOOT		1
+#endif
+
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+/*
+ * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ */
+/* #define CONFIG_FEC_10MBIT 1 */
+#define CONFIG_PHY_ADDR		1
+
+/*
+ * GPIO configuration
+ */
+/* 0x10000004 = 32MB SDRAM */
+/* 0x90000004 = 64MB SDRAM */
+#define CFG_GPS_PORT_CONFIG	0x10000004
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	    */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+/*
+ * Various low-level settings
+ */
+#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL		HID0_ICE
+
+#define CFG_BOOTCS_START	CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
+#define CFG_BOOTCS_CFG		0x0004fb00
+#define CFG_CS0_START		CFG_FLASH_BASE
+#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+
+#define CFG_CS_BURST		0x00000000
+#define CFG_CS_DEADCYCLE	0x33333333
+
+#define CFG_RESET_ADDRESS	0xff000000
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK	0x0001BBBB
+#define CONFIG_USB_CONFIG	0x00005000
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/netstar.h b/include/configs/netstar.h
index 30d26547322..697796a1143 100644
--- a/include/configs/netstar.h
+++ b/include/configs/netstar.h
@@ -130,8 +130,8 @@
  * NAND flash
  */
 #define CFG_MAX_NAND_DEVICE	1
+#define NAND_MAX_CHIPS		1
 #define CFG_NAND_BASE	0x04000000 + (2 << 23)
-#define CONFIG_NEW_NAND_CODE
 
 /*
  * JFFS2 partitions (mtdparts command line support)
diff --git a/include/configs/svm_sc8xx.h b/include/configs/svm_sc8xx.h
index 7118f3f74be..92ee8cb3331 100644
--- a/include/configs/svm_sc8xx.h
+++ b/include/configs/svm_sc8xx.h
@@ -141,6 +141,7 @@
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
+#define CFG_NAND_LEGACY
 
 /*
  * Miscellaneous configurable options
diff --git a/include/flash.h b/include/flash.h
index 069aa63414d..84931917897 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -274,6 +274,12 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
 #define INTEL_ID_28F64K3    0x88018801	/*  64M =  32K x 255 + 32k x 4 */
 #define INTEL_ID_28F128K3   0x88028802	/* 128M =  64K x 255 + 32k x 4 */
 #define INTEL_ID_28F256K3   0x88038803	/* 256M = 128K x 255 + 32k x 4 */
+#define INTEL_ID_28F64P30T  0x88178817	/*  64M =  32K x 255 + 32k x 4 */
+#define INTEL_ID_28F64P30B  0x881A881A	/*  64M =  32K x 255 + 32k x 4 */
+#define INTEL_ID_28F128P30T 0x88188818	/* 128M =  64K x 255 + 32k x 4 */
+#define INTEL_ID_28F128P30B 0x881B881B	/* 128M =  64K x 255 + 32k x 4 */
+#define INTEL_ID_28F256P30T 0x88198819	/* 256M = 128K x 255 + 32k x 4 */
+#define INTEL_ID_28F256P30B 0x881C881C	/* 256M = 128K x 255 + 32k x 4 */
 
 #define INTEL_ID_28F160S3   0x00D000D0	/*  16M = 512K x  32 (64kB x 32)	*/
 #define INTEL_ID_28F320S3   0x00D400D4	/*  32M = 512K x  64 (64kB x 64)	*/
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index b0894c5e83d..a5227188d4f 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -2,10 +2,10 @@
  *  linux/include/linux/mtd/nand.h
  *
  *  Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
- *                     Steven J. Hill <sjhill@cotw.com>
- *		       Thomas Gleixner <gleixner@autronix.de>
+ *                     Steven J. Hill <sjhill@realitydiluted.com>
+ *		       Thomas Gleixner <tglx@linutronix.de>
  *
- * $Id: nand.h,v 1.7 2003/07/24 23:30:46 a0384864 Exp $
+ * $Id: nand.h,v 1.68 2004/11/12 10:40:37 gleixner Exp $
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -32,13 +32,65 @@
  *			command delay times for different chips
  *   04-28-2002 TG	OOB config defines moved from nand.c to avoid duplicate
  *			defines in jffs2/wbuf.c
+ *   08-07-2002 TG	forced bad block location to byte 5 of OOB, even if
+ *			CONFIG_MTD_NAND_ECC_JFFS2 is not set
+ *   08-10-2002 TG	extensions to nand_chip structure to support HW-ECC
+ *
+ *   08-29-2002 tglx 	nand_chip structure: data_poi for selecting
+ *			internal / fs-driver buffer
+ *			support for 6byte/512byte hardware ECC
+ *			read_ecc, write_ecc extended for different oob-layout
+ *			oob layout selections: NAND_NONE_OOB, NAND_JFFS2_OOB,
+ *			NAND_YAFFS_OOB
+ *  11-25-2002 tglx	Added Manufacturer code FUJITSU, NATIONAL
+ *			Split manufacturer and device ID structures
+ *
+ *  02-08-2004 tglx 	added option field to nand structure for chip anomalities
+ *  05-25-2004 tglx 	added bad block table support, ST-MICRO manufacturer id
+ *			update of nand_chip structure description
  */
 #ifndef __LINUX_MTD_NAND_H
 #define __LINUX_MTD_NAND_H
 
-#ifdef CONFIG_NEW_NAND_CODE
-#include "nand_new.h"
-#else
+#include <linux/mtd/compat.h>
+#include <linux/mtd/mtd.h>
+
+struct mtd_info;
+/* Scan and identify a NAND device */
+extern int nand_scan (struct mtd_info *mtd, int max_chips);
+/* Free resources held by the NAND device */
+extern void nand_release (struct mtd_info *mtd);
+
+/* Read raw data from the device without ECC */
+extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len, size_t ooblen);
+
+
+/* This constant declares the max. oobsize / page, which
+ * is supported now. If you add a chip with bigger oobsize/page
+ * adjust this accordingly.
+ */
+#define NAND_MAX_OOBSIZE	64
+
+/*
+ * Constants for hardware specific CLE/ALE/NCE function
+*/
+/* Select the chip by setting nCE to low */
+#define NAND_CTL_SETNCE 	1
+/* Deselect the chip by setting nCE to high */
+#define NAND_CTL_CLRNCE		2
+/* Select the command latch by setting CLE to high */
+#define NAND_CTL_SETCLE		3
+/* Deselect the command latch by setting CLE to low */
+#define NAND_CTL_CLRCLE		4
+/* Select the address latch by setting ALE to high */
+#define NAND_CTL_SETALE		5
+/* Deselect the address latch by setting ALE to low */
+#define NAND_CTL_CLRALE		6
+/* Set write protection by setting WP to high. Not used! */
+#define NAND_CTL_SETWP		7
+/* Clear write protection by setting WP to low. Not used! */
+#define NAND_CTL_CLRWP		8
+
 /*
  * Standard NAND flash commands
  */
@@ -48,12 +100,104 @@
 #define NAND_CMD_READOOB	0x50
 #define NAND_CMD_ERASE1		0x60
 #define NAND_CMD_STATUS		0x70
+#define NAND_CMD_STATUS_MULTI	0x71
 #define NAND_CMD_SEQIN		0x80
 #define NAND_CMD_READID		0x90
 #define NAND_CMD_ERASE2		0xd0
 #define NAND_CMD_RESET		0xff
 
+/* Extended commands for large page devices */
+#define NAND_CMD_READSTART	0x30
+#define NAND_CMD_CACHEDPROG	0x15
+
+/* Status bits */
+#define NAND_STATUS_FAIL	0x01
+#define NAND_STATUS_FAIL_N1	0x02
+#define NAND_STATUS_TRUE_READY	0x20
+#define NAND_STATUS_READY	0x40
+#define NAND_STATUS_WP		0x80
+
 /*
+ * Constants for ECC_MODES
+ */
+
+/* No ECC. Usage is not recommended ! */
+#define NAND_ECC_NONE		0
+/* Software ECC 3 byte ECC per 256 Byte data */
+#define NAND_ECC_SOFT		1
+/* Hardware ECC 3 byte ECC per 256 Byte data */
+#define NAND_ECC_HW3_256	2
+/* Hardware ECC 3 byte ECC per 512 Byte data */
+#define NAND_ECC_HW3_512	3
+/* Hardware ECC 3 byte ECC per 512 Byte data */
+#define NAND_ECC_HW6_512	4
+/* Hardware ECC 8 byte ECC per 512 Byte data */
+#define NAND_ECC_HW8_512	6
+/* Hardware ECC 12 byte ECC per 2048 Byte data */
+#define NAND_ECC_HW12_2048	7
+
+/*
+ * Constants for Hardware ECC
+*/
+/* Reset Hardware ECC for read */
+#define NAND_ECC_READ		0
+/* Reset Hardware ECC for write */
+#define NAND_ECC_WRITE		1
+/* Enable Hardware ECC before syndrom is read back from flash */
+#define NAND_ECC_READSYN	2
+
+/* Option constants for bizarre disfunctionality and real
+*  features
+*/
+/* Chip can not auto increment pages */
+#define NAND_NO_AUTOINCR	0x00000001
+/* Buswitdh is 16 bit */
+#define NAND_BUSWIDTH_16	0x00000002
+/* Device supports partial programming without padding */
+#define NAND_NO_PADDING		0x00000004
+/* Chip has cache program function */
+#define NAND_CACHEPRG		0x00000008
+/* Chip has copy back function */
+#define NAND_COPYBACK		0x00000010
+/* AND Chip which has 4 banks and a confusing page / block
+ * assignment. See Renesas datasheet for further information */
+#define NAND_IS_AND		0x00000020
+/* Chip has a array of 4 pages which can be read without
+ * additional ready /busy waits */
+#define NAND_4PAGE_ARRAY	0x00000040
+
+/* Options valid for Samsung large page devices */
+#define NAND_SAMSUNG_LP_OPTIONS \
+	(NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
+
+/* Macros to identify the above */
+#define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
+#define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
+#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
+#define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
+
+/* Mask to zero out the chip options, which come from the id table */
+#define NAND_CHIPOPTIONS_MSK	(0x0000ffff & ~NAND_NO_AUTOINCR)
+
+/* Non chip related options */
+/* Use a flash based bad block table. This option is passed to the
+ * default bad block table function. */
+#define NAND_USE_FLASH_BBT	0x00010000
+/* The hw ecc generator provides a syndrome instead a ecc value on read
+ * This can only work if we have the ecc bytes directly behind the
+ * data bytes. Applies for DOC and AG-AND Renesas HW Reed Solomon generators */
+#define NAND_HWECC_SYNDROME	0x00020000
+
+
+/* Options set by nand scan */
+/* Nand scan has allocated oob_buf */
+#define NAND_OOBBUF_ALLOC	0x40000000
+/* Nand scan has allocated data_buf */
+#define NAND_DATABUF_ALLOC	0x80000000
+
+
+/*
+ * nand_state_t - chip states
  * Enumeration for NAND flash chip state
  */
 typedef enum {
@@ -61,71 +205,138 @@ typedef enum {
 	FL_READING,
 	FL_WRITING,
 	FL_ERASING,
-	FL_SYNCING
+	FL_SYNCING,
+	FL_CACHEDPRG,
 } nand_state_t;
 
+/* Keep gcc happy */
+struct nand_chip;
 
-/*
- * NAND Private Flash Chip Data
- *
- * Structure overview:
- *
- *  IO_ADDR - address to access the 8 I/O lines of the flash device
- *
- *  hwcontrol - hardwarespecific function for accesing control-lines
- *
- *  dev_ready - hardwarespecific function for accesing device ready/busy line
- *
- *  chip_lock - spinlock used to protect access to this structure
- *
- *  wq - wait queue to sleep on if a NAND operation is in progress
- *
- *  state - give the current state of the NAND device
- *
- *  page_shift - number of address bits in a page (column address bits)
- *
- *  data_buf - data buffer passed to/from MTD user modules
- *
- *  data_cache - data cache for redundant page access and shadow for
- *		 ECC failure
- *
- *  ecc_code_buf - used only for holding calculated or read ECCs for
- *                 a page read or written when ECC is in use
- *
- *  reserved - padding to make structure fall on word boundary if
- *             when ECC is in use
+#if 0
+/**
+ * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independend devices
+ * @lock:               protection lock
+ * @active:		the mtd device which holds the controller currently
  */
-struct Nand {
-	char floor, chip;
-	unsigned long curadr;
-	unsigned char curmode;
-	/* Also some erase/write/pipeline info when we get that far */
+struct nand_hw_control {
+	spinlock_t	 lock;
+	struct nand_chip *active;
 };
+#endif
+
+/**
+ * struct nand_chip - NAND Private Flash Chip Data
+ * @IO_ADDR_R:		[BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
+ * @IO_ADDR_W:		[BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
+ * @read_byte:		[REPLACEABLE] read one byte from the chip
+ * @write_byte:		[REPLACEABLE] write one byte to the chip
+ * @read_word:		[REPLACEABLE] read one word from the chip
+ * @write_word:		[REPLACEABLE] write one word to the chip
+ * @write_buf:		[REPLACEABLE] write data from the buffer to the chip
+ * @read_buf:		[REPLACEABLE] read data from the chip into the buffer
+ * @verify_buf:		[REPLACEABLE] verify buffer contents against the chip data
+ * @select_chip:	[REPLACEABLE] select chip nr
+ * @block_bad:		[REPLACEABLE] check, if the block is bad
+ * @block_markbad:	[REPLACEABLE] mark the block bad
+ * @hwcontrol:		[BOARDSPECIFIC] hardwarespecific function for accesing control-lines
+ * @dev_ready:		[BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
+ *			If set to NULL no access to ready/busy is available and the ready/busy information
+ *			is read from the chip status register
+ * @cmdfunc:		[REPLACEABLE] hardwarespecific function for writing commands to the chip
+ * @waitfunc:		[REPLACEABLE] hardwarespecific function for wait on ready
+ * @calculate_ecc: 	[REPLACEABLE] function for ecc calculation or readback from ecc hardware
+ * @correct_data:	[REPLACEABLE] function for ecc correction, matching to ecc generator (sw/hw)
+ * @enable_hwecc:	[BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only
+ *			be provided if a hardware ECC is available
+ * @erase_cmd:		[INTERN] erase command write function, selectable due to AND support
+ * @scan_bbt:		[REPLACEABLE] function to scan bad block table
+ * @eccmode:		[BOARDSPECIFIC] mode of ecc, see defines
+ * @eccsize: 		[INTERN] databytes used per ecc-calculation
+ * @eccbytes: 		[INTERN] number of ecc bytes per ecc-calculation step
+ * @eccsteps:		[INTERN] number of ecc calculation steps per page
+ * @chip_delay:		[BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
+ * @chip_lock:		[INTERN] spinlock used to protect access to this structure and the chip
+ * @wq:			[INTERN] wait queue to sleep on if a NAND operation is in progress
+ * @state: 		[INTERN] the current state of the NAND device
+ * @page_shift:		[INTERN] number of address bits in a page (column address bits)
+ * @phys_erase_shift:	[INTERN] number of address bits in a physical eraseblock
+ * @bbt_erase_shift:	[INTERN] number of address bits in a bbt entry
+ * @chip_shift:		[INTERN] number of address bits in one chip
+ * @data_buf:		[INTERN] internal buffer for one page + oob
+ * @oob_buf:		[INTERN] oob buffer for one eraseblock
+ * @oobdirty:		[INTERN] indicates that oob_buf must be reinitialized
+ * @data_poi:		[INTERN] pointer to a data buffer
+ * @options:		[BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
+ *			special functionality. See the defines for further explanation
+ * @badblockpos:	[INTERN] position of the bad block marker in the oob area
+ * @numchips:		[INTERN] number of physical chips
+ * @chipsize:		[INTERN] the size of one chip for multichip arrays
+ * @pagemask:		[INTERN] page number mask = number of (pages / chip) - 1
+ * @pagebuf:		[INTERN] holds the pagenumber which is currently in data_buf
+ * @autooob:		[REPLACEABLE] the default (auto)placement scheme
+ * @bbt:		[INTERN] bad block table pointer
+ * @bbt_td:		[REPLACEABLE] bad block table descriptor for flash lookup
+ * @bbt_md:		[REPLACEABLE] bad block table mirror descriptor
+ * @badblock_pattern:	[REPLACEABLE] bad block scan pattern used for initial bad block scan
+ * @controller:		[OPTIONAL] a pointer to a hardware controller structure which is shared among multiple independend devices
+ * @priv:		[OPTIONAL] pointer to private chip date
+ */
 
 struct nand_chip {
+	void  __iomem	*IO_ADDR_R;
+	void  __iomem 	*IO_ADDR_W;
+
+	u_char		(*read_byte)(struct mtd_info *mtd);
+	void		(*write_byte)(struct mtd_info *mtd, u_char byte);
+	u16		(*read_word)(struct mtd_info *mtd);
+	void		(*write_word)(struct mtd_info *mtd, u16 word);
+
+	void		(*write_buf)(struct mtd_info *mtd, const u_char *buf, int len);
+	void		(*read_buf)(struct mtd_info *mtd, u_char *buf, int len);
+	int		(*verify_buf)(struct mtd_info *mtd, const u_char *buf, int len);
+	void		(*select_chip)(struct mtd_info *mtd, int chip);
+	int		(*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
+	int		(*block_markbad)(struct mtd_info *mtd, loff_t ofs);
+	void 		(*hwcontrol)(struct mtd_info *mtd, int cmd);
+	int  		(*dev_ready)(struct mtd_info *mtd);
+	void 		(*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
+	int 		(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this, int state);
+	int		(*calculate_ecc)(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code);
+	int 		(*correct_data)(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc);
+	void		(*enable_hwecc)(struct mtd_info *mtd, int mode);
+	void		(*erase_cmd)(struct mtd_info *mtd, int page);
+	int		(*scan_bbt)(struct mtd_info *mtd);
+	int		eccmode;
+	int		eccsize;
+	int		eccbytes;
+	int		eccsteps;
+	int 		chip_delay;
+#if 0
+	spinlock_t	chip_lock;
+	wait_queue_head_t wq;
+	nand_state_t 	state;
+#endif
 	int 		page_shift;
+	int		phys_erase_shift;
+	int		bbt_erase_shift;
+	int		chip_shift;
 	u_char 		*data_buf;
-	u_char 		*data_cache;
-	int		cache_page;
-	u_char 		ecc_code_buf[6];
-	u_char 		reserved[2];
-	char ChipID; /* Type of DiskOnChip */
-	struct Nand *chips;
-	int chipshift;
-	char* chips_name;
-	unsigned long erasesize;
-	unsigned long mfr; /* Flash IDs - only one type of flash per device */
-	unsigned long id;
-	char* name;
-	int numchips;
-	char page256;
-	char pageadrlen;
-	unsigned long IO_ADDR;  /* address to access the 8 I/O lines to the flash device */
-	unsigned long totlen;
-	uint oobblock;  /* Size of OOB blocks (e.g. 512) */
-	uint oobsize;   /* Amount of OOB data per block (e.g. 16) */
-	uint eccsize;
-	int bus16;
+	u_char		*oob_buf;
+	int		oobdirty;
+	u_char		*data_poi;
+	unsigned int	options;
+	int		badblockpos;
+	int		numchips;
+	unsigned long	chipsize;
+	int		pagemask;
+	int		pagebuf;
+	struct nand_oobinfo	*autooob;
+	uint8_t		*bbt;
+	struct nand_bbt_descr	*bbt_td;
+	struct nand_bbt_descr	*bbt_md;
+	struct nand_bbt_descr	*badblock_pattern;
+	struct nand_hw_control  *controller;
+	void		*priv;
 };
 
 /*
@@ -133,71 +344,125 @@ struct nand_chip {
  */
 #define NAND_MFR_TOSHIBA	0x98
 #define NAND_MFR_SAMSUNG	0xec
+#define NAND_MFR_FUJITSU	0x04
+#define NAND_MFR_NATIONAL	0x8f
+#define NAND_MFR_RENESAS	0x07
+#define NAND_MFR_STMICRO	0x20
 
-/*
- * NAND Flash Device ID Structure
- *
- * Structure overview:
- *
- *  name - Complete name of device
- *
- *  manufacture_id - manufacturer ID code of device.
- *
- *  model_id - model ID code of device.
- *
- *  chipshift - total number of address bits for the device which
- *              is used to calculate address offsets and the total
- *              number of bytes the device is capable of.
+/**
+ * struct nand_flash_dev - NAND Flash Device ID Structure
  *
- *  page256 - denotes if flash device has 256 byte pages or not.
- *
- *  pageadrlen - number of bytes minus one needed to hold the
- *               complete address into the flash array. Keep in
- *               mind that when a read or write is done to a
- *               specific address, the address is input serially
- *               8 bits at a time. This structure member is used
- *               by the read/write routines as a loop index for
- *               shifting the address out 8 bits at a time.
- *
- *  erasesize - size of an erase block in the flash device.
+ * @name:  	Identify the device type
+ * @id:   	device ID code
+ * @pagesize:  	Pagesize in bytes. Either 256 or 512 or 0
+ *		If the pagesize is 0, then the real pagesize
+ *		and the eraseize are determined from the
+ *		extended id bytes in the chip
+ * @erasesize: 	Size of an erase block in the flash device.
+ * @chipsize:  	Total chipsize in Mega Bytes
+ * @options:	Bitfield to store chip relevant options
  */
 struct nand_flash_dev {
-	char * name;
-	int manufacture_id;
-	int model_id;
-	int chipshift;
-	char page256;
-	char pageadrlen;
+	char *name;
+	int id;
+	unsigned long pagesize;
+	unsigned long chipsize;
 	unsigned long erasesize;
-	int bus16;
+	unsigned long options;
 };
 
+/**
+ * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
+ * @name:	Manufacturer name
+ * @id: 	manufacturer ID code of device.
+*/
+struct nand_manufacturers {
+	int id;
+	char * name;
+};
+
+extern struct nand_flash_dev nand_flash_ids[];
+extern struct nand_manufacturers nand_manuf_ids[];
+
+/**
+ * struct nand_bbt_descr - bad block table descriptor
+ * @options:	options for this descriptor
+ * @pages:	the page(s) where we find the bbt, used with option BBT_ABSPAGE
+ *		when bbt is searched, then we store the found bbts pages here.
+ *		Its an array and supports up to 8 chips now
+ * @offs:	offset of the pattern in the oob area of the page
+ * @veroffs:	offset of the bbt version counter in the oob are of the page
+ * @version:	version read from the bbt page during scan
+ * @len:	length of the pattern, if 0 no pattern check is performed
+ * @maxblocks:	maximum number of blocks to search for a bbt. This number of
+ *		blocks is reserved at the end of the device where the tables are
+ *		written.
+ * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
+ *              bad) block in the stored bbt
+ * @pattern:	pattern to identify bad block table or factory marked good /
+ *		bad blocks, can be NULL, if len = 0
+ *
+ * Descriptor for the bad block table marker and the descriptor for the
+ * pattern which identifies good and bad blocks. The assumption is made
+ * that the pattern and the version count are always located in the oob area
+ * of the first block.
+ */
+struct nand_bbt_descr {
+	int	options;
+	int	pages[NAND_MAX_CHIPS];
+	int	offs;
+	int	veroffs;
+	uint8_t	version[NAND_MAX_CHIPS];
+	int	len;
+	int 	maxblocks;
+	int	reserved_block_code;
+	uint8_t	*pattern;
+};
+
+/* Options for the bad block table descriptors */
+
+/* The number of bits used per block in the bbt on the device */
+#define NAND_BBT_NRBITS_MSK	0x0000000F
+#define NAND_BBT_1BIT		0x00000001
+#define NAND_BBT_2BIT		0x00000002
+#define NAND_BBT_4BIT		0x00000004
+#define NAND_BBT_8BIT		0x00000008
+/* The bad block table is in the last good block of the device */
+#define	NAND_BBT_LASTBLOCK	0x00000010
+/* The bbt is at the given page, else we must scan for the bbt */
+#define NAND_BBT_ABSPAGE	0x00000020
+/* The bbt is at the given page, else we must scan for the bbt */
+#define NAND_BBT_SEARCH		0x00000040
+/* bbt is stored per chip on multichip devices */
+#define NAND_BBT_PERCHIP	0x00000080
+/* bbt has a version counter at offset veroffs */
+#define NAND_BBT_VERSION	0x00000100
+/* Create a bbt if none axists */
+#define NAND_BBT_CREATE		0x00000200
+/* Search good / bad pattern through all pages of a block */
+#define NAND_BBT_SCANALLPAGES	0x00000400
+/* Scan block empty during good / bad block scan */
+#define NAND_BBT_SCANEMPTY	0x00000800
+/* Write bbt if neccecary */
+#define NAND_BBT_WRITE		0x00001000
+/* Read and write back block contents when writing bbt */
+#define NAND_BBT_SAVECONTENT	0x00002000
+/* Search good / bad pattern on the first and the second page */
+#define NAND_BBT_SCAN2NDPAGE	0x00004000
+
+/* The maximum number of blocks to scan for a bbt */
+#define NAND_BBT_SCAN_MAXBLOCKS	4
+
+extern int nand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd);
+extern int nand_update_bbt (struct mtd_info *mtd, loff_t offs);
+extern int nand_default_bbt (struct mtd_info *mtd);
+extern int nand_isbad_bbt (struct mtd_info *mtd, loff_t offs, int allowbbt);
+extern int nand_erase_nand (struct mtd_info *mtd, struct erase_info *instr, int allowbbt);
+
 /*
 * Constants for oob configuration
 */
-#define NAND_NOOB_ECCPOS0		0
-#define NAND_NOOB_ECCPOS1		1
-#define NAND_NOOB_ECCPOS2		2
-#define NAND_NOOB_ECCPOS3		3
-#define NAND_NOOB_ECCPOS4		6
-#define NAND_NOOB_ECCPOS5		7
-#define NAND_NOOB_BADBPOS		-1
-#define NAND_NOOB_ECCVPOS		-1
-
-#define NAND_JFFS2_OOB_ECCPOS0		0
-#define NAND_JFFS2_OOB_ECCPOS1		1
-#define NAND_JFFS2_OOB_ECCPOS2		2
-#define NAND_JFFS2_OOB_ECCPOS3		3
-#define NAND_JFFS2_OOB_ECCPOS4		6
-#define NAND_JFFS2_OOB_ECCPOS5		7
-#define NAND_JFFS2_OOB_BADBPOS		5
-#define NAND_JFFS2_OOB_ECCVPOS		4
-
-#define NAND_JFFS2_OOB8_FSDAPOS		6
-#define NAND_JFFS2_OOB16_FSDAPOS	8
-#define NAND_JFFS2_OOB8_FSDALEN		2
-#define NAND_JFFS2_OOB16_FSDALEN	8
-
-unsigned long nand_probe(unsigned long physadr);
-#endif /* !CONFIG_NEW_NAND_CODE */
+#define NAND_SMALL_BADBLOCK_POS		5
+#define NAND_LARGE_BADBLOCK_POS		0
+
 #endif /* __LINUX_MTD_NAND_H */
diff --git a/include/linux/mtd/nand_ids.h b/include/linux/mtd/nand_ids.h
index 75c305b569f..d9eb9118280 100644
--- a/include/linux/mtd/nand_ids.h
+++ b/include/linux/mtd/nand_ids.h
@@ -28,6 +28,10 @@
 #ifndef __LINUX_MTD_NAND_IDS_H
 #define __LINUX_MTD_NAND_IDS_H
 
+#ifndef CFG_NAND_LEGACY
+#error This module is for the legacy NAND support
+#endif
+
 static struct nand_flash_dev nand_flash_ids[] = {
 	{"Toshiba TC5816BDC",     NAND_MFR_TOSHIBA, 0x64, 21, 1, 2, 0x1000, 0},
 	{"Toshiba TC5832DC",      NAND_MFR_TOSHIBA, 0x6b, 22, 0, 2, 0x2000, 0},
diff --git a/include/linux/mtd/nand_legacy.h b/include/linux/mtd/nand_legacy.h
new file mode 100644
index 00000000000..a8769e72ad7
--- /dev/null
+++ b/include/linux/mtd/nand_legacy.h
@@ -0,0 +1,203 @@
+/*
+ *  linux/include/linux/mtd/nand.h
+ *
+ *  Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
+ *                     Steven J. Hill <sjhill@cotw.com>
+ *		       Thomas Gleixner <gleixner@autronix.de>
+ *
+ * $Id: nand.h,v 1.7 2003/07/24 23:30:46 a0384864 Exp $
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Info:
+ *   Contains standard defines and IDs for NAND flash devices
+ *
+ *  Changelog:
+ *   01-31-2000 DMW     Created
+ *   09-18-2000 SJH     Moved structure out of the Disk-On-Chip drivers
+ *			so it can be used by other NAND flash device
+ *			drivers. I also changed the copyright since none
+ *			of the original contents of this file are specific
+ *			to DoC devices. David can whack me with a baseball
+ *			bat later if I did something naughty.
+ *   10-11-2000 SJH     Added private NAND flash structure for driver
+ *   10-24-2000 SJH     Added prototype for 'nand_scan' function
+ *   10-29-2001 TG	changed nand_chip structure to support
+ *			hardwarespecific function for accessing control lines
+ *   02-21-2002 TG	added support for different read/write adress and
+ *			ready/busy line access function
+ *   02-26-2002 TG	added chip_delay to nand_chip structure to optimize
+ *			command delay times for different chips
+ *   04-28-2002 TG	OOB config defines moved from nand.c to avoid duplicate
+ *			defines in jffs2/wbuf.c
+ */
+#ifndef __LINUX_MTD_NAND_LEGACY_H
+#define __LINUX_MTD_NAND_LEGACY_H
+
+#ifndef CFG_NAND_LEGACY
+#error This module is for the legacy NAND support
+#endif
+
+/*
+ * Standard NAND flash commands
+ */
+#define NAND_CMD_READ0		0
+#define NAND_CMD_READ1		1
+#define NAND_CMD_PAGEPROG	0x10
+#define NAND_CMD_READOOB	0x50
+#define NAND_CMD_ERASE1		0x60
+#define NAND_CMD_STATUS		0x70
+#define NAND_CMD_SEQIN		0x80
+#define NAND_CMD_READID		0x90
+#define NAND_CMD_ERASE2		0xd0
+#define NAND_CMD_RESET		0xff
+
+/*
+ * Enumeration for NAND flash chip state
+ */
+typedef enum {
+	FL_READY,
+	FL_READING,
+	FL_WRITING,
+	FL_ERASING,
+	FL_SYNCING
+} nand_state_t;
+
+
+/*
+ * NAND Private Flash Chip Data
+ *
+ * Structure overview:
+ *
+ *  IO_ADDR - address to access the 8 I/O lines of the flash device
+ *
+ *  hwcontrol - hardwarespecific function for accesing control-lines
+ *
+ *  dev_ready - hardwarespecific function for accesing device ready/busy line
+ *
+ *  chip_lock - spinlock used to protect access to this structure
+ *
+ *  wq - wait queue to sleep on if a NAND operation is in progress
+ *
+ *  state - give the current state of the NAND device
+ *
+ *  page_shift - number of address bits in a page (column address bits)
+ *
+ *  data_buf - data buffer passed to/from MTD user modules
+ *
+ *  data_cache - data cache for redundant page access and shadow for
+ *		 ECC failure
+ *
+ *  ecc_code_buf - used only for holding calculated or read ECCs for
+ *                 a page read or written when ECC is in use
+ *
+ *  reserved - padding to make structure fall on word boundary if
+ *             when ECC is in use
+ */
+struct Nand {
+	char floor, chip;
+	unsigned long curadr;
+	unsigned char curmode;
+	/* Also some erase/write/pipeline info when we get that far */
+};
+
+struct nand_chip {
+	int 		page_shift;
+	u_char 		*data_buf;
+	u_char 		*data_cache;
+	int		cache_page;
+	u_char 		ecc_code_buf[6];
+	u_char 		reserved[2];
+	char ChipID; /* Type of DiskOnChip */
+	struct Nand *chips;
+	int chipshift;
+	char* chips_name;
+	unsigned long erasesize;
+	unsigned long mfr; /* Flash IDs - only one type of flash per device */
+	unsigned long id;
+	char* name;
+	int numchips;
+	char page256;
+	char pageadrlen;
+	unsigned long IO_ADDR;  /* address to access the 8 I/O lines to the flash device */
+	unsigned long totlen;
+	uint oobblock;  /* Size of OOB blocks (e.g. 512) */
+	uint oobsize;   /* Amount of OOB data per block (e.g. 16) */
+	uint eccsize;
+	int bus16;
+};
+
+/*
+ * NAND Flash Manufacturer ID Codes
+ */
+#define NAND_MFR_TOSHIBA	0x98
+#define NAND_MFR_SAMSUNG	0xec
+
+/*
+ * NAND Flash Device ID Structure
+ *
+ * Structure overview:
+ *
+ *  name - Complete name of device
+ *
+ *  manufacture_id - manufacturer ID code of device.
+ *
+ *  model_id - model ID code of device.
+ *
+ *  chipshift - total number of address bits for the device which
+ *              is used to calculate address offsets and the total
+ *              number of bytes the device is capable of.
+ *
+ *  page256 - denotes if flash device has 256 byte pages or not.
+ *
+ *  pageadrlen - number of bytes minus one needed to hold the
+ *               complete address into the flash array. Keep in
+ *               mind that when a read or write is done to a
+ *               specific address, the address is input serially
+ *               8 bits at a time. This structure member is used
+ *               by the read/write routines as a loop index for
+ *               shifting the address out 8 bits at a time.
+ *
+ *  erasesize - size of an erase block in the flash device.
+ */
+struct nand_flash_dev {
+	char * name;
+	int manufacture_id;
+	int model_id;
+	int chipshift;
+	char page256;
+	char pageadrlen;
+	unsigned long erasesize;
+	int bus16;
+};
+
+/*
+* Constants for oob configuration
+*/
+#define NAND_NOOB_ECCPOS0		0
+#define NAND_NOOB_ECCPOS1		1
+#define NAND_NOOB_ECCPOS2		2
+#define NAND_NOOB_ECCPOS3		3
+#define NAND_NOOB_ECCPOS4		6
+#define NAND_NOOB_ECCPOS5		7
+#define NAND_NOOB_BADBPOS		-1
+#define NAND_NOOB_ECCVPOS		-1
+
+#define NAND_JFFS2_OOB_ECCPOS0		0
+#define NAND_JFFS2_OOB_ECCPOS1		1
+#define NAND_JFFS2_OOB_ECCPOS2		2
+#define NAND_JFFS2_OOB_ECCPOS3		3
+#define NAND_JFFS2_OOB_ECCPOS4		6
+#define NAND_JFFS2_OOB_ECCPOS5		7
+#define NAND_JFFS2_OOB_BADBPOS		5
+#define NAND_JFFS2_OOB_ECCVPOS		4
+
+#define NAND_JFFS2_OOB8_FSDAPOS		6
+#define NAND_JFFS2_OOB16_FSDAPOS	8
+#define NAND_JFFS2_OOB8_FSDALEN		2
+#define NAND_JFFS2_OOB16_FSDALEN	8
+
+unsigned long nand_probe(unsigned long physadr);
+#endif /* __LINUX_MTD_NAND_LEGACY_H */
diff --git a/include/linux/mtd/nand_new.h b/include/linux/mtd/nand_new.h
deleted file mode 100644
index 7d4b805b9ad..00000000000
--- a/include/linux/mtd/nand_new.h
+++ /dev/null
@@ -1,469 +0,0 @@
-/*
- *  linux/include/linux/mtd/nand.h
- *
- *  Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
- *                     Steven J. Hill <sjhill@realitydiluted.com>
- *		       Thomas Gleixner <tglx@linutronix.de>
- *
- * $Id: nand.h,v 1.68 2004/11/12 10:40:37 gleixner Exp $
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  Info:
- *   Contains standard defines and IDs for NAND flash devices
- *
- *  Changelog:
- *   01-31-2000 DMW     Created
- *   09-18-2000 SJH     Moved structure out of the Disk-On-Chip drivers
- *			so it can be used by other NAND flash device
- *			drivers. I also changed the copyright since none
- *			of the original contents of this file are specific
- *			to DoC devices. David can whack me with a baseball
- *			bat later if I did something naughty.
- *   10-11-2000 SJH     Added private NAND flash structure for driver
- *   10-24-2000 SJH     Added prototype for 'nand_scan' function
- *   10-29-2001 TG	changed nand_chip structure to support
- *			hardwarespecific function for accessing control lines
- *   02-21-2002 TG	added support for different read/write adress and
- *			ready/busy line access function
- *   02-26-2002 TG	added chip_delay to nand_chip structure to optimize
- *			command delay times for different chips
- *   04-28-2002 TG	OOB config defines moved from nand.c to avoid duplicate
- *			defines in jffs2/wbuf.c
- *   08-07-2002 TG	forced bad block location to byte 5 of OOB, even if
- *			CONFIG_MTD_NAND_ECC_JFFS2 is not set
- *   08-10-2002 TG	extensions to nand_chip structure to support HW-ECC
- *
- *   08-29-2002 tglx 	nand_chip structure: data_poi for selecting
- *			internal / fs-driver buffer
- *			support for 6byte/512byte hardware ECC
- *			read_ecc, write_ecc extended for different oob-layout
- *			oob layout selections: NAND_NONE_OOB, NAND_JFFS2_OOB,
- *			NAND_YAFFS_OOB
- *  11-25-2002 tglx	Added Manufacturer code FUJITSU, NATIONAL
- *			Split manufacturer and device ID structures
- *
- *  02-08-2004 tglx 	added option field to nand structure for chip anomalities
- *  05-25-2004 tglx 	added bad block table support, ST-MICRO manufacturer id
- *			update of nand_chip structure description
- */
-#ifndef __LINUX_MTD_NAND_NEW_H
-#define __LINUX_MTD_NAND_NEW_H
-
-#include <linux/mtd/compat.h>
-#include <linux/mtd/mtd.h>
-
-struct mtd_info;
-/* Scan and identify a NAND device */
-extern int nand_scan (struct mtd_info *mtd, int max_chips);
-/* Free resources held by the NAND device */
-extern void nand_release (struct mtd_info *mtd);
-
-/* Read raw data from the device without ECC */
-extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len, size_t ooblen);
-
-
-
-/* This constant declares the max. oobsize / page, which
- * is supported now. If you add a chip with bigger oobsize/page
- * adjust this accordingly.
- */
-#define NAND_MAX_OOBSIZE	64
-
-/*
- * Constants for hardware specific CLE/ALE/NCE function
-*/
-/* Select the chip by setting nCE to low */
-#define NAND_CTL_SETNCE 	1
-/* Deselect the chip by setting nCE to high */
-#define NAND_CTL_CLRNCE		2
-/* Select the command latch by setting CLE to high */
-#define NAND_CTL_SETCLE		3
-/* Deselect the command latch by setting CLE to low */
-#define NAND_CTL_CLRCLE		4
-/* Select the address latch by setting ALE to high */
-#define NAND_CTL_SETALE		5
-/* Deselect the address latch by setting ALE to low */
-#define NAND_CTL_CLRALE		6
-/* Set write protection by setting WP to high. Not used! */
-#define NAND_CTL_SETWP		7
-/* Clear write protection by setting WP to low. Not used! */
-#define NAND_CTL_CLRWP		8
-
-/*
- * Standard NAND flash commands
- */
-#define NAND_CMD_READ0		0
-#define NAND_CMD_READ1		1
-#define NAND_CMD_PAGEPROG	0x10
-#define NAND_CMD_READOOB	0x50
-#define NAND_CMD_ERASE1		0x60
-#define NAND_CMD_STATUS		0x70
-#define NAND_CMD_STATUS_MULTI	0x71
-#define NAND_CMD_SEQIN		0x80
-#define NAND_CMD_READID		0x90
-#define NAND_CMD_ERASE2		0xd0
-#define NAND_CMD_RESET		0xff
-
-/* Extended commands for large page devices */
-#define NAND_CMD_READSTART	0x30
-#define NAND_CMD_CACHEDPROG	0x15
-
-/* Status bits */
-#define NAND_STATUS_FAIL	0x01
-#define NAND_STATUS_FAIL_N1	0x02
-#define NAND_STATUS_TRUE_READY	0x20
-#define NAND_STATUS_READY	0x40
-#define NAND_STATUS_WP		0x80
-
-/*
- * Constants for ECC_MODES
- */
-
-/* No ECC. Usage is not recommended ! */
-#define NAND_ECC_NONE		0
-/* Software ECC 3 byte ECC per 256 Byte data */
-#define NAND_ECC_SOFT		1
-/* Hardware ECC 3 byte ECC per 256 Byte data */
-#define NAND_ECC_HW3_256	2
-/* Hardware ECC 3 byte ECC per 512 Byte data */
-#define NAND_ECC_HW3_512	3
-/* Hardware ECC 3 byte ECC per 512 Byte data */
-#define NAND_ECC_HW6_512	4
-/* Hardware ECC 8 byte ECC per 512 Byte data */
-#define NAND_ECC_HW8_512	6
-/* Hardware ECC 12 byte ECC per 2048 Byte data */
-#define NAND_ECC_HW12_2048	7
-
-/*
- * Constants for Hardware ECC
-*/
-/* Reset Hardware ECC for read */
-#define NAND_ECC_READ		0
-/* Reset Hardware ECC for write */
-#define NAND_ECC_WRITE		1
-/* Enable Hardware ECC before syndrom is read back from flash */
-#define NAND_ECC_READSYN	2
-
-/* Option constants for bizarre disfunctionality and real
-*  features
-*/
-/* Chip can not auto increment pages */
-#define NAND_NO_AUTOINCR	0x00000001
-/* Buswitdh is 16 bit */
-#define NAND_BUSWIDTH_16	0x00000002
-/* Device supports partial programming without padding */
-#define NAND_NO_PADDING		0x00000004
-/* Chip has cache program function */
-#define NAND_CACHEPRG		0x00000008
-/* Chip has copy back function */
-#define NAND_COPYBACK		0x00000010
-/* AND Chip which has 4 banks and a confusing page / block
- * assignment. See Renesas datasheet for further information */
-#define NAND_IS_AND		0x00000020
-/* Chip has a array of 4 pages which can be read without
- * additional ready /busy waits */
-#define NAND_4PAGE_ARRAY	0x00000040
-
-/* Options valid for Samsung large page devices */
-#define NAND_SAMSUNG_LP_OPTIONS \
-	(NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
-
-/* Macros to identify the above */
-#define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
-#define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
-#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
-#define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
-
-/* Mask to zero out the chip options, which come from the id table */
-#define NAND_CHIPOPTIONS_MSK	(0x0000ffff & ~NAND_NO_AUTOINCR)
-
-/* Non chip related options */
-/* Use a flash based bad block table. This option is passed to the
- * default bad block table function. */
-#define NAND_USE_FLASH_BBT	0x00010000
-/* The hw ecc generator provides a syndrome instead a ecc value on read
- * This can only work if we have the ecc bytes directly behind the
- * data bytes. Applies for DOC and AG-AND Renesas HW Reed Solomon generators */
-#define NAND_HWECC_SYNDROME	0x00020000
-
-
-/* Options set by nand scan */
-/* Nand scan has allocated oob_buf */
-#define NAND_OOBBUF_ALLOC	0x40000000
-/* Nand scan has allocated data_buf */
-#define NAND_DATABUF_ALLOC	0x80000000
-
-
-/*
- * nand_state_t - chip states
- * Enumeration for NAND flash chip state
- */
-typedef enum {
-	FL_READY,
-	FL_READING,
-	FL_WRITING,
-	FL_ERASING,
-	FL_SYNCING,
-	FL_CACHEDPRG,
-} nand_state_t;
-
-/* Keep gcc happy */
-struct nand_chip;
-
-#if 0
-/**
- * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independend devices
- * @lock:               protection lock
- * @active:		the mtd device which holds the controller currently
- */
-struct nand_hw_control {
-	spinlock_t	 lock;
-	struct nand_chip *active;
-};
-#endif
-
-/**
- * struct nand_chip - NAND Private Flash Chip Data
- * @IO_ADDR_R:		[BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
- * @IO_ADDR_W:		[BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
- * @read_byte:		[REPLACEABLE] read one byte from the chip
- * @write_byte:		[REPLACEABLE] write one byte to the chip
- * @read_word:		[REPLACEABLE] read one word from the chip
- * @write_word:		[REPLACEABLE] write one word to the chip
- * @write_buf:		[REPLACEABLE] write data from the buffer to the chip
- * @read_buf:		[REPLACEABLE] read data from the chip into the buffer
- * @verify_buf:		[REPLACEABLE] verify buffer contents against the chip data
- * @select_chip:	[REPLACEABLE] select chip nr
- * @block_bad:		[REPLACEABLE] check, if the block is bad
- * @block_markbad:	[REPLACEABLE] mark the block bad
- * @hwcontrol:		[BOARDSPECIFIC] hardwarespecific function for accesing control-lines
- * @dev_ready:		[BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
- *			If set to NULL no access to ready/busy is available and the ready/busy information
- *			is read from the chip status register
- * @cmdfunc:		[REPLACEABLE] hardwarespecific function for writing commands to the chip
- * @waitfunc:		[REPLACEABLE] hardwarespecific function for wait on ready
- * @calculate_ecc: 	[REPLACEABLE] function for ecc calculation or readback from ecc hardware
- * @correct_data:	[REPLACEABLE] function for ecc correction, matching to ecc generator (sw/hw)
- * @enable_hwecc:	[BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only
- *			be provided if a hardware ECC is available
- * @erase_cmd:		[INTERN] erase command write function, selectable due to AND support
- * @scan_bbt:		[REPLACEABLE] function to scan bad block table
- * @eccmode:		[BOARDSPECIFIC] mode of ecc, see defines
- * @eccsize: 		[INTERN] databytes used per ecc-calculation
- * @eccbytes: 		[INTERN] number of ecc bytes per ecc-calculation step
- * @eccsteps:		[INTERN] number of ecc calculation steps per page
- * @chip_delay:		[BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
- * @chip_lock:		[INTERN] spinlock used to protect access to this structure and the chip
- * @wq:			[INTERN] wait queue to sleep on if a NAND operation is in progress
- * @state: 		[INTERN] the current state of the NAND device
- * @page_shift:		[INTERN] number of address bits in a page (column address bits)
- * @phys_erase_shift:	[INTERN] number of address bits in a physical eraseblock
- * @bbt_erase_shift:	[INTERN] number of address bits in a bbt entry
- * @chip_shift:		[INTERN] number of address bits in one chip
- * @data_buf:		[INTERN] internal buffer for one page + oob
- * @oob_buf:		[INTERN] oob buffer for one eraseblock
- * @oobdirty:		[INTERN] indicates that oob_buf must be reinitialized
- * @data_poi:		[INTERN] pointer to a data buffer
- * @options:		[BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
- *			special functionality. See the defines for further explanation
- * @badblockpos:	[INTERN] position of the bad block marker in the oob area
- * @numchips:		[INTERN] number of physical chips
- * @chipsize:		[INTERN] the size of one chip for multichip arrays
- * @pagemask:		[INTERN] page number mask = number of (pages / chip) - 1
- * @pagebuf:		[INTERN] holds the pagenumber which is currently in data_buf
- * @autooob:		[REPLACEABLE] the default (auto)placement scheme
- * @bbt:		[INTERN] bad block table pointer
- * @bbt_td:		[REPLACEABLE] bad block table descriptor for flash lookup
- * @bbt_md:		[REPLACEABLE] bad block table mirror descriptor
- * @badblock_pattern:	[REPLACEABLE] bad block scan pattern used for initial bad block scan
- * @controller:		[OPTIONAL] a pointer to a hardware controller structure which is shared among multiple independend devices
- * @priv:		[OPTIONAL] pointer to private chip date
- */
-
-struct nand_chip {
-	void  __iomem	*IO_ADDR_R;
-	void  __iomem 	*IO_ADDR_W;
-
-	u_char		(*read_byte)(struct mtd_info *mtd);
-	void		(*write_byte)(struct mtd_info *mtd, u_char byte);
-	u16		(*read_word)(struct mtd_info *mtd);
-	void		(*write_word)(struct mtd_info *mtd, u16 word);
-
-	void		(*write_buf)(struct mtd_info *mtd, const u_char *buf, int len);
-	void		(*read_buf)(struct mtd_info *mtd, u_char *buf, int len);
-	int		(*verify_buf)(struct mtd_info *mtd, const u_char *buf, int len);
-	void		(*select_chip)(struct mtd_info *mtd, int chip);
-	int		(*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
-	int		(*block_markbad)(struct mtd_info *mtd, loff_t ofs);
-	void 		(*hwcontrol)(struct mtd_info *mtd, int cmd);
-	int  		(*dev_ready)(struct mtd_info *mtd);
-	void 		(*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
-	int 		(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this, int state);
-	int		(*calculate_ecc)(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code);
-	int 		(*correct_data)(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc);
-	void		(*enable_hwecc)(struct mtd_info *mtd, int mode);
-	void		(*erase_cmd)(struct mtd_info *mtd, int page);
-	int		(*scan_bbt)(struct mtd_info *mtd);
-	int		eccmode;
-	int		eccsize;
-	int		eccbytes;
-	int		eccsteps;
-	int 		chip_delay;
-#if 0
-	spinlock_t	chip_lock;
-	wait_queue_head_t wq;
-	nand_state_t 	state;
-#endif
-	int 		page_shift;
-	int		phys_erase_shift;
-	int		bbt_erase_shift;
-	int		chip_shift;
-	u_char 		*data_buf;
-	u_char		*oob_buf;
-	int		oobdirty;
-	u_char		*data_poi;
-	unsigned int	options;
-	int		badblockpos;
-	int		numchips;
-	unsigned long	chipsize;
-	int		pagemask;
-	int		pagebuf;
-	struct nand_oobinfo	*autooob;
-	uint8_t		*bbt;
-	struct nand_bbt_descr	*bbt_td;
-	struct nand_bbt_descr	*bbt_md;
-	struct nand_bbt_descr	*badblock_pattern;
-	struct nand_hw_control  *controller;
-	void		*priv;
-};
-
-/*
- * NAND Flash Manufacturer ID Codes
- */
-#define NAND_MFR_TOSHIBA	0x98
-#define NAND_MFR_SAMSUNG	0xec
-#define NAND_MFR_FUJITSU	0x04
-#define NAND_MFR_NATIONAL	0x8f
-#define NAND_MFR_RENESAS	0x07
-#define NAND_MFR_STMICRO	0x20
-
-/**
- * struct nand_flash_dev - NAND Flash Device ID Structure
- *
- * @name:  	Identify the device type
- * @id:   	device ID code
- * @pagesize:  	Pagesize in bytes. Either 256 or 512 or 0
- *		If the pagesize is 0, then the real pagesize
- *		and the eraseize are determined from the
- *		extended id bytes in the chip
- * @erasesize: 	Size of an erase block in the flash device.
- * @chipsize:  	Total chipsize in Mega Bytes
- * @options:	Bitfield to store chip relevant options
- */
-struct nand_flash_dev {
-	char *name;
-	int id;
-	unsigned long pagesize;
-	unsigned long chipsize;
-	unsigned long erasesize;
-	unsigned long options;
-};
-
-/**
- * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
- * @name:	Manufacturer name
- * @id: 	manufacturer ID code of device.
-*/
-struct nand_manufacturers {
-	int id;
-	char * name;
-};
-
-extern struct nand_flash_dev nand_flash_ids[];
-extern struct nand_manufacturers nand_manuf_ids[];
-
-/**
- * struct nand_bbt_descr - bad block table descriptor
- * @options:	options for this descriptor
- * @pages:	the page(s) where we find the bbt, used with option BBT_ABSPAGE
- *		when bbt is searched, then we store the found bbts pages here.
- *		Its an array and supports up to 8 chips now
- * @offs:	offset of the pattern in the oob area of the page
- * @veroffs:	offset of the bbt version counter in the oob are of the page
- * @version:	version read from the bbt page during scan
- * @len:	length of the pattern, if 0 no pattern check is performed
- * @maxblocks:	maximum number of blocks to search for a bbt. This number of
- *		blocks is reserved at the end of the device where the tables are
- *		written.
- * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
- *              bad) block in the stored bbt
- * @pattern:	pattern to identify bad block table or factory marked good /
- *		bad blocks, can be NULL, if len = 0
- *
- * Descriptor for the bad block table marker and the descriptor for the
- * pattern which identifies good and bad blocks. The assumption is made
- * that the pattern and the version count are always located in the oob area
- * of the first block.
- */
-struct nand_bbt_descr {
-	int	options;
-	int	pages[NAND_MAX_CHIPS];
-	int	offs;
-	int	veroffs;
-	uint8_t	version[NAND_MAX_CHIPS];
-	int	len;
-	int 	maxblocks;
-	int	reserved_block_code;
-	uint8_t	*pattern;
-};
-
-/* Options for the bad block table descriptors */
-
-/* The number of bits used per block in the bbt on the device */
-#define NAND_BBT_NRBITS_MSK	0x0000000F
-#define NAND_BBT_1BIT		0x00000001
-#define NAND_BBT_2BIT		0x00000002
-#define NAND_BBT_4BIT		0x00000004
-#define NAND_BBT_8BIT		0x00000008
-/* The bad block table is in the last good block of the device */
-#define	NAND_BBT_LASTBLOCK	0x00000010
-/* The bbt is at the given page, else we must scan for the bbt */
-#define NAND_BBT_ABSPAGE	0x00000020
-/* The bbt is at the given page, else we must scan for the bbt */
-#define NAND_BBT_SEARCH		0x00000040
-/* bbt is stored per chip on multichip devices */
-#define NAND_BBT_PERCHIP	0x00000080
-/* bbt has a version counter at offset veroffs */
-#define NAND_BBT_VERSION	0x00000100
-/* Create a bbt if none axists */
-#define NAND_BBT_CREATE		0x00000200
-/* Search good / bad pattern through all pages of a block */
-#define NAND_BBT_SCANALLPAGES	0x00000400
-/* Scan block empty during good / bad block scan */
-#define NAND_BBT_SCANEMPTY	0x00000800
-/* Write bbt if neccecary */
-#define NAND_BBT_WRITE		0x00001000
-/* Read and write back block contents when writing bbt */
-#define NAND_BBT_SAVECONTENT	0x00002000
-/* Search good / bad pattern on the first and the second page */
-#define NAND_BBT_SCAN2NDPAGE	0x00004000
-
-/* The maximum number of blocks to scan for a bbt */
-#define NAND_BBT_SCAN_MAXBLOCKS	4
-
-extern int nand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd);
-extern int nand_update_bbt (struct mtd_info *mtd, loff_t offs);
-extern int nand_default_bbt (struct mtd_info *mtd);
-extern int nand_isbad_bbt (struct mtd_info *mtd, loff_t offs, int allowbbt);
-extern int nand_erase_nand (struct mtd_info *mtd, struct erase_info *instr, int allowbbt);
-
-/*
-* Constants for oob configuration
-*/
-#define NAND_SMALL_BADBLOCK_POS		5
-#define NAND_LARGE_BADBLOCK_POS		0
-
-#endif /* __LINUX_MTD_NAND_NEW_H */