Add omapl137 support1.3.3-omapl137-evm-200906171409

23 files changed, 1562 insertions, 223 deletions

diff --git a/include/.gitignore b/include/.gitignore
index ef7dd5fc8a2..e69de29bb2d 100644
--- a/include/.gitignore
+++ b/include/.gitignore
@@ -1,8 +0,0 @@
-/autoconf.mk*
-/asm
-/asm-*/arch
-/asm-*/proc
-/bmp_logo.h
-/config.h
-/config.mk
-/version_autogenerated.h
diff --git a/include/asm-arm/arch-at91sam9/hardware.h b/include/asm-arm/arch-at91sam9/hardware.h
index d2fe45388b3..fba3908cbdb 100644
--- a/include/asm-arm/arch-at91sam9/hardware.h
+++ b/include/asm-arm/arch-at91sam9/hardware.h
@@ -42,15 +42,4 @@
 #error "Unsupported AT91 processor"
 #endif
 
-/*
- * container_of - cast a member of a structure out to the containing structure
- *
- * @ptr:	the pointer to the member.
- * @type:	the type of the container struct this is embedded in.
- * @member:	the name of the member within the struct.
- */
-#define container_of(ptr, type, member) ({			\
-	const typeof(((type *)0)->member) *__mptr = (ptr);	\
-	(type *)((char *)__mptr - offsetof(type, member)); })
-
 #endif
diff --git a/include/asm-arm/arch-da8xx/emac_defs.h b/include/asm-arm/arch-da8xx/emac_defs.h
new file mode 100644
index 00000000000..6120a595e36
--- /dev/null
+++ b/include/asm-arm/arch-da8xx/emac_defs.h
@@ -0,0 +1,331 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Based on:
+ *
+ * ----------------------------------------------------------------------------
+ *
+ * dm644x_emac.h
+ *
+ * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM
+ *
+ * Copyright (C) 2005 Texas Instruments.
+ *
+ * ----------------------------------------------------------------------------
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * ----------------------------------------------------------------------------
+
+ * Modifications:
+ * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot.
+ *
+ */
+
+#ifndef _DM644X_EMAC_H_
+#define _DM644X_EMAC_H_
+
+#include <asm/arch/hardware.h>
+
+#define EMAC_BASE_ADDR				DAVINCI_EMAC_CNTRL_REGS_BASE
+#define EMAC_WRAPPER_BASE_ADDR		DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE
+#define EMAC_WRAPPER_RAM_ADDR		DAVINCI_EMAC_WRAPPER_RAM_BASE
+#define EMAC_MDIO_BASE_ADDR			DAVINCI_MDIO_CNTRL_REGS_BASE
+
+/* MDIO module input frequency */
+#define EMAC_MDIO_BUS_FREQ			clk_get(DAVINCI_MDIO_CLKID)
+
+/* MDIO clock output frequency */
+#define EMAC_MDIO_CLOCK_FREQ		2000000		/* 2.0 MHz */
+
+/* Ethernet Min/Max packet size */
+#define EMAC_MIN_ETHERNET_PKT_SIZE	60
+#define EMAC_MAX_ETHERNET_PKT_SIZE	1518
+#define EMAC_PKT_ALIGN			18	/* 1518 + 18 = 1536 (packet aligned on 32 byte boundry) */
+
+/* Number of RX packet buffers
+ * NOTE: Only 1 buffer supported as of now
+ */
+#define EMAC_MAX_RX_BUFFERS		10
+
+
+/***********************************************
+ ******** Internally used macros ***************
+ ***********************************************/
+
+#define EMAC_CH_TX			1
+#define EMAC_CH_RX			0
+
+/* Each descriptor occupies 4 words, lets start RX desc's at 0 and
+ * reserve space for 64 descriptors max
+ */
+#define EMAC_RX_DESC_BASE		0x0
+#define EMAC_TX_DESC_BASE		0x1000
+
+/* EMAC Teardown value */
+#define EMAC_TEARDOWN_VALUE		0xfffffffc
+
+/* MII Status Register */
+#define MII_STATUS_REG			1
+
+/* Number of statistics registers */
+#define EMAC_NUM_STATS			36
+
+
+/* EMAC Descriptor */
+typedef volatile struct _emac_desc
+{
+	u_int32_t	next;		/* Pointer to next descriptor in chain */
+	u_int8_t	*buffer;	/* Pointer to data buffer */
+	u_int32_t	buff_off_len;	/* Buffer Offset(MSW) and Length(LSW) */
+	u_int32_t	pkt_flag_len;	/* Packet Flags(MSW) and Length(LSW) */
+} emac_desc;
+
+/* CPPI bit positions */
+#define EMAC_CPPI_SOP_BIT		(0x80000000)
+#define EMAC_CPPI_EOP_BIT		(0x40000000)
+#define EMAC_CPPI_OWNERSHIP_BIT		(0x20000000)
+#define EMAC_CPPI_EOQ_BIT		(0x10000000)
+#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT	(0x08000000)
+#define EMAC_CPPI_PASS_CRC_BIT		(0x04000000)
+
+#define EMAC_CPPI_RX_ERROR_FRAME	(0x03fc0000)
+
+#define EMAC_MACCONTROL_RMIISPEED_100		(1 << 15)
+#define EMAC_MACCONTROL_MIIEN_ENABLE		(0x20)
+#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE	(0x1)
+
+#define EMAC_RXMBPENABLE_RXCAFEN_ENABLE	(0x200000)
+#define EMAC_RXMBPENABLE_RXBROADEN	(0x2000)
+
+
+#define MDIO_CONTROL_IDLE		(0x80000000)
+#define MDIO_CONTROL_ENABLE		(0x40000000)
+#define MDIO_CONTROL_FAULT_ENABLE	(0x40000)
+#define MDIO_CONTROL_FAULT		(0x80000)
+#define MDIO_USERACCESS0_GO		(0x80000000)
+#define MDIO_USERACCESS0_WRITE_READ	(0x0)
+#define MDIO_USERACCESS0_WRITE_WRITE	(0x40000000)
+#define MDIO_USERACCESS0_ACK		(0x20000000)
+
+/* Ethernet MAC Registers Structure */
+typedef struct  {
+	dv_reg		TXIDVER;
+	dv_reg		TXCONTROL;
+	dv_reg		TXTEARDOWN;
+	u_int8_t	RSVD0[4];
+	dv_reg		RXIDVER;
+	dv_reg		RXCONTROL;
+	dv_reg		RXTEARDOWN;
+	u_int8_t	RSVD1[100];
+	dv_reg		TXINTSTATRAW;
+	dv_reg		TXINTSTATMASKED;
+	dv_reg		TXINTMASKSET;
+	dv_reg		TXINTMASKCLEAR;
+	dv_reg		MACINVECTOR;
+	u_int8_t	RSVD2[12];
+	dv_reg		RXINTSTATRAW;
+	dv_reg		RXINTSTATMASKED;
+	dv_reg		RXINTMASKSET;
+	dv_reg		RXINTMASKCLEAR;
+	dv_reg		MACINTSTATRAW;
+	dv_reg		MACINTSTATMASKED;
+	dv_reg		MACINTMASKSET;
+	dv_reg		MACINTMASKCLEAR;
+	u_int8_t	RSVD3[64];
+	dv_reg		RXMBPENABLE;
+	dv_reg		RXUNICASTSET;
+	dv_reg		RXUNICASTCLEAR;
+	dv_reg		RXMAXLEN;
+	dv_reg		RXBUFFEROFFSET;
+	dv_reg		RXFILTERLOWTHRESH;
+	u_int8_t	RSVD4[8];
+	dv_reg		RX0FLOWTHRESH;
+	dv_reg		RX1FLOWTHRESH;
+	dv_reg		RX2FLOWTHRESH;
+	dv_reg		RX3FLOWTHRESH;
+	dv_reg		RX4FLOWTHRESH;
+	dv_reg		RX5FLOWTHRESH;
+	dv_reg		RX6FLOWTHRESH;
+	dv_reg		RX7FLOWTHRESH;
+	dv_reg		RX0FREEBUFFER;
+	dv_reg		RX1FREEBUFFER;
+	dv_reg		RX2FREEBUFFER;
+	dv_reg		RX3FREEBUFFER;
+	dv_reg		RX4FREEBUFFER;
+	dv_reg		RX5FREEBUFFER;
+	dv_reg		RX6FREEBUFFER;
+	dv_reg		RX7FREEBUFFER;
+	dv_reg		MACCONTROL;
+	dv_reg		MACSTATUS;
+	dv_reg		EMCONTROL;
+	dv_reg		FIFOCONTROL;
+	dv_reg		MACCONFIG;
+	dv_reg		SOFTRESET;
+	u_int8_t	RSVD5[88];
+	dv_reg		MACSRCADDRLO;
+	dv_reg		MACSRCADDRHI;
+	dv_reg		MACHASH1;
+	dv_reg		MACHASH2;
+	dv_reg		BOFFTEST;
+	dv_reg		TPACETEST;
+	dv_reg		RXPAUSE;
+	dv_reg		TXPAUSE;
+	u_int8_t	RSVD6[16];
+	dv_reg		RXGOODFRAMES;
+	dv_reg		RXBCASTFRAMES;
+	dv_reg		RXMCASTFRAMES;
+	dv_reg		RXPAUSEFRAMES;
+	dv_reg		RXCRCERRORS;
+	dv_reg		RXALIGNCODEERRORS;
+	dv_reg		RXOVERSIZED;
+	dv_reg		RXJABBER;
+	dv_reg		RXUNDERSIZED;
+	dv_reg		RXFRAGMENTS;
+	dv_reg		RXFILTERED;
+	dv_reg		RXQOSFILTERED;
+	dv_reg		RXOCTETS;
+	dv_reg		TXGOODFRAMES;
+	dv_reg		TXBCASTFRAMES;
+	dv_reg		TXMCASTFRAMES;
+	dv_reg		TXPAUSEFRAMES;
+	dv_reg		TXDEFERRED;
+	dv_reg		TXCOLLISION;
+	dv_reg		TXSINGLECOLL;
+	dv_reg		TXMULTICOLL;
+	dv_reg		TXEXCESSIVECOLL;
+	dv_reg		TXLATECOLL;
+	dv_reg		TXUNDERRUN;
+	dv_reg		TXCARRIERSENSE;
+	dv_reg		TXOCTETS;
+	dv_reg		FRAME64;
+	dv_reg		FRAME65T127;
+	dv_reg		FRAME128T255;
+	dv_reg		FRAME256T511;
+	dv_reg		FRAME512T1023;
+	dv_reg		FRAME1024TUP;
+	dv_reg		NETOCTETS;
+	dv_reg		RXSOFOVERRUNS;
+	dv_reg		RXMOFOVERRUNS;
+	dv_reg		RXDMAOVERRUNS;
+	u_int8_t	RSVD7[624];
+	dv_reg		MACADDRLO;
+	dv_reg		MACADDRHI;
+	dv_reg		MACINDEX;
+	u_int8_t	RSVD8[244];
+	dv_reg		TX0HDP;
+	dv_reg		TX1HDP;
+	dv_reg		TX2HDP;
+	dv_reg		TX3HDP;
+	dv_reg		TX4HDP;
+	dv_reg		TX5HDP;
+	dv_reg		TX6HDP;
+	dv_reg		TX7HDP;
+	dv_reg		RX0HDP;
+	dv_reg		RX1HDP;
+	dv_reg		RX2HDP;
+	dv_reg		RX3HDP;
+	dv_reg		RX4HDP;
+	dv_reg		RX5HDP;
+	dv_reg		RX6HDP;
+	dv_reg		RX7HDP;
+	dv_reg		TX0CP;
+	dv_reg		TX1CP;
+	dv_reg		TX2CP;
+	dv_reg		TX3CP;
+	dv_reg		TX4CP;
+	dv_reg		TX5CP;
+	dv_reg		TX6CP;
+	dv_reg		TX7CP;
+	dv_reg		RX0CP;
+	dv_reg		RX1CP;
+	dv_reg		RX2CP;
+	dv_reg		RX3CP;
+	dv_reg		RX4CP;
+	dv_reg		RX5CP;
+	dv_reg		RX6CP;
+	dv_reg		RX7CP;
+} emac_regs;
+
+/* EMAC Wrapper Registers Structure */
+typedef struct  {
+	dv_reg	REV;
+	dv_reg	SOFTRESET;
+	dv_reg	INTCONTROL;
+	dv_reg	C0RXTHRESHEN;
+	dv_reg	C0RXEN;
+	dv_reg	C0TXEN;
+	dv_reg	C0MISCEN;
+	dv_reg	C1RXTHRESHEN;
+	dv_reg	C1RXEN;
+	dv_reg	C1TXEN;
+	dv_reg	C1MISCEN;
+	dv_reg	C2RXTHRESHEN;
+	dv_reg	C2RXEN;
+	dv_reg	C2TXEN;
+	dv_reg	C2MISCEN;
+	dv_reg	C0RXTHRESHSTAT;
+	dv_reg	C0RXSTAT;
+	dv_reg	C0TXSTAT;
+	dv_reg	C0MISCSTAT;
+	dv_reg	C1RXTHRESHSTAT;
+	dv_reg	C1RXSTAT;
+	dv_reg	C1TXSTAT;
+	dv_reg	C1MISCSTAT;
+	dv_reg	C2RXTHRESHSTAT;
+	dv_reg	C2RXSTAT;
+	dv_reg	C2TXSTAT;
+	dv_reg	C2MISCSTAT;
+	dv_reg  C0RXIMAX;
+	dv_reg  C0TXIMAX;
+	dv_reg  C1RXIMAX;
+	dv_reg  C1TXIMAX;
+	dv_reg  C2RXIMAX;
+	dv_reg  C2TXIMAX;
+} ewrap_regs;
+
+
+/* EMAC MDIO Registers Structure */
+typedef struct  {
+	dv_reg		VERSION;
+	dv_reg		CONTROL;
+	dv_reg		ALIVE;
+	dv_reg		LINK;
+	dv_reg		LINKINTRAW;
+	dv_reg		LINKINTMASKED;
+	u_int8_t	RSVD0[8];
+	dv_reg		USERINTRAW;
+	dv_reg		USERINTMASKED;
+	dv_reg		USERINTMASKSET;
+	dv_reg		USERINTMASKCLEAR;
+	u_int8_t	RSVD1[80];
+	dv_reg		USERACCESS0;
+	dv_reg		USERPHYSEL0;
+	dv_reg		USERACCESS1;
+	dv_reg		USERPHYSEL1;
+} mdio_regs;
+
+int dm644x_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data);
+int dm644x_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data);
+
+typedef struct
+{
+	char	name[64];
+	int	(*init)(int phy_addr);
+	int	(*is_phy_connected)(int phy_addr);
+	int	(*get_link_speed)(int phy_addr);
+	int	(*auto_negotiate)(int phy_addr);
+} phy_t;
+
+#endif  /* _DM644X_EMAC_H_ */
diff --git a/include/asm-arm/arch-da8xx/emif_defs.h b/include/asm-arm/arch-da8xx/emif_defs.h
new file mode 100644
index 00000000000..646fc774694
--- /dev/null
+++ b/include/asm-arm/arch-da8xx/emif_defs.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _EMIF_DEFS_H_
+#define _EMIF_DEFS_H_
+
+#include <asm/arch/hardware.h>
+
+typedef struct {
+	dv_reg		ERCSR;
+	dv_reg		AWCCR;
+	dv_reg		SDBCR;
+	dv_reg		SDRCR;
+	dv_reg		AB1CR;
+	dv_reg		AB2CR;
+	dv_reg		AB3CR;
+	dv_reg		AB4CR;
+	dv_reg		SDTIMR;
+	dv_reg		DDRSR;
+	dv_reg		DDRPHYCR;
+	dv_reg		DDRPHYSR;
+	dv_reg		TOTAR;
+	dv_reg		TOTACTR;
+	dv_reg		DDRPHYID_REV;
+	dv_reg		SDSRETR;
+	dv_reg		EIRR;
+	dv_reg		EIMR;
+	dv_reg		EIMSR;
+	dv_reg		EIMCR;
+	dv_reg		IOCTRLR;
+	dv_reg		IOSTATR;
+	u_int8_t	RSVD0[8];
+	dv_reg		NANDFCR;
+	dv_reg		NANDFSR;
+	u_int8_t	RSVD1[8];
+	dv_reg		NANDF1ECC;
+	dv_reg		NANDF2ECC;
+	dv_reg		NANDF3ECC;
+	dv_reg		NANDF4ECC;
+} emif_registers;
+
+typedef emif_registers	*emifregs;
+#endif
diff --git a/include/asm-arm/arch-da8xx/hardware.h b/include/asm-arm/arch-da8xx/hardware.h
new file mode 100644
index 00000000000..6791c3b21eb
--- /dev/null
+++ b/include/asm-arm/arch-da8xx/hardware.h
@@ -0,0 +1,207 @@
+/*
+ * Copyright (C) 2008 Sekhar Nori, Texas Instruments, Inc
+ *
+ * Based on hardware.h for DaVinci. Original Copyrights follow.
+ *
+ * Sergey Kubushyn <ksi@koi8.net>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Based on:
+ *
+ * -------------------------------------------------------------------------
+ *
+ *	linux/include/asm-arm/arch-davinci/hardware.h
+ *
+ *	Copyright (C) 2006 Texas Instruments.
+ *
+ *	This program is free software; you can redistribute  it and/or modify it
+ *	under  the terms of  the GNU General  Public License as published by the
+ *	Free Software Foundation;  either version 2 of the	License, or (at your
+ *	option) any later version.
+ *
+ *	THIS  SOFTWARE	IS PROVIDED   ``AS	IS'' AND   ANY	EXPRESS OR IMPLIED
+ *	WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *	MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *	NO	EVENT  SHALL   THE AUTHOR  BE	 LIABLE FOR ANY   DIRECT, INDIRECT,
+ *	INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *	NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS	OR SERVICES; LOSS OF
+ *	USE, DATA,	OR PROFITS; OR	BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *	ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *	(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *	THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *	You should have received a copy of the	GNU General Public License along
+ *	with this program; if not, write  to the Free Software Foundation, Inc.,
+ *	675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <config.h>
+
+#ifndef __ASSEMBLY__
+
+#include <asm/sizes.h>
+
+#define REG(addr)	(*(volatile unsigned int *)(addr))
+#define REG_P(addr) ((volatile unsigned int *)(addr))
+
+typedef volatile unsigned int	dv_reg;
+typedef volatile unsigned int * dv_reg_p;
+
+#endif
+
+/*
+ * Base register addresses
+ */
+#define DAVINCI_UART0_BASE			(0x01c42000)
+#define DAVINCI_UART1_BASE			(0x01d0c000)
+#define DAVINCI_UART2_BASE			(0x01d0d000)
+#define DAVINCI_I2C0_BASE			(0x01c22000)
+#define DAVINCI_I2C1_BASE			(0x01e28000)
+#define DAVINCI_TIMER0_BASE 		(0x01c20000)
+#define DAVINCI_TIMER1_BASE 		(0x01c21000)
+#define DAVINCI_WDOG_BASE			(0x01c21000)
+#define DAVINCI_PLL_CNTRL0_BASE 	(0x01c11000)
+#define DAVINCI_PSC0_BASE			(0x01c10000)
+#define DAVINCI_PSC1_BASE			(0x01e27000)
+#define DAVINCI_SPI0_BASE			(0x01c41000)
+#define DAVINCI_SPI1_BASE			(0x01e12000)
+#define DAVINCI_GPIO_BASE			(0x01e26000)
+#define DAVINCI_EMAC_CNTRL_REGS_BASE			(0x01e23000)
+#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE	(0x01e22000)
+#define DAVINCI_EMAC_WRAPPER_RAM_BASE			(0x01e20000)
+#define DAVINCI_MDIO_CNTRL_REGS_BASE			(0x01e24000)
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE		(0x68000000)
+#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE	(0x40000000)
+#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE	(0x60000000)
+#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE	(0x62000000)
+#define DAVINCI_ASYNC_EMIF_DATA_CE4_BASE	(0x64000000)
+#define DAVINCI_ASYNC_EMIF_DATA_CE5_BASE	(0x66000000)
+#define DAVINCI_DDR_EMIF_CTRL_BASE	(0xb0000000)
+#define DAVINCI_DDR_EMIF_DATA_BASE	(0xc0000000)
+#define DAVINCI_INTC_BASE			(0xfffee000)
+#define DAVINCI_BOOTCFG_BASE		(0x01c14000)
+
+/* Clock IDs */
+#define DAVINCI_PLLM_CLKID			(0xFF + 0)
+#define DAVINCI_PLLC_CLKID			(0xFF + 1)
+#define DAVINCI_AUXCLK_CLKID		(0xFF + 2)
+#define DAVINCI_MDIO_CLKID			4
+#define DAVINCI_SPI0_CLKID			2
+#define DAVINCI_UART2_CLKID 		2
+#define DAVINCI_ARM_CLKID		  6
+
+/* Power and Sleep Controller (PSC) Domains */
+#define DAVINCI_GPSC_ARMDOMAIN		0
+#define DAVINCI_GPSC_DSPDOMAIN		1
+
+/* LPSCs in PSC0 */
+#define DAVINCI_LPSC_TPCC		0
+#define DAVINCI_LPSC_TPTC0		1
+#define DAVINCI_LPSC_TPTC1		2
+#define DAVINCI_LPSC_AEMIF		3
+#define DAVINCI_LPSC_SPI0		4
+#define DAVINCI_LPSC_MMC_SD 	5
+#define DAVINCI_LPSC_AINTC		6
+#define DAVINCI_LPSC_ARM_RAM_ROM	7
+#define DAVINCI_LPSC_SECCTL_KEYMGR	8
+#define DAVINCI_LPSC_UART0		9
+#define DAVINCI_LPSC_SCR0		10
+#define DAVINCI_LPSC_SCR1		11
+#define DAVINCI_LPSC_SCR2		12
+#define DAVINCI_LPSC_DMAX		13
+#define DAVINCI_LPSC_ARM		14
+#define DAVINCI_LPSC_GEM		15
+
+/* for LPSCs in PSC1, 32 + actual id is being used for differentiation */
+#define DAVINCI_LPSC_USB11		(32 + 1)
+#define DAVINCI_LPSC_USB20		(32 + 2)
+#define DAVINCI_LPSC_GPIO		(32 + 3)
+#define DAVINCI_LPSC_UHPI		(32 + 4)
+#define DAVINCI_LPSC_EMAC		(32 + 5)
+#define DAVINCI_LPSC_DDR_EMIF	(32 + 6)
+#define DAVINCI_LPSC_McASP0 	(32 + 7)
+#define DAVINCI_LPSC_McASP1 	(32 + 8)
+#define DAVINCI_LPSC_McASP2 	(32 + 9)
+#define DAVINCI_LPSC_SPI1		(32 + 10)
+#define DAVINCI_LPSC_I2C1		(32 + 11)
+#define DAVINCI_LPSC_UART1		(32 + 12)
+#define DAVINCI_LPSC_UART2		(32 + 13)
+#define DAVINCI_LPSC_LCDC		(32 + 16)
+#define DAVINCI_LPSC_ePWM		(32 + 17)
+#define DAVINCI_LPSC_eCAP		(32 + 20)
+#define DAVINCI_LPSC_eQEP		(32 + 21)
+#define DAVINCI_LPSC_SCR_P0 	(32 + 22)
+#define DAVINCI_LPSC_SCR_P1 	(32 + 23)
+#define DAVINCI_LPSC_CR_P3		(32 + 26)
+#define DAVINCI_LPSC_L3_CBA_RAM   (32 + 31)
+
+/* Some PSC defines */
+
+#define PSC0_MDCTL			(DAVINCI_PSC0_BASE + 0xa00)
+#define PSC0_MDSTAT 		(DAVINCI_PSC0_BASE + 0x800)
+#define PSC0_PTCMD			(DAVINCI_PSC0_BASE + 0x120)
+#define PSC0_PTSTAT 		(DAVINCI_PSC0_BASE + 0x128)
+
+#define PSC1_MDCTL			(DAVINCI_PSC1_BASE + 0xa00)
+#define PSC1_MDSTAT 		(DAVINCI_PSC1_BASE + 0x800)
+#define PSC1_PTCMD			(DAVINCI_PSC1_BASE + 0x120)
+#define PSC1_PTSTAT 		(DAVINCI_PSC1_BASE + 0x128)
+
+/* Some PLL defines */
+#define PLL0_PLLCTL 		(DAVINCI_PLL_CNTRL0_BASE + 0x100)
+#define PLL0_PLLM			(DAVINCI_PLL_CNTRL0_BASE + 0x110)
+#define PLL0_PREDIV 		(DAVINCI_PLL_CNTRL0_BASE + 0x114)
+#define PLL0_POSTDIV		(DAVINCI_PLL_CNTRL0_BASE + 0x128)
+#define PLL0_DIV1			(DAVINCI_PLL_CNTRL0_BASE + 0x118)
+#define PLL0_DIV2			(DAVINCI_PLL_CNTRL0_BASE + 0x11c)
+#define PLL0_DIV3			(DAVINCI_PLL_CNTRL0_BASE + 0x120)
+#define PLL0_DIV4			(DAVINCI_PLL_CNTRL0_BASE + 0x160)
+#define PLL0_DIV5			(DAVINCI_PLL_CNTRL0_BASE + 0x164)
+#define PLL0_DIV6			(DAVINCI_PLL_CNTRL0_BASE + 0x168)
+#define PLL0_DIV7			(DAVINCI_PLL_CNTRL0_BASE + 0x16c)
+#define PLL0_DIV8			(DAVINCI_PLL_CNTRL0_BASE + 0x170)
+#define PLL0_DIV9			(DAVINCI_PLL_CNTRL0_BASE + 0x114)
+
+/* Boot config */
+#define KICK0				(DAVINCI_BOOTCFG_BASE + 0x38)
+#define KICK1				(DAVINCI_BOOTCFG_BASE + 0x3c)
+#define PINMUX0 			(DAVINCI_BOOTCFG_BASE + 0x120)
+#define PINMUX1 			(DAVINCI_BOOTCFG_BASE + 0x124)
+#define PINMUX2 			(DAVINCI_BOOTCFG_BASE + 0x128)
+#define PINMUX3 			(DAVINCI_BOOTCFG_BASE + 0x12c)
+#define PINMUX4 			(DAVINCI_BOOTCFG_BASE + 0x130)
+#define PINMUX5 			(DAVINCI_BOOTCFG_BASE + 0x134)
+#define PINMUX6 			(DAVINCI_BOOTCFG_BASE + 0x138)
+#define PINMUX7 			(DAVINCI_BOOTCFG_BASE + 0x13c)
+#define PINMUX8 			(DAVINCI_BOOTCFG_BASE + 0x140)
+#define PINMUX9 			(DAVINCI_BOOTCFG_BASE + 0x144)
+#define PINMUX10			(DAVINCI_BOOTCFG_BASE + 0x148)
+#define PINMUX11			(DAVINCI_BOOTCFG_BASE + 0x14c)
+#define PINMUX12			(DAVINCI_BOOTCFG_BASE + 0x150)
+#define PINMUX13			(DAVINCI_BOOTCFG_BASE + 0x154)
+#define PINMUX14			(DAVINCI_BOOTCFG_BASE + 0x158)
+#define PINMUX15			(DAVINCI_BOOTCFG_BASE + 0x15C)
+#define PINMUX16			(DAVINCI_BOOTCFG_BASE + 0x160)
+#define PINMUX17			(DAVINCI_BOOTCFG_BASE + 0x164)
+#define PINMUX18			(DAVINCI_BOOTCFG_BASE + 0x168)
+#define PINMUX19			(DAVINCI_BOOTCFG_BASE + 0x16c)
+#define SUSPSRC 			(DAVINCI_BOOTCFG_BASE + 0x170)
+#define CFGCHIP0			(DAVINCI_BOOTCFG_BASE + 0x17c)
+#define CFGCHIP2			(DAVINCI_BOOTCFG_BASE + 0x184)
+
+/* Interrupt controller */
+#define INTC_GLB_EN 		(DAVINCI_INTC_BASE + 0x10)
+#define INTC_HINT_EN		(DAVINCI_INTC_BASE + 0x1500)
+#define INTC_EN_CLR0		(DAVINCI_INTC_BASE + 0x380)
+
+/* GPIO */
+#define GPIO_BANK4_ADDR 			0x01E26000
+#define GPIO_BANK4_REG_DIR_ADDR 	( GPIO_BANK4_ADDR + 0x60 )
+#define GPIO_BANK4_REG_OPDATA_ADDR	( GPIO_BANK4_ADDR + 0x64 )
+#define GPIO_BANK4_REG_SET_ADDR 	( GPIO_BANK4_ADDR + 0x68 )
+#define GPIO_BANK4_REG_CLR_ADDR 	( GPIO_BANK4_ADDR + 0x6C )
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-da8xx/i2c_defs.h b/include/asm-arm/arch-da8xx/i2c_defs.h
new file mode 100644
index 00000000000..714211fca5e
--- /dev/null
+++ b/include/asm-arm/arch-da8xx/i2c_defs.h
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ *
+ * Some changes copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _DAVINCI_I2C_H_
+#define _DAVINCI_I2C_H_
+
+#define I2C_WRITE		0
+#define I2C_READ		1
+
+#define I2C_BASE		0x01c22000
+
+#define	I2C_OA			(I2C_BASE + 0x00)
+#define I2C_IE			(I2C_BASE + 0x04)
+#define I2C_STAT		(I2C_BASE + 0x08)
+#define I2C_SCLL		(I2C_BASE + 0x0c)
+#define I2C_SCLH		(I2C_BASE + 0x10)
+#define I2C_CNT			(I2C_BASE + 0x14)
+#define I2C_DRR			(I2C_BASE + 0x18)
+#define I2C_SA			(I2C_BASE + 0x1c)
+#define I2C_DXR			(I2C_BASE + 0x20)
+#define I2C_CON			(I2C_BASE + 0x24)
+#define I2C_IV			(I2C_BASE + 0x28)
+#define I2C_PSC			(I2C_BASE + 0x30)
+
+/* I2C masks */
+
+/* I2C Interrupt Enable Register (I2C_IE): */
+#define I2C_IE_SCD_IE	(1 << 5)	/* Stop condition detect interrupt enable */
+#define I2C_IE_XRDY_IE	(1 << 4)	/* Transmit data ready interrupt enable */
+#define I2C_IE_RRDY_IE	(1 << 3)	/* Receive data ready interrupt enable */
+#define I2C_IE_ARDY_IE	(1 << 2)	/* Register access ready interrupt enable */
+#define I2C_IE_NACK_IE	(1 << 1)	/* No acknowledgment interrupt enable */
+#define I2C_IE_AL_IE	(1 << 0)	/* Arbitration lost interrupt enable */
+
+/* I2C Status Register (I2C_STAT): */
+
+#define I2C_STAT_BB	(1 << 12)	/* Bus busy */
+#define I2C_STAT_ROVR	(1 << 11)	/* Receive overrun */
+#define I2C_STAT_XUDF	(1 << 10)	/* Transmit underflow */
+#define I2C_STAT_AAS	(1 << 9)	/* Address as slave */
+#define I2C_STAT_SCD	(1 << 5)	/* Stop condition detect */
+#define I2C_STAT_XRDY	(1 << 4)	/* Transmit data ready */
+#define I2C_STAT_RRDY	(1 << 3)	/* Receive data ready */
+#define I2C_STAT_ARDY	(1 << 2)	/* Register access ready */
+#define I2C_STAT_NACK	(1 << 1)	/* No acknowledgment interrupt enable */
+#define I2C_STAT_AL	(1 << 0)	/* Arbitration lost interrupt enable */
+
+
+/* I2C Interrupt Code Register (I2C_INTCODE): */
+
+#define I2C_INTCODE_MASK	7
+#define I2C_INTCODE_NONE	0
+#define I2C_INTCODE_AL		1	/* Arbitration lost */
+#define I2C_INTCODE_NAK		2	/* No acknowledgement/general call */
+#define I2C_INTCODE_ARDY	3	/* Register access ready */
+#define I2C_INTCODE_RRDY	4	/* Rcv data ready */
+#define I2C_INTCODE_XRDY	5	/* Xmit data ready */
+#define I2C_INTCODE_SCD		6	/* Stop condition detect */
+
+
+/* I2C Configuration Register (I2C_CON): */
+
+#define I2C_CON_EN	(1 << 5)	/* I2C module enable */
+#define I2C_CON_STB	(1 << 4)	/* Start byte mode (master mode only) */
+#define I2C_CON_MST	(1 << 10)	/* Master/slave mode */
+#define I2C_CON_TRX	(1 << 9)	/* Transmitter/receiver mode (master mode only) */
+#define I2C_CON_XA	(1 << 8)	/* Expand address */
+#define I2C_CON_STP	(1 << 11)	/* Stop condition (master mode only) */
+#define I2C_CON_STT	(1 << 13)	/* Start condition (master mode only) */
+#define I2C_CON_FREE	(1 << 14)	/* Free run on emulation */
+
+#define I2C_TIMEOUT	0xffff0000	/* Timeout mask for poll_i2c_irq() */
+
+#endif
diff --git a/include/asm-arm/arch-da8xx/nand_defs.h b/include/asm-arm/arch-da8xx/nand_defs.h
new file mode 100644
index 00000000000..5084bb7f34c
--- /dev/null
+++ b/include/asm-arm/arch-da8xx/nand_defs.h
@@ -0,0 +1,164 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Parts shamelesly stolen from Linux Kernel source tree.
+ *
+ * ------------------------------------------------------------
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _NAND_DEFS_H_
+#define _NAND_DEFS_H_
+
+#include <asm/arch/hardware.h>
+
+#define	MASK_CLE	0x10
+//#define	MASK_ALE	0x0a
+#define	MASK_ALE	0x08
+
+
+#define NAND_CE0CLE	((volatile u_int8_t *)(CFG_NAND_BASE + 0x10))
+//#define NAND_CE0ALE	((volatile u_int8_t *)(CFG_NAND_BASE + 0x0a))
+#define NAND_CE0ALE	((volatile u_int8_t *)(CFG_NAND_BASE + 0x08))
+#define NAND_CE0DATA	((volatile u_int8_t *)CFG_NAND_BASE)
+
+typedef struct  {
+	u_int32_t	NRCSR;
+	u_int32_t	AWCCR;
+	u_int8_t	RSVD0[8];
+	u_int32_t	AB1CR;
+	u_int32_t	AB2CR;
+	u_int32_t	AB3CR;
+	u_int32_t	AB4CR;
+	u_int8_t	RSVD1[32];
+	u_int32_t	NIRR;
+	u_int32_t	NIMR;
+	u_int32_t	NIMSR;
+	u_int32_t	NIMCR;
+	u_int8_t	RSVD2[16];
+	u_int32_t	NANDFCR;
+	u_int32_t	NANDFSR;
+	u_int8_t	RSVD3[8];
+	u_int32_t	NANDF1ECC;
+	u_int32_t	NANDF2ECC;
+	u_int32_t	NANDF3ECC;
+	u_int32_t	NANDF4ECC;
+	u_int8_t	RSVD4[4];
+	u_int32_t	IODFTECR;
+	u_int32_t	IODFTGCR;
+	u_int8_t	RSVD5[4];
+	u_int32_t	IODFTMRLR;
+	u_int32_t	IODFTMRMR;
+	u_int32_t	IODFTMRMSBR;
+	u_int8_t	RSVD6[20];
+	u_int32_t	MODRNR;
+	u_int8_t	RSVD7[76];
+	u_int32_t	CE0DATA;
+	u_int32_t	CE0ALE;
+	u_int32_t	CE0CLE;
+	u_int8_t	RSVD8[4];
+	u_int32_t	CE1DATA;
+	u_int32_t	CE1ALE;
+	u_int32_t	CE1CLE;
+	u_int8_t	RSVD9[4];
+	u_int32_t	CE2DATA;
+	u_int32_t	CE2ALE;
+	u_int32_t	CE2CLE;
+	u_int8_t	RSVD10[4];
+	u_int32_t	CE3DATA;
+	u_int32_t	CE3ALE;
+	u_int32_t	CE3CLE;
+} nand_registers;
+
+typedef volatile nand_registers	*nandregs;
+
+#define NAND_READ_START		0x00
+#define NAND_READ_END		0x30
+#define NAND_STATUS		0x70
+
+#ifdef CFG_NAND_HW_ECC
+#define NAND_Ecc_P1e		(1 << 0)
+#define NAND_Ecc_P2e		(1 << 1)
+#define NAND_Ecc_P4e		(1 << 2)
+#define NAND_Ecc_P8e		(1 << 3)
+#define NAND_Ecc_P16e		(1 << 4)
+#define NAND_Ecc_P32e		(1 << 5)
+#define NAND_Ecc_P64e		(1 << 6)
+#define NAND_Ecc_P128e		(1 << 7)
+#define NAND_Ecc_P256e		(1 << 8)
+#define NAND_Ecc_P512e		(1 << 9)
+#define NAND_Ecc_P1024e		(1 << 10)
+#define NAND_Ecc_P2048e		(1 << 11)
+
+#define NAND_Ecc_P1o		(1 << 16)
+#define NAND_Ecc_P2o		(1 << 17)
+#define NAND_Ecc_P4o		(1 << 18)
+#define NAND_Ecc_P8o		(1 << 19)
+#define NAND_Ecc_P16o		(1 << 20)
+#define NAND_Ecc_P32o		(1 << 21)
+#define NAND_Ecc_P64o		(1 << 22)
+#define NAND_Ecc_P128o		(1 << 23)
+#define NAND_Ecc_P256o		(1 << 24)
+#define NAND_Ecc_P512o		(1 << 25)
+#define NAND_Ecc_P1024o		(1 << 26)
+#define NAND_Ecc_P2048o		(1 << 27)
+
+#define TF(v)			(v ? 1 : 0)
+
+#define P2048e(a)		(TF(a & NAND_Ecc_P2048e) << 0)
+#define P2048o(a)		(TF(a & NAND_Ecc_P2048o) << 1)
+#define P1e(a)			(TF(a & NAND_Ecc_P1e) << 2)
+#define P1o(a)			(TF(a & NAND_Ecc_P1o) << 3)
+#define P2e(a)			(TF(a & NAND_Ecc_P2e) << 4)
+#define P2o(a)			(TF(a & NAND_Ecc_P2o) << 5)
+#define P4e(a)			(TF(a & NAND_Ecc_P4e) << 6)
+#define P4o(a)			(TF(a & NAND_Ecc_P4o) << 7)
+
+#define P8e(a)			(TF(a & NAND_Ecc_P8e) << 0)
+#define P8o(a)			(TF(a & NAND_Ecc_P8o) << 1)
+#define P16e(a)			(TF(a & NAND_Ecc_P16e) << 2)
+#define P16o(a)			(TF(a & NAND_Ecc_P16o) << 3)
+#define P32e(a)			(TF(a & NAND_Ecc_P32e) << 4)
+#define P32o(a)			(TF(a & NAND_Ecc_P32o) << 5)
+#define P64e(a)			(TF(a & NAND_Ecc_P64e) << 6)
+#define P64o(a)			(TF(a & NAND_Ecc_P64o) << 7)
+
+#define P128e(a)		(TF(a & NAND_Ecc_P128e) << 0)
+#define P128o(a)		(TF(a & NAND_Ecc_P128o) << 1)
+#define P256e(a)		(TF(a & NAND_Ecc_P256e) << 2)
+#define P256o(a)		(TF(a & NAND_Ecc_P256o) << 3)
+#define P512e(a)		(TF(a & NAND_Ecc_P512e) << 4)
+#define P512o(a)		(TF(a & NAND_Ecc_P512o) << 5)
+#define P1024e(a)		(TF(a & NAND_Ecc_P1024e) << 6)
+#define P1024o(a)		(TF(a & NAND_Ecc_P1024o) << 7)
+
+#define P8e_s(a)		(TF(a & NAND_Ecc_P8e) << 0)
+#define P8o_s(a)		(TF(a & NAND_Ecc_P8o) << 1)
+#define P16e_s(a)		(TF(a & NAND_Ecc_P16e) << 2)
+#define P16o_s(a)		(TF(a & NAND_Ecc_P16o) << 3)
+#define P1e_s(a)		(TF(a & NAND_Ecc_P1e) << 4)
+#define P1o_s(a)		(TF(a & NAND_Ecc_P1o) << 5)
+#define P2e_s(a)		(TF(a & NAND_Ecc_P2e) << 6)
+#define P2o_s(a)		(TF(a & NAND_Ecc_P2o) << 7)
+
+#define P4e_s(a)		(TF(a & NAND_Ecc_P4e) << 0)
+#define P4o_s(a)		(TF(a & NAND_Ecc_P4o) << 1)
+#endif
+
+#endif
diff --git a/include/asm-avr32/arch-at32ap700x/chip-features.h b/include/asm-avr32/arch-at32ap700x/chip-features.h
index 29b1fd663d0..c47107e2a64 100644
--- a/include/asm-avr32/arch-at32ap700x/chip-features.h
+++ b/include/asm-avr32/arch-at32ap700x/chip-features.h
@@ -25,6 +25,7 @@
 /* Currently, all the AP700x chips have these */
 #define AT32AP700x_CHIP_HAS_USART
 #define AT32AP700x_CHIP_HAS_MMCI
+#define AT32AP700x_CHIP_HAS_SPI
 
 /* Only AP7000 has ethernet interface */
 #ifdef CONFIG_AT32AP7000
diff --git a/include/asm-avr32/arch-at32ap700x/clk.h b/include/asm-avr32/arch-at32ap700x/clk.h
index 385319aac75..bd6f2e5c7bd 100644
--- a/include/asm-avr32/arch-at32ap700x/clk.h
+++ b/include/asm-avr32/arch-at32ap700x/clk.h
@@ -74,6 +74,12 @@ static inline unsigned long get_mci_clk_rate(void)
 	return get_pbb_clk_rate();
 }
 #endif
+#ifdef AT32AP700x_CHIP_HAS_SPI
+static inline unsigned long get_spi_clk_rate(unsigned int dev_id)
+{
+	return get_pba_clk_rate();
+}
+#endif
 
 /* Board code may need the SDRAM base clock as a compile-time constant */
 #define SDRAMC_BUS_HZ	(MAIN_CLK_RATE >> CFG_CLKDIV_HSB)
diff --git a/include/asm-avr32/arch-at32ap700x/gpio.h b/include/asm-avr32/arch-at32ap700x/gpio.h
index b10a3e4f868..ef20ceaab7c 100644
--- a/include/asm-avr32/arch-at32ap700x/gpio.h
+++ b/include/asm-avr32/arch-at32ap700x/gpio.h
@@ -216,5 +216,9 @@ void gpio_enable_macb1(void);
 #ifdef AT32AP700x_CHIP_HAS_MMCI
 void gpio_enable_mmci(void);
 #endif
+#ifdef AT32AP700x_CHIP_HAS_SPI
+void gpio_enable_spi0(unsigned long cs_mask);
+void gpio_enable_spi1(unsigned long cs_mask);
+#endif
 
 #endif /* __ASM_AVR32_ARCH_GPIO_H__ */
diff --git a/include/asm-avr32/u-boot.h b/include/asm-avr32/u-boot.h
index 71dfcaf2840..85ef008b727 100644
--- a/include/asm-avr32/u-boot.h
+++ b/include/asm-avr32/u-boot.h
@@ -42,15 +42,4 @@ typedef struct bd_info {
 #define bi_memstart bi_dram[0].start
 #define bi_memsize bi_dram[0].size
 
-/**
- *  container_of - cast a member of a structure out to the containing structure
- *
- *    @ptr:        the pointer to the member.
- *    @type:       the type of the container struct this is embedded in.
- *    @member:     the name of the member within the struct.
- */
-#define container_of(ptr, type, member) ({                      \
-	const typeof( ((type *)0)->member ) *__mptr = (ptr);    \
-	(type *)( (char *)__mptr - offsetof(type,member) );})
-
 #endif /* __ASM_U_BOOT_H__ */
diff --git a/include/common.h b/include/common.h
index d0f57040ee4..bfd18fe8961 100644
--- a/include/common.h
+++ b/include/common.h
@@ -106,6 +106,9 @@ typedef volatile unsigned char	vu_char;
 #ifdef CONFIG_BLACKFIN
 #include <asm/blackfin.h>
 #endif
+#ifdef CONFIG_DA8XX
+#include <asm/arch/hardware.h>
+#endif
 
 #include <part.h>
 #include <flash.h>
@@ -176,6 +179,17 @@ typedef void (interrupt_handler_t)(void *);
 		(__x > __y) ? __x : __y; })
 
 
+/**
+ * container_of - cast a member of a structure out to the containing structure
+ * @ptr:	the pointer to the member.
+ * @type:	the type of the container struct this is embedded in.
+ * @member:	the name of the member within the struct.
+ *
+ */
+#define container_of(ptr, type, member) ({			\
+	const typeof( ((type *)0)->member ) *__mptr = (ptr);	\
+	(type *)( (char *)__mptr - offsetof(type,member) );})
+
 /*
  * Function Prototypes
  */
diff --git a/include/configs/da8xx_evm.h b/include/configs/da8xx_evm.h
new file mode 100644
index 00000000000..f093710a220
--- /dev/null
+++ b/include/configs/da8xx_evm.h
@@ -0,0 +1,232 @@
+/*
+ * Copyright (C) 2008 Texas Instruments, Inc <www.ti.com>
+ *
+ * Based on davinci_dvevm.h. Original Copyrights follow:
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/sizes.h>
+
+/*=======*/
+/* Board */
+/*=======*/
+#define  CFG_USE_SPIFLASH
+
+/*===================*/
+/* SoC Configuration */
+/*===================*/
+#define CONFIG_ARM926EJS				/* arm926ejs CPU core */
+#define CONFIG_DA8XX					/* TI DA8xx SoC */
+#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)	/* Arm Clock */
+#define CFG_OSCIN_FREQ		24000000
+#define CFG_TIMERBASE		DAVINCI_TIMER0_BASE /* use timer 0 */
+#define CFG_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID) /* Timer Input clock freq */
+#define CFG_HZ				1000
+#undef CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is _always_ loaded by a bootloader */
+#define CONFIG_SKIP_RELOCATE_UBOOT	/* to a proper address, init done */
+
+/*=============*/
+/* Memory Info */
+/*=============*/
+#define CFG_MALLOC_LEN		(0x10000 + 1*1024*1024)	/* malloc() len */
+#define CFG_GBL_DATA_SIZE	128 	/* reserved for initial data */
+#define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE	/* DDR Start */
+#define PHYS_SDRAM_1_SIZE	0x04000000	/* SDRAM size 64MB */
+#define CFG_MEMTEST_START	PHYS_SDRAM_1	/* memtest start address */
+#define CFG_MEMTEST_END 	(PHYS_SDRAM_1 + 16*1024*1024)	/* 16MB RAM test */
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE	(256*1024)	/* regular stack */
+#define SDRAM_4BANKS_10COLS 			/* TODO: Update this! */
+
+/*====================*/
+/* Serial Driver info */
+/*====================*/
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	4		/* NS16550 register size */
+#define CFG_NS16550_COM1	DAVINCI_UART2_BASE	/* Base address of UART2 */
+#define CFG_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) /* Input clock to NS16550 */
+#define CONFIG_CONS_INDEX	1			/* use UART0 for console */
+#define CONFIG_BAUDRATE 	115200		/* Default baud rate */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*===================*/
+/* I2C Configuration */
+/*===================*/
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CFG_I2C_SPEED			25000	/* 100Kbps won't work, silicon bug */
+#define CFG_I2C_SLAVE			10		/* Bogus, master-only in U-Boot */
+
+/*====================================================*/
+/* I2C EEPROM definitions for catalyst 24W256 EEPROM chip */
+/*====================================================*/
+#define CFG_I2C_EEPROM_ADDR_LEN 	2
+#define CFG_I2C_EEPROM_ADDR 	0x50
+#define CFG_EEPROM_PAGE_WRITE_BITS	6
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20
+
+/*==================================*/
+/* Network & Ethernet Configuration */
+/*==================================*/
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT	10
+
+/*=====================*/
+/* Flash & Environment */
+/*=====================*/
+#ifdef CFG_USE_NAND
+#undef CFG_ENV_IS_IN_FLASH
+#define CFG_NO_FLASH
+#define CFG_ENV_IS_IN_NAND		/* U-Boot env in NAND Flash  */
+#define CFG_ENV_SIZE		SZ_128K
+#define CFG_NAND_1BIT_ECC
+#define CFG_NAND_CS 	3
+#define CFG_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
+#define CFG_CLE_MASK		0x10
+#define CFG_ALE_MASK		0x8
+#define CFG_NAND_HW_ECC
+#define CFG_MAX_NAND_DEVICE 1	/* Max number of NAND devices */
+#define NAND_MAX_CHIPS		1
+#define CFG_ENV_OFFSET		0x0 /* Block 0--not used by bootcode */
+#define DEF_BOOTM		""
+#endif
+
+#ifdef CFG_USE_NOR
+#define CFG_ENV_IS_IN_FLASH
+#undef CFG_NO_FLASH
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_MAX_FLASH_BANKS 1		/* max number of flash banks */
+#define CFG_FLASH_SECT_SZ	0x10000 	/* 64KB sect size AMD Flash */
+#define CFG_ENV_OFFSET		(CFG_FLASH_SECT_SZ*3)
+#define CFG_FLASH_BASE		DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
+#define PHYS_FLASH_SIZE 	0x2000000	/* Flash size 32MB	 */
+#define CFG_MAX_FLASH_SECT	(PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ)
+#define CFG_ENV_SECT_SIZE	CFG_FLASH_SECT_SZ	/* Env sector Size */
+#define CFG_FLASH_SPL_ACCESS
+#endif
+
+#ifdef CFG_USE_SPIFLASH
+#undef CFG_ENV_IS_IN_FLASH
+#undef CFG_ENV_IS_IN_NAND
+#define CFG_ENV_IS_IN_SPI_FLASH
+#define CFG_ENV_SIZE		SZ_16K
+#define CFG_ENV_OFFSET		SZ_256K
+#define CFG_NO_FLASH
+#define CONFIG_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_DAVINCI_SPI
+#define CFG_SPI_BASE DAVINCI_SPI0_BASE
+#define CFG_SPI_CLK clk_get(DAVINCI_SPI0_CLKID)
+#define CONFIG_SF_DEFAULT_SPEED 50000000
+#define CFG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+#endif
+
+
+/*==============================*/
+/* U-Boot general configuration */
+/*==============================*/
+#undef	CONFIG_USE_IRQ			/* No IRQ/FIQ in U-Boot */
+#define CONFIG_MISC_INIT_R
+#undef CONFIG_BOOTDELAY
+#define CONFIG_BOOTFILE 	"uImage"	/* Boot file name */
+#define CFG_PROMPT		"U-Boot > " /* Monitor Command Prompt */
+#define CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print buffer sz */
+#define CFG_MAXARGS 	16		/* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_LOAD_ADDR		(CFG_MEMTEST_START + 0x700000)	/* default Linux kernel load address */
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE		/* Won't work with hush so far, may be later */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_CMDLINE_EDITING
+#define CFG_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+#define CONFIG_MUSB 		   /* Enable Mentor USB support */
+#define CONFIG_USB_DA8XX
+#define CONFIG_USB_STORAGE
+#define CONFIG_USE_PINMUX
+
+/*===================*/
+/* Linux Information */
+/*===================*/
+#define LINUX_BOOT_PARAM_ADDR	(CFG_MEMTEST_START + 0x100)
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTARGS 	"mem=32M console=ttyS2,115200n8 root=/dev/mtdblock/2 rw noinitrd ip=dhcp"
+#define CONFIG_BOOTCOMMAND	""
+#define CONFIG_BOOTDELAY    3
+
+/*=================*/
+/* U-Boot commands */
+/*=================*/
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_MEMORY
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#define CONFIG_CMD_EEPROM
+
+#ifdef CFG_USE_NAND
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+#endif
+
+#ifdef CFG_USE_SPIFLASH
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_FLASH
+#define CONFIG_CMD_SF
+#endif
+
+#if !defined(CFG_USE_NAND) && !defined(CFG_USE_NOR) && !defined(CFG_USE_SPIFLASH)
+#define CFG_ENV_IS_NOWHERE
+#define CFG_NO_FLASH
+#define CFG_ENV_SIZE		SZ_16K
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_ENV
+#endif
+
+#ifdef CONFIG_USB_DA8XX
+#define CONFIG_CMD_USB		/* inclue support for usb	*/
+#define CONFIG_CMD_STORAGE		/* inclue support for usb	*/
+#define CONFIG_CMD_FAT	  /* inclue support for FAT/storage*/
+#define CONFIG_DOS_PARTITION	/* inclue support for FAT/storage*/
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h
index 4281d73c90b..ec4ed1eeb67 100644
--- a/include/configs/imx31_litekit.h
+++ b/include/configs/imx31_litekit.h
@@ -65,7 +65,8 @@
 
 #define CONFIG_HARD_SPI		1
 #define CONFIG_MXC_SPI		1
-#define CONFIG_MXC_SPI_IFACE	1
+#define CONFIG_DEFAULT_SPI_BUS	1
+#define CONFIG_DEFAULT_SPI_MODE	(SPI_MODE_2 | SPI_CS_HIGH)
 
 #define CONFIG_RTC_MC13783	1
 
diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h
index 2ea48a6da9a..37ba872a439 100644
--- a/include/configs/mx31ads.h
+++ b/include/configs/mx31ads.h
@@ -62,7 +62,8 @@
 
 #define CONFIG_HARD_SPI		1
 #define CONFIG_MXC_SPI		1
-#define CONFIG_MXC_SPI_IFACE	1	/* Default SPI interface number */
+#define CONFIG_DEFAULT_SPI_BUS	1
+#define CONFIG_DEFAULT_SPI_MODE	(SPI_MODE_2 | SPI_CS_HIGH)
 
 #define CONFIG_RTC_MC13783	1
 
diff --git a/include/flash.h b/include/flash.h
index 2ed1e20fd22..bd92e59ef54 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -26,7 +26,7 @@
 
 #ifndef CFG_NO_FLASH
 /*-----------------------------------------------------------------------
- * FLASH Info: contains chip specific data, per FLASH bank
+ * FLASH Info: contains chip/board specific data, per FLASH bank
  */
 
 typedef struct {
@@ -56,8 +56,21 @@ typedef struct {
 	ulong   addr_unlock2;		/* unlock address 2 for AMD flash roms  */
 	const char *name;		/* human-readable name 	                */
 #endif
+	
+	/* board specific write routines */
+	void (*write8)(u8 value, void *addr);
+	void (*write16)(u16 value, void *addr);
+	void (*write32)(u32 value, void *addr);
+	void (*write64)(u64 value, void *addr);
+
+	/* board specific read routines */	
+	u8 (*read8)(void *addr);
+	u16 (*read16)(void *addr);
+	u32 (*read32)(void *addr);
+	u64 (*read64)(void *addr);
 } flash_info_t;
 
+
 /*
  * Values for the width of the port
  */
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 4cc4a7d1bb4..79d670d349d 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -109,6 +109,26 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_
 /* Extended commands for large page devices */
 #define NAND_CMD_READSTART	0x30
 #define NAND_CMD_CACHEDPROG	0x15
+/* Extended commands for AG-AND device */
+/* 
+ * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but 
+ *       there is no way to distinguish that from NAND_CMD_READ0
+ *       until the remaining sequence of commands has been completed
+ *       so add a high order bit and mask it off in the command.
+ */
+#define NAND_CMD_DEPLETE1	0x100
+#define NAND_CMD_DEPLETE2	0x38
+#define NAND_CMD_STATUS_MULTI	0x71
+#define NAND_CMD_STATUS_ERROR	0x72
+/* multi-bank error status (banks 0-3) */
+#define NAND_CMD_STATUS_ERROR0	0x73
+#define NAND_CMD_STATUS_ERROR1	0x74
+#define NAND_CMD_STATUS_ERROR2	0x75
+#define NAND_CMD_STATUS_ERROR3	0x76
+#define NAND_CMD_STATUS_RESET	0x7f
+#define NAND_CMD_STATUS_CLEAR	0xff
+
+
 
 /* Status bits */
 #define NAND_STATUS_FAIL	0x01
@@ -135,6 +155,18 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_
 #define NAND_ECC_HW8_512	6
 /* Hardware ECC 12 byte ECC per 2048 Byte data */
 #define NAND_ECC_HW12_2048	7
+/* Hardware ECC 10 byte ECC per 512 Byte data */
+#define NAND_ECC_HW10_512	8
+
+struct page_layout_item {
+	int length;
+	enum {
+		ITEM_TYPE_DATA, 
+		ITEM_TYPE_OOB, 
+		ITEM_TYPE_ECC,
+	} type;
+}; 
+
 
 /*
  * Constants for Hardware ECC
@@ -145,6 +177,14 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_
 #define NAND_ECC_WRITE		1
 /* Enable Hardware ECC before syndrom is read back from flash */
 #define NAND_ECC_READSYN	2
+#define NAND_ECC_WRITESYN	3
+#define NAND_ECC_READOOB	4
+#define NAND_ECC_WRITEOOB	5
+
+/* Bit mask for flags passed to do_nand_read_ecc */
+#define NAND_GET_DEVICE		0x80
+
+
 
 /* Option constants for bizarre disfunctionality and real
 *  features
@@ -165,6 +205,10 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_
 /* Chip has a array of 4 pages which can be read without
  * additional ready /busy waits */
 #define NAND_4PAGE_ARRAY	0x00000040
+/* Chip requires that BBT is periodically rewritten to prevent
+ * bits from adjacent blocks from 'leaking' in altering data.
+ * This happens with the Renesas AG-AND chips, possibly others.  */
+#define BBT_AUTO_REFRESH	0x00000080
 
 /* Options valid for Samsung large page devices */
 #define NAND_SAMSUNG_LP_OPTIONS \
@@ -187,6 +231,12 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_
  * This can only work if we have the ecc bytes directly behind the
  * data bytes. Applies for DOC and AG-AND Renesas HW Reed Solomon generators */
 #define NAND_HWECC_SYNDROME	0x00020000
+/* This option skips the bbt scan during initialization. */
+#define NAND_SKIP_BBTSCAN	0x00040000
+/* This option specifies that a whole NAND page is to be written in
+ * nand_write_oob. This is needed for some HW ECC generators that need a
+ * whole page to be written to generate ECC properly */
+#define NAND_COMPLEX_OOB_WRITE	0x00080000
 
 
 /* Options set by nand scan */
@@ -207,6 +257,7 @@ typedef enum {
 	FL_ERASING,
 	FL_SYNCING,
 	FL_CACHEDPRG,
+        FL_PM_SUSPENDED,
 } nand_state_t;
 
 /* Keep gcc happy */
@@ -331,12 +382,16 @@ struct nand_chip {
 	int		pagemask;
 	int		pagebuf;
 	struct nand_oobinfo	*autooob;
+	struct page_layout_item *layout;
+	int		layout_allocated;
 	uint8_t		*bbt;
 	struct nand_bbt_descr	*bbt_td;
 	struct nand_bbt_descr	*bbt_md;
 	struct nand_bbt_descr	*badblock_pattern;
 	struct nand_hw_control	*controller;
 	void		*priv;
+	int		(*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page);
+
 };
 
 /*
@@ -348,6 +403,7 @@ struct nand_chip {
 #define NAND_MFR_NATIONAL	0x8f
 #define NAND_MFR_RENESAS	0x07
 #define NAND_MFR_STMICRO	0x20
+#define NAND_MFR_HYNIX          0xad
 #define NAND_MFR_MICRON		0x2c
 
 /**
@@ -459,6 +515,10 @@ extern int nand_update_bbt (struct mtd_info *mtd, loff_t offs);
 extern int nand_default_bbt (struct mtd_info *mtd);
 extern int nand_isbad_bbt (struct mtd_info *mtd, loff_t offs, int allowbbt);
 extern int nand_erase_nand (struct mtd_info *mtd, struct erase_info *instr, int allowbbt);
+extern int nand_do_read_ecc (struct mtd_info *mtd, loff_t from, size_t len,
+                             size_t * retlen, u_char * buf, u_char * oob_buf,
+                             struct nand_oobinfo *oobsel, int flags);
+
 
 /*
 * Constants for oob configuration
diff --git a/include/linux/mtd/nand_ids.h b/include/linux/mtd/nand_ids.h
index d9eb9118280..5c58fce5051 100644
--- a/include/linux/mtd/nand_ids.h
+++ b/include/linux/mtd/nand_ids.h
@@ -53,6 +53,7 @@ static struct nand_flash_dev nand_flash_ids[] = {
 	{"Samsung KM29W16000",    NAND_MFR_SAMSUNG, 0xea, 21, 1, 2, 0x1000, 0},
 	{"Samsung K9F5616Q0C",    NAND_MFR_SAMSUNG, 0x45, 25, 0, 2, 0x4000, 1},
 	{"Samsung K9K1216Q0C",    NAND_MFR_SAMSUNG, 0x46, 26, 0, 3, 0x4000, 1},
+	{"Samsung K9K1208Q0C",    NAND_MFR_SAMSUNG, 0x36, 26, 0, 3, 0x4000, 0},
 	{"Samsung K9F1G08U0M",    NAND_MFR_SAMSUNG, 0xf1, 27, 0, 2, 0, 0},
 	{NULL,}
 };
diff --git a/include/nand.h b/include/nand.h
index 247d3465dbb..3c0752ea12a 100644
--- a/include/nand.h
+++ b/include/nand.h
@@ -34,22 +34,22 @@ extern int nand_curr_device;
 extern nand_info_t nand_info[];
 extern void nand_init(void);
 
-static inline int nand_read(nand_info_t *info, off_t ofs, size_t *len, u_char *buf)
+static inline int nand_read(nand_info_t *info, ulong ofs, ulong *len, u_char *buf)
 {
 	return info->read(info, ofs, *len, (size_t *)len, buf);
 }
 
-static inline int nand_write(nand_info_t *info, off_t ofs, size_t *len, u_char *buf)
+static inline int nand_write(nand_info_t *info, ulong ofs, ulong *len, u_char *buf)
 {
 	return info->write(info, ofs, *len, (size_t *)len, buf);
 }
 
-static inline int nand_block_isbad(nand_info_t *info, off_t ofs)
+static inline int nand_block_isbad(nand_info_t *info, ulong ofs)
 {
 	return info->block_isbad(info, ofs);
 }
 
-static inline int nand_erase(nand_info_t *info, off_t off, size_t size)
+static inline int nand_erase(nand_info_t *info, ulong off, ulong size)
 {
 	struct erase_info instr;
 
diff --git a/include/spi.h b/include/spi.h
index 3a55a68c4d1..7744c2e36b0 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -31,22 +31,87 @@
 #define	SPI_MODE_1	(0|SPI_CPHA)
 #define	SPI_MODE_2	(SPI_CPOL|0)
 #define	SPI_MODE_3	(SPI_CPOL|SPI_CPHA)
-#define	SPI_CS_HIGH	0x04			/* chipselect active high? */
+#define	SPI_CS_HIGH	0x04			/* CS active high */
 #define	SPI_LSB_FIRST	0x08			/* per-word bits-on-wire */
 #define	SPI_3WIRE	0x10			/* SI/SO signals shared */
 #define	SPI_LOOP	0x20			/* loopback mode */
 
-/*
- * The function call pointer type used to drive the chip select.
- */
-typedef void (*spi_chipsel_type)(int cs);
+/* SPI transfer flags */
+#define SPI_XFER_BEGIN	0x01			/* Assert CS before transfer */
+#define SPI_XFER_END	0x02			/* Deassert CS after transfer */
 
+/*-----------------------------------------------------------------------
+ * Representation of a SPI slave, i.e. what we're communicating with.
+ *
+ * Drivers are expected to extend this with controller-specific data.
+ *
+ *   bus:	ID of the bus that the slave is attached to.
+ *   cs:	ID of the chip select connected to the slave.
+ */
+struct spi_slave {
+	unsigned int	bus;
+	unsigned int	cs;
+};
 
 /*-----------------------------------------------------------------------
  * Initialization, must be called once on start up.
+ *
+ * TODO: I don't think we really need this.
  */
 void spi_init(void);
 
+/*-----------------------------------------------------------------------
+ * Set up communications parameters for a SPI slave.
+ *
+ * This must be called once for each slave. Note that this function
+ * usually doesn't touch any actual hardware, it only initializes the
+ * contents of spi_slave so that the hardware can be easily
+ * initialized later.
+ *
+ *   bus:     Bus ID of the slave chip.
+ *   cs:      Chip select ID of the slave chip on the specified bus.
+ *   max_hz:  Maximum SCK rate in Hz.
+ *   mode:    Clock polarity, clock phase and other parameters.
+ *
+ * Returns: A spi_slave reference that can be used in subsequent SPI
+ * calls, or NULL if one or more of the parameters are not supported.
+ */
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+		unsigned int max_hz, unsigned int mode);
+
+/*-----------------------------------------------------------------------
+ * Free any memory associated with a SPI slave.
+ *
+ *   slave:	The SPI slave
+ */
+void spi_free_slave(struct spi_slave *slave);
+
+/*-----------------------------------------------------------------------
+ * Claim the bus and prepare it for communication with a given slave.
+ *
+ * This must be called before doing any transfers with a SPI slave. It
+ * will enable and initialize any SPI hardware as necessary, and make
+ * sure that the SCK line is in the correct idle state. It is not
+ * allowed to claim the same bus for several slaves without releasing
+ * the bus in between.
+ *
+ *   slave:	The SPI slave
+ *
+ * Returns: 0 if the bus was claimed successfully, or a negative value
+ * if it wasn't.
+ */
+int spi_claim_bus(struct spi_slave *slave);
+
+/*-----------------------------------------------------------------------
+ * Release the SPI bus
+ *
+ * This must be called once for every call to spi_claim_bus() after
+ * all transfers have finished. It may disable any SPI hardware as
+ * appropriate.
+ *
+ *   slave:	The SPI slave
+ */
+void spi_release_bus(struct spi_slave *slave);
 
 /*-----------------------------------------------------------------------
  * SPI transfer
@@ -60,28 +125,67 @@ void spi_init(void);
  * input data overwrites the output data (since both are buffered by
  * temporary variables, this is OK).
  *
- * If the chipsel() function is not NULL, it is called with a parameter
- * of '1' (chip select active) at the start of the transfer and again with
- * a parameter of '0' at the end of the transfer.
- *
- * If the chipsel() function _is_ NULL, it the responsibility of the
- * caller to make the appropriate chip select active before calling
- * spi_xfer() and making it inactive after spi_xfer() returns.
- *
  * spi_xfer() interface:
- *   chipsel: Routine to call to set/clear the chip select:
- *              if chipsel is NULL, it is not used.
- *              if(cs),  make the chip select active (typically '0').
- *              if(!cs), make the chip select inactive (typically '1').
- *   dout:    Pointer to a string of bits to send out.  The bits are
- *              held in a byte array and are sent MSB first.
- *   din:     Pointer to a string of bits that will be filled in.
- *   bitlen:  How many bits to write and read.
+ *   slave:	The SPI slave which will be sending/receiving the data.
+ *   bitlen:	How many bits to write and read.
+ *   dout:	Pointer to a string of bits to send out.  The bits are
+ *		held in a byte array and are sent MSB first.
+ *   din:	Pointer to a string of bits that will be filled in.
+ *   flags:	A bitwise combination of SPI_XFER_* flags.
  *
  *   Returns: 0 on success, not 0 on failure
  */
-int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din);
+int  spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+		void *din, unsigned long flags);
+
+/*-----------------------------------------------------------------------
+ * Determine if a SPI chipselect is valid.
+ * This function is provided by the board if the low-level SPI driver
+ * needs it to determine if a given chipselect is actually valid.
+ *
+ * Returns: 1 if bus:cs identifies a valid chip on this board, 0
+ * otherwise.
+ */
+int  spi_cs_is_valid(unsigned int bus, unsigned int cs);
+
+/*-----------------------------------------------------------------------
+ * Activate a SPI chipselect.
+ * This function is provided by the board code when using a driver
+ * that can't control its chipselects automatically (e.g.
+ * common/soft_spi.c). When called, it should activate the chip select
+ * to the device identified by "slave".
+ */
+void spi_cs_activate(struct spi_slave *slave);
+
+/*-----------------------------------------------------------------------
+ * Deactivate a SPI chipselect.
+ * This function is provided by the board code when using a driver
+ * that can't control its chipselects automatically (e.g.
+ * common/soft_spi.c). When called, it should deactivate the chip
+ * select to the device identified by "slave".
+ */
+void spi_cs_deactivate(struct spi_slave *slave);
+
+/*-----------------------------------------------------------------------
+ * Write 8 bits, then read 8 bits.
+ *   slave:	The SPI slave we're communicating with
+ *   byte:	Byte to be written
+ *
+ * Returns: The value that was read, or a negative value on error.
+ *
+ * TODO: This function probably shouldn't be inlined.
+ */
+static inline int spi_w8r8(struct spi_slave *slave, unsigned char byte)
+{
+	unsigned char dout[2];
+	unsigned char din[2];
+	int ret;
+
+	dout[0] = byte;
+	dout[1] = 0;
 
-int spi_select(unsigned int bus, unsigned int dev, unsigned long mode);
+	ret = spi_xfer(slave, 16, dout, din, SPI_XFER_BEGIN | SPI_XFER_END);
+	return ret < 0 ? ret : din[1];
+}
 
 #endif	/* _SPI_H_ */
diff --git a/include/spi_flash.h b/include/spi_flash.h
new file mode 100644
index 00000000000..de4f174ad52
--- /dev/null
+++ b/include/spi_flash.h
@@ -0,0 +1,70 @@
+/*
+ * Interface to SPI flash
+ *
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _SPI_FLASH_H_
+#define _SPI_FLASH_H_
+
+#include <spi.h>
+
+struct spi_flash_region {
+	unsigned int	count;
+	unsigned int	size;
+};
+
+struct spi_flash {
+	struct spi_slave *spi;
+
+	const char	*name;
+
+	u32		size;
+
+	int		(*read)(struct spi_flash *flash, u32 offset,
+				size_t len, void *buf);
+	int		(*write)(struct spi_flash *flash, u32 offset,
+				size_t len, const void *buf);
+	int		(*erase)(struct spi_flash *flash, u32 offset,
+				size_t len);
+};
+
+struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
+		unsigned int max_hz, unsigned int spi_mode);
+void spi_flash_free(struct spi_flash *flash);
+
+static inline int spi_flash_read(struct spi_flash *flash, u32 offset,
+		size_t len, void *buf)
+{
+	return flash->read(flash, offset, len, buf);
+}
+
+static inline int spi_flash_write(struct spi_flash *flash, u32 offset,
+		size_t len, const void *buf)
+{
+	return flash->write(flash, offset, len, buf);
+}
+
+static inline int spi_flash_erase(struct spi_flash *flash, u32 offset,
+		size_t len)
+{
+	return flash->erase(flash, offset, len);
+}
+
+#endif /* _SPI_FLASH_H_ */
diff --git a/include/usb.h b/include/usb.h
index 5a6ffddec80..f8a4fdaa4de 100644
--- a/include/usb.h
+++ b/include/usb.h
@@ -12,7 +12,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -29,15 +29,15 @@
 #include <usb_defs.h>
 
 /* Everything is aribtrary */
-#define USB_ALTSETTINGALLOC		4
-#define USB_MAXALTSETTING		128	/* Hard limit */
+#define USB_ALTSETTINGALLOC 	4
+#define USB_MAXALTSETTING		128 /* Hard limit */
 
 #define USB_MAX_DEVICE			32
 #define USB_MAXCONFIG			8
 #define USB_MAXINTERFACES		8
 #define USB_MAXENDPOINTS		16
-#define USB_MAXCHILDREN			8	/* This is arbitrary */
-#define USB_MAX_HUB			16
+#define USB_MAXCHILDREN 		8	/* This is arbitrary */
+#define USB_MAX_HUB 		16
 
 #define USB_CNTL_TIMEOUT 100 /* 100ms timeout */
 
@@ -131,18 +131,19 @@ struct usb_config_descriptor {
 
 
 struct usb_device {
-	int devnum;			/* Device number on USB bus */
+	int devnum; 		/* Device number on USB bus */
 	int slow;			/* Slow device? */
+	int high;			/* High speed device? */
 	char mf[32];			/* manufacturer */
 	char prod[32];			/* product */
 	char serial[32];		/* serial number */
 
 	int maxpacketsize;		/* Maximum packet size; encoded as 0,1,2,3 = 8,16,32,64 */
-	unsigned int toggle[2];		/* one bit for each endpoint ([0] = IN, [1] = OUT) */
-	unsigned int halted[2];		/* endpoint halts; one bit per endpoint # & direction; */
-			    /* [0] = IN, [1] = OUT */
+	unsigned int toggle[2]; 	/* one bit for each endpoint ([0] = IN, [1] = OUT) */
+	unsigned int halted[2]; 	/* endpoint halts; one bit per endpoint # & direction; */
+				/* [0] = IN, [1] = OUT */
 	int epmaxpacketin[16];		/* INput endpoint specific maximums */
-	int epmaxpacketout[16];		/* OUTput endpoint specific maximums */
+	int epmaxpacketout[16]; 	/* OUTput endpoint specific maximums */
 
 	int configno;			/* selected config number */
 	struct usb_device_descriptor descriptor; /* Device Descriptor */
@@ -155,7 +156,7 @@ struct usb_device {
 	int irq_act_len;		/* transfered bytes */
 	void *privptr;
 	/*
-	 * Child devices -  if this is a hub device
+	 * Child devices -	if this is a hub device
 	 * Each instance needs its own set of data structures.
 	 */
 	unsigned long status;
@@ -171,7 +172,7 @@ struct usb_device {
 
 #if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || \
 	defined(CONFIG_USB_OHCI_NEW) || defined (CONFIG_USB_SL811HS) || \
-	defined(CONFIG_USB_ISP116X_HCD)
+	defined(CONFIG_USB_ISP116X_HCD) || defined(CONFIG_USB_DA8XX)
 
 int usb_lowlevel_init(void);
 int usb_lowlevel_stop(void);
@@ -184,7 +185,7 @@ void usb_event_poll(void);
 
 /* Defines */
 #define USB_UHCI_VEND_ID 0x8086
-#define USB_UHCI_DEV_ID	 0x7112
+#define USB_UHCI_DEV_ID  0x7112
 
 #else
 #error USB Lowlevel not defined
@@ -243,8 +244,8 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate);
 	({ unsigned long x_ = (unsigned long)x; \
 	 (unsigned long)( \
 		((x_ & 0x000000FFUL) << 24) | \
-		((x_ & 0x0000FF00UL) <<	 8) | \
-		((x_ & 0x00FF0000UL) >>	 8) | \
+		((x_ & 0x0000FF00UL) <<  8) | \
+		((x_ & 0x00FF0000UL) >>  8) | \
 		((x_ & 0xFF000000UL) >> 24) ); \
 	})
 
@@ -260,13 +261,13 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate);
  * Calling this entity a "pipe" is glorifying it. A USB pipe
  * is something embarrassingly simple: it basically consists
  * of the following information:
- *  - device number (7 bits)
- *  - endpoint number (4 bits)
- *  - current Data0/1 state (1 bit)
- *  - direction (1 bit)
- *  - speed (1 bit)
- *  - max packet size (2 bits: 8, 16, 32 or 64)
- *  - pipe type (2 bits: control, interrupt, bulk, isochronous)
+ *	- device number (7 bits)
+ *	- endpoint number (4 bits)
+ *	- current Data0/1 state (1 bit)
+ *	- direction (1 bit)
+ *	- speed (1 bit)
+ *	- max packet size (2 bits: 8, 16, 32 or 64)
+ *	- pipe type (2 bits: control, interrupt, bulk, isochronous)
  *
  * That's 18 bits. Really. Nothing more. And the USB people have
  * documented these eighteen bits as some kind of glorious
@@ -275,13 +276,13 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate);
  * Let's not fall in that trap. We'll just encode it as a simple
  * unsigned int. The encoding is:
  *
- *  - max size:		bits 0-1	(00 = 8, 01 = 16, 10 = 32, 11 = 64)
- *  - direction:	bit 7		(0 = Host-to-Device [Out], 1 = Device-to-Host [In])
- *  - device:		bits 8-14
- *  - endpoint:		bits 15-18
- *  - Data0/1:		bit 19
- *  - speed:		bit 26		(0 = Full, 1 = Low Speed)
- *  - pipe type:	bits 30-31	(00 = isochronous, 01 = interrupt, 10 = control, 11 = bulk)
+ *	- max size: 	bits 0-1	(00 = 8, 01 = 16, 10 = 32, 11 = 64)
+ *	- direction:	bit 7		(0 = Host-to-Device [Out], 1 = Device-to-Host [In])
+ *	- device:		bits 8-14
+ *	- endpoint: 	bits 15-18
+ *	- Data0/1:		bit 19
+ *	- speed:		bit 26		(0 = Full, 1 = Low Speed)
+ *	- pipe type:	bits 30-31	(00 = isochronous, 01 = interrupt, 10 = control, 11 = bulk)
  *
  * Why? Because it's arbitrary, and whatever encoding we select is really
  * up to us. This one happens to share a lot of bit positions with the UHCI
@@ -301,12 +302,12 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate);
 #define usb_rcvbulkpipe(dev,endpoint)	((PIPE_BULK << 30) | create_pipe(dev,endpoint) | USB_DIR_IN)
 #define usb_sndintpipe(dev,endpoint)	((PIPE_INTERRUPT << 30) | create_pipe(dev,endpoint))
 #define usb_rcvintpipe(dev,endpoint)	((PIPE_INTERRUPT << 30) | create_pipe(dev,endpoint) | USB_DIR_IN)
-#define usb_snddefctrl(dev)		((PIPE_CONTROL << 30) | default_pipe(dev))
-#define usb_rcvdefctrl(dev)		((PIPE_CONTROL << 30) | default_pipe(dev) | USB_DIR_IN)
+#define usb_snddefctrl(dev) 	((PIPE_CONTROL << 30) | default_pipe(dev))
+#define usb_rcvdefctrl(dev) 	((PIPE_CONTROL << 30) | default_pipe(dev) | USB_DIR_IN)
 
 /* The D0/D1 toggle bits */
 #define usb_gettoggle(dev, ep, out) (((dev)->toggle[out] >> ep) & 1)
-#define usb_dotoggle(dev, ep, out)  ((dev)->toggle[out] ^= (1 << ep))
+#define usb_dotoggle(dev, ep, out)	((dev)->toggle[out] ^= (1 << ep))
 #define usb_settoggle(dev, ep, out, bit) ((dev)->toggle[out] = ((dev)->toggle[out] & ~(1 << ep)) | ((bit) << ep))
 
 /* Endpoint halt control/status */
diff --git a/include/usb_defs.h b/include/usb_defs.h
index 353019fc166..6ad4d084e97 100644
--- a/include/usb_defs.h
+++ b/include/usb_defs.h
@@ -30,149 +30,149 @@
 
 /* Device and/or Interface Class codes */
 #define USB_CLASS_PER_INTERFACE  0	/* for DeviceClass */
-#define USB_CLASS_AUDIO          1
-#define USB_CLASS_COMM           2
-#define USB_CLASS_HID            3
-#define USB_CLASS_PRINTER	       7
-#define USB_CLASS_MASS_STORAGE   8
-#define USB_CLASS_HUB            9
-#define USB_CLASS_DATA           10
-#define USB_CLASS_VENDOR_SPEC    0xff
+#define USB_CLASS_AUDIO 		 1
+#define USB_CLASS_COMM			 2
+#define USB_CLASS_HID			 3
+#define USB_CLASS_PRINTER		   7
+#define USB_CLASS_MASS_STORAGE	 8
+#define USB_CLASS_HUB			 9
+#define USB_CLASS_DATA			 10
+#define USB_CLASS_VENDOR_SPEC	 0xff
 
 /* some HID sub classes */
-#define USB_SUB_HID_NONE        0
-#define USB_SUB_HID_BOOT        1
+#define USB_SUB_HID_NONE		0
+#define USB_SUB_HID_BOOT		1
 
 /* some UID Protocols */
-#define USB_PROT_HID_NONE       0
-#define USB_PROT_HID_KEYBOARD   1
-#define USB_PROT_HID_MOUSE      2
+#define USB_PROT_HID_NONE		0
+#define USB_PROT_HID_KEYBOARD	1
+#define USB_PROT_HID_MOUSE		2
 
 
 /* Sub STORAGE Classes */
-#define US_SC_RBC              1		/* Typically, flash devices */
-#define US_SC_8020             2		/* CD-ROM */
-#define US_SC_QIC              3		/* QIC-157 Tapes */
-#define US_SC_UFI              4		/* Floppy */
-#define US_SC_8070             5		/* Removable media */
-#define US_SC_SCSI             6		/* Transparent */
-#define US_SC_MIN              US_SC_RBC
-#define US_SC_MAX              US_SC_SCSI
+#define US_SC_RBC			   1		/* Typically, flash devices */
+#define US_SC_8020			   2		/* CD-ROM */
+#define US_SC_QIC			   3		/* QIC-157 Tapes */
+#define US_SC_UFI			   4		/* Floppy */
+#define US_SC_8070			   5		/* Removable media */
+#define US_SC_SCSI			   6		/* Transparent */
+#define US_SC_MIN			   US_SC_RBC
+#define US_SC_MAX			   US_SC_SCSI
 
 /* STORAGE Protocols */
-#define US_PR_CB               1		/* Control/Bulk w/o interrupt */
-#define US_PR_CBI              0		/* Control/Bulk/Interrupt */
-#define US_PR_BULK             0x50		/* bulk only */
+#define US_PR_CB			   1		/* Control/Bulk w/o interrupt */
+#define US_PR_CBI			   0		/* Control/Bulk/Interrupt */
+#define US_PR_BULK			   0x50 	/* bulk only */
 
 /* USB types */
-#define USB_TYPE_STANDARD   (0x00 << 5)
-#define USB_TYPE_CLASS      (0x01 << 5)
-#define USB_TYPE_VENDOR     (0x02 << 5)
-#define USB_TYPE_RESERVED   (0x03 << 5)
+#define USB_TYPE_STANDARD	(0x00 << 5)
+#define USB_TYPE_CLASS		(0x01 << 5)
+#define USB_TYPE_VENDOR 	(0x02 << 5)
+#define USB_TYPE_RESERVED	(0x03 << 5)
 
 /* USB recipients */
-#define USB_RECIP_DEVICE      0x00
+#define USB_RECIP_DEVICE	  0x00
 #define USB_RECIP_INTERFACE   0x01
-#define USB_RECIP_ENDPOINT    0x02
-#define USB_RECIP_OTHER       0x03
+#define USB_RECIP_ENDPOINT	  0x02
+#define USB_RECIP_OTHER 	  0x03
 
 /* USB directions */
-#define USB_DIR_OUT           0
-#define USB_DIR_IN            0x80
+#define USB_DIR_OUT 		  0
+#define USB_DIR_IN			  0x80
 
 /* Descriptor types */
-#define USB_DT_DEVICE        0x01
-#define USB_DT_CONFIG        0x02
-#define USB_DT_STRING        0x03
-#define USB_DT_INTERFACE     0x04
-#define USB_DT_ENDPOINT      0x05
+#define USB_DT_DEVICE		 0x01
+#define USB_DT_CONFIG		 0x02
+#define USB_DT_STRING		 0x03
+#define USB_DT_INTERFACE	 0x04
+#define USB_DT_ENDPOINT 	 0x05
 
-#define USB_DT_HID          (USB_TYPE_CLASS | 0x01)
-#define USB_DT_REPORT       (USB_TYPE_CLASS | 0x02)
-#define USB_DT_PHYSICAL     (USB_TYPE_CLASS | 0x03)
-#define USB_DT_HUB          (USB_TYPE_CLASS | 0x09)
+#define USB_DT_HID			(USB_TYPE_CLASS | 0x01)
+#define USB_DT_REPORT		(USB_TYPE_CLASS | 0x02)
+#define USB_DT_PHYSICAL 	(USB_TYPE_CLASS | 0x03)
+#define USB_DT_HUB			(USB_TYPE_CLASS | 0x09)
 
 /* Descriptor sizes per descriptor type */
-#define USB_DT_DEVICE_SIZE      18
-#define USB_DT_CONFIG_SIZE      9
-#define USB_DT_INTERFACE_SIZE   9
-#define USB_DT_ENDPOINT_SIZE    7
-#define USB_DT_ENDPOINT_AUDIO_SIZE  9	/* Audio extension */
-#define USB_DT_HUB_NONVAR_SIZE  7
-#define USB_DT_HID_SIZE         9
+#define USB_DT_DEVICE_SIZE		18
+#define USB_DT_CONFIG_SIZE		9
+#define USB_DT_INTERFACE_SIZE	9
+#define USB_DT_ENDPOINT_SIZE	7
+#define USB_DT_ENDPOINT_AUDIO_SIZE	9	/* Audio extension */
+#define USB_DT_HUB_NONVAR_SIZE	7
+#define USB_DT_HID_SIZE 		9
 
 /* Endpoints */
 #define USB_ENDPOINT_NUMBER_MASK  0x0f	/* in bEndpointAddress */
-#define USB_ENDPOINT_DIR_MASK     0x80
+#define USB_ENDPOINT_DIR_MASK	  0x80
 
-#define USB_ENDPOINT_XFERTYPE_MASK 0x03	/* in bmAttributes */
+#define USB_ENDPOINT_XFERTYPE_MASK 0x03 /* in bmAttributes */
 #define USB_ENDPOINT_XFER_CONTROL  0
-#define USB_ENDPOINT_XFER_ISOC     1
-#define USB_ENDPOINT_XFER_BULK     2
-#define USB_ENDPOINT_XFER_INT      3
+#define USB_ENDPOINT_XFER_ISOC	   1
+#define USB_ENDPOINT_XFER_BULK	   2
+#define USB_ENDPOINT_XFER_INT	   3
 
 /* USB Packet IDs (PIDs) */
-#define USB_PID_UNDEF_0             0xf0
-#define USB_PID_OUT                 0xe1
-#define USB_PID_ACK                 0xd2
-#define USB_PID_DATA0               0xc3
-#define USB_PID_UNDEF_4             0xb4
-#define USB_PID_SOF                 0xa5
-#define USB_PID_UNDEF_6             0x96
-#define USB_PID_UNDEF_7             0x87
-#define USB_PID_UNDEF_8             0x78
-#define USB_PID_IN                  0x69
-#define USB_PID_NAK                 0x5a
-#define USB_PID_DATA1               0x4b
-#define USB_PID_PREAMBLE            0x3c
-#define USB_PID_SETUP               0x2d
-#define USB_PID_STALL               0x1e
-#define USB_PID_UNDEF_F             0x0f
+#define USB_PID_UNDEF_0 			0xf0
+#define USB_PID_OUT 				0xe1
+#define USB_PID_ACK 				0xd2
+#define USB_PID_DATA0				0xc3
+#define USB_PID_UNDEF_4 			0xb4
+#define USB_PID_SOF 				0xa5
+#define USB_PID_UNDEF_6 			0x96
+#define USB_PID_UNDEF_7 			0x87
+#define USB_PID_UNDEF_8 			0x78
+#define USB_PID_IN					0x69
+#define USB_PID_NAK 				0x5a
+#define USB_PID_DATA1				0x4b
+#define USB_PID_PREAMBLE			0x3c
+#define USB_PID_SETUP				0x2d
+#define USB_PID_STALL				0x1e
+#define USB_PID_UNDEF_F 			0x0f
 
 /* Standard requests */
-#define USB_REQ_GET_STATUS          0x00
-#define USB_REQ_CLEAR_FEATURE       0x01
-#define USB_REQ_SET_FEATURE         0x03
-#define USB_REQ_SET_ADDRESS         0x05
-#define USB_REQ_GET_DESCRIPTOR      0x06
-#define USB_REQ_SET_DESCRIPTOR      0x07
-#define USB_REQ_GET_CONFIGURATION   0x08
-#define USB_REQ_SET_CONFIGURATION   0x09
-#define USB_REQ_GET_INTERFACE       0x0A
-#define USB_REQ_SET_INTERFACE       0x0B
-#define USB_REQ_SYNCH_FRAME         0x0C
+#define USB_REQ_GET_STATUS			0x00
+#define USB_REQ_CLEAR_FEATURE		0x01
+#define USB_REQ_SET_FEATURE 		0x03
+#define USB_REQ_SET_ADDRESS 		0x05
+#define USB_REQ_GET_DESCRIPTOR		0x06
+#define USB_REQ_SET_DESCRIPTOR		0x07
+#define USB_REQ_GET_CONFIGURATION	0x08
+#define USB_REQ_SET_CONFIGURATION	0x09
+#define USB_REQ_GET_INTERFACE		0x0A
+#define USB_REQ_SET_INTERFACE		0x0B
+#define USB_REQ_SYNCH_FRAME 		0x0C
 
 /* HID requests */
-#define USB_REQ_GET_REPORT          0x01
-#define USB_REQ_GET_IDLE            0x02
-#define USB_REQ_GET_PROTOCOL        0x03
-#define USB_REQ_SET_REPORT          0x09
-#define USB_REQ_SET_IDLE            0x0A
-#define USB_REQ_SET_PROTOCOL        0x0B
+#define USB_REQ_GET_REPORT			0x01
+#define USB_REQ_GET_IDLE			0x02
+#define USB_REQ_GET_PROTOCOL		0x03
+#define USB_REQ_SET_REPORT			0x09
+#define USB_REQ_SET_IDLE			0x0A
+#define USB_REQ_SET_PROTOCOL		0x0B
 
 
 /* "pipe" definitions */
 
-#define PIPE_ISOCHRONOUS    0
-#define PIPE_INTERRUPT      1
-#define PIPE_CONTROL        2
-#define PIPE_BULK           3
-#define PIPE_DEVEP_MASK     0x0007ff00
+#define PIPE_ISOCHRONOUS	0
+#define PIPE_INTERRUPT		1
+#define PIPE_CONTROL		2
+#define PIPE_BULK			3
+#define PIPE_DEVEP_MASK 	0x0007ff00
 
 #define USB_ISOCHRONOUS    0
-#define USB_INTERRUPT      1
-#define USB_CONTROL        2
-#define USB_BULK           3
+#define USB_INTERRUPT	   1
+#define USB_CONTROL 	   2
+#define USB_BULK		   3
 
 /* USB-status codes: */
-#define USB_ST_ACTIVE           0x1		/* TD is active */
-#define USB_ST_STALLED          0x2		/* TD is stalled */
-#define USB_ST_BUF_ERR          0x4		/* buffer error */
-#define USB_ST_BABBLE_DET       0x8		/* Babble detected */
-#define USB_ST_NAK_REC          0x10	/* NAK Received*/
-#define USB_ST_CRC_ERR          0x20	/* CRC/timeout Error */
-#define USB_ST_BIT_ERR          0x40	/* Bitstuff error */
-#define USB_ST_NOT_PROC         0x80000000L	/* Not yet processed */
+#define USB_ST_ACTIVE			0x1 	/* TD is active */
+#define USB_ST_STALLED			0x2 	/* TD is stalled */
+#define USB_ST_BUF_ERR			0x4 	/* buffer error */
+#define USB_ST_BABBLE_DET		0x8 	/* Babble detected */
+#define USB_ST_NAK_REC			0x10	/* NAK Received*/
+#define USB_ST_CRC_ERR			0x20	/* CRC/timeout Error */
+#define USB_ST_BIT_ERR			0x40	/* Bitstuff error */
+#define USB_ST_NOT_PROC 		0x80000000L /* Not yet processed */
 
 
 /*************************************************************************
@@ -184,50 +184,51 @@
  */
 
 #define USB_RT_HUB	(USB_TYPE_CLASS | USB_RECIP_DEVICE)
-#define USB_RT_PORT	(USB_TYPE_CLASS | USB_RECIP_OTHER)
+#define USB_RT_PORT (USB_TYPE_CLASS | USB_RECIP_OTHER)
 
 /*
  * Hub Class feature numbers
  */
-#define C_HUB_LOCAL_POWER   0
-#define C_HUB_OVER_CURRENT  1
+#define C_HUB_LOCAL_POWER	0
+#define C_HUB_OVER_CURRENT	1
 
 /*
  * Port feature numbers
  */
-#define USB_PORT_FEAT_CONNECTION     0
-#define USB_PORT_FEAT_ENABLE         1
-#define USB_PORT_FEAT_SUSPEND        2
-#define USB_PORT_FEAT_OVER_CURRENT   3
-#define USB_PORT_FEAT_RESET          4
-#define USB_PORT_FEAT_POWER          8
-#define USB_PORT_FEAT_LOWSPEED       9
-#define USB_PORT_FEAT_C_CONNECTION   16
-#define USB_PORT_FEAT_C_ENABLE       17
-#define USB_PORT_FEAT_C_SUSPEND      18
+#define USB_PORT_FEAT_CONNECTION	 0
+#define USB_PORT_FEAT_ENABLE		 1
+#define USB_PORT_FEAT_SUSPEND		 2
+#define USB_PORT_FEAT_OVER_CURRENT	 3
+#define USB_PORT_FEAT_RESET 		 4
+#define USB_PORT_FEAT_POWER 		 8
+#define USB_PORT_FEAT_LOWSPEED		 9
+#define USB_PORT_FEAT_C_CONNECTION	 16
+#define USB_PORT_FEAT_C_ENABLE		 17
+#define USB_PORT_FEAT_C_SUSPEND 	 18
 #define USB_PORT_FEAT_C_OVER_CURRENT 19
-#define USB_PORT_FEAT_C_RESET        20
+#define USB_PORT_FEAT_C_RESET		 20
 
 /* wPortStatus bits */
-#define USB_PORT_STAT_CONNECTION    0x0001
-#define USB_PORT_STAT_ENABLE        0x0002
-#define USB_PORT_STAT_SUSPEND       0x0004
-#define USB_PORT_STAT_OVERCURRENT   0x0008
-#define USB_PORT_STAT_RESET         0x0010
-#define USB_PORT_STAT_POWER         0x0100
-#define USB_PORT_STAT_LOW_SPEED     0x0200
+#define USB_PORT_STAT_CONNECTION	0x0001
+#define USB_PORT_STAT_ENABLE		0x0002
+#define USB_PORT_STAT_SUSPEND		0x0004
+#define USB_PORT_STAT_OVERCURRENT	0x0008
+#define USB_PORT_STAT_RESET 		0x0010
+#define USB_PORT_STAT_POWER 		0x0100
+#define USB_PORT_STAT_LOW_SPEED 	0x0200
+#define USB_PORT_STAT_HIGH_SPEED	0x0400
 
 /* wPortChange bits */
-#define USB_PORT_STAT_C_CONNECTION  0x0001
-#define USB_PORT_STAT_C_ENABLE      0x0002
-#define USB_PORT_STAT_C_SUSPEND     0x0004
+#define USB_PORT_STAT_C_CONNECTION	0x0001
+#define USB_PORT_STAT_C_ENABLE		0x0002
+#define USB_PORT_STAT_C_SUSPEND 	0x0004
 #define USB_PORT_STAT_C_OVERCURRENT 0x0008
-#define USB_PORT_STAT_C_RESET       0x0010
+#define USB_PORT_STAT_C_RESET		0x0010
 
 /* wHubCharacteristics (masks) */
-#define HUB_CHAR_LPSM               0x0003
-#define HUB_CHAR_COMPOUND           0x0004
-#define HUB_CHAR_OCPM               0x0018
+#define HUB_CHAR_LPSM				0x0003
+#define HUB_CHAR_COMPOUND			0x0004
+#define HUB_CHAR_OCPM				0x0018
 
 /*
  *Hub Status & Hub Change bit masks
@@ -238,4 +239,6 @@
 #define HUB_CHANGE_LOCAL_POWER	0x0001
 #define HUB_CHANGE_OVERCURRENT	0x0002
 
+#define LITTLEENDIAN
+
 #endif /*_USB_DEFS_H_ */