diff options
| author | Hou Zhiqiang <Zhiqiang.Hou@nxp.com> | 2016-12-09 16:09:00 +0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2017-01-18 09:29:08 -0800 |
| commit | 031acdbae89515371f794d01df819b490ff7ca9c (patch) | |
| tree | 6ce8549630686f35299191fe944d0b7d8e18e238 /include | |
| parent | 6424577b1bf1c7872baea42de174bc461de74b6b (diff) | |
armv8/fsl_lsch2: Add chip power supply voltage setup
Set up chip power supply voltage according to voltage ID.
The fuse status register provides the values from on-chip
voltage ID fuses programmed at the factory. These values
define the voltage requirements for the chip.
Main operations:
1. Set up the core voltage
2. Set up the SERDES voltage and reset SERDES lanes
3. Enable/disable DDR controller support 0.9V if needed
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/fsl_ddr_sdram.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index 1404c579360..b8de46bb42e 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -173,6 +173,7 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; /* DDR_CDR1 */ #define DDR_CDR1_DHC_EN 0x80000000 +#define DDR_CDR1_V0PT9_EN 0x40000000 #define DDR_CDR1_ODT_SHIFT 17 #define DDR_CDR1_ODT_MASK 0x6 #define DDR_CDR2_ODT_MASK 0x1 |