diff options
| author | wdenk <wdenk> | 2003-06-27 21:31:46 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2003-06-27 21:31:46 +0000 |
| commit | 8bde7f776c77b343aca29b8c7b58464d915ac245 (patch) | |
| tree | 20f1fd99975215e7c658454a15cdb4ed4694e2d4 /include | |
| parent | 993cad9364c6b87ae429d1ed1130d8153f6f027e (diff) | |
* Code cleanup:LABEL_2003_06_27_2340
- remove trailing white space, trailing empty lines, C++ comments, etc.
- split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c)
* Patches by Kenneth Johansson, 25 Jun 2003:
- major rework of command structure
(work done mostly by Michal Cendrowski and Joakim Kristiansen)
Diffstat (limited to 'include')
212 files changed, 3273 insertions, 6027 deletions
diff --git a/include/405_dimm.h b/include/405_dimm.h index b2bbe870e92..103a3490902 100644 --- a/include/405_dimm.h +++ b/include/405_dimm.h @@ -2,4 +2,3 @@ #define _405_dimm_h_ long int walnut_dimm(void); #endif - diff --git a/include/405_mal.h b/include/405_mal.h index 459924b6bef..020874fdd13 100644 --- a/include/405_mal.h +++ b/include/405_mal.h @@ -103,4 +103,3 @@ typedef struct { } mal_desc_t; #endif - diff --git a/include/405gp_enet.h b/include/405gp_enet.h index 52a2f331beb..224452106ed 100644 --- a/include/405gp_enet.h +++ b/include/405gp_enet.h @@ -236,8 +236,6 @@ struct arp_entry { #define EMAC_RX_ERRORS 0x03FF - - /*-----------------------------------------------------------------------------+ | Function prototypes for device table. +-----------------------------------------------------------------------------*/ diff --git a/include/440_i2c.h b/include/440_i2c.h index d04976646d8..b0ac592faf7 100644 --- a/include/440_i2c.h +++ b/include/440_i2c.h @@ -1,6 +1,3 @@ - - - #ifndef _440_i2c_h_ #define _440_i2c_h_ diff --git a/include/SA-1100.h b/include/SA-1100.h index f1f9625c3da..9985783e586 100644 --- a/include/SA-1100.h +++ b/include/SA-1100.h @@ -54,13 +54,13 @@ typedef void (*ExcpHndlr) (void) ; #define StMemBnkSp MemBnkSp /* Static Memory Bank Space [byte] */ #define StMemBnk0Sp StMemBnkSp /* Static Memory Bank 0 Space */ - /* [byte] */ + /* [byte] */ #define StMemBnk1Sp StMemBnkSp /* Static Memory Bank 1 Space */ - /* [byte] */ + /* [byte] */ #define StMemBnk2Sp StMemBnkSp /* Static Memory Bank 2 Space */ - /* [byte] */ + /* [byte] */ #define StMemBnk3Sp StMemBnkSp /* Static Memory Bank 3 Space */ - /* [byte] */ + /* [byte] */ #define DRAMBnkSp MemBnkSp /* DRAM Bank Space [byte] */ #define DRAMBnk0Sp DRAMBnkSp /* DRAM Bank 0 Space [byte] */ @@ -71,7 +71,7 @@ typedef void (*ExcpHndlr) (void) ; #define ZeroMemSp MemBnkSp /* Zero Memory bank Space [byte] */ #define _StMemBnk(Nb) /* Static Memory Bank [0..3] */ \ - (0x00000000 + (Nb)*StMemBnkSp) + (0x00000000 + (Nb)*StMemBnkSp) #define _StMemBnk0 _StMemBnk (0) /* Static Memory Bank 0 */ #define _StMemBnk1 _StMemBnk (1) /* Static Memory Bank 1 */ #define _StMemBnk2 _StMemBnk (2) /* Static Memory Bank 2 */ @@ -80,7 +80,7 @@ typedef void (*ExcpHndlr) (void) ; #if LANGUAGE == C typedef Quad StMemBnkType [StMemBnkSp/sizeof (Quad)] ; #define StMemBnk /* Static Memory Bank [0..3] */ \ - ((StMemBnkType *) io_p2v (_StMemBnk (0))) + ((StMemBnkType *) io_p2v (_StMemBnk (0))) #define StMemBnk0 (StMemBnk [0]) /* Static Memory Bank 0 */ #define StMemBnk1 (StMemBnk [1]) /* Static Memory Bank 1 */ #define StMemBnk2 (StMemBnk [2]) /* Static Memory Bank 2 */ @@ -88,7 +88,7 @@ typedef Quad StMemBnkType [StMemBnkSp/sizeof (Quad)] ; #endif /* LANGUAGE == C */ #define _DRAMBnk(Nb) /* DRAM Bank [0..3] */ \ - (0xC0000000 + (Nb)*DRAMBnkSp) + (0xC0000000 + (Nb)*DRAMBnkSp) #define _DRAMBnk0 _DRAMBnk (0) /* DRAM Bank 0 */ #define _DRAMBnk1 _DRAMBnk (1) /* DRAM Bank 1 */ #define _DRAMBnk2 _DRAMBnk (2) /* DRAM Bank 2 */ @@ -97,7 +97,7 @@ typedef Quad StMemBnkType [StMemBnkSp/sizeof (Quad)] ; #if LANGUAGE == C typedef Quad DRAMBnkType [DRAMBnkSp/sizeof (Quad)] ; #define DRAMBnk /* DRAM Bank [0..3] */ \ - ((DRAMBnkType *) io_p2v (_DRAMBnk (0))) + ((DRAMBnkType *) io_p2v (_DRAMBnk (0))) #define DRAMBnk0 (DRAMBnk [0]) /* DRAM Bank 0 */ #define DRAMBnk1 (DRAMBnk [1]) /* DRAM Bank 1 */ #define DRAMBnk2 (DRAMBnk [2]) /* DRAM Bank 2 */ @@ -109,7 +109,7 @@ typedef Quad DRAMBnkType [DRAMBnkSp/sizeof (Quad)] ; #if LANGUAGE == C typedef Quad ZeroMemType [ZeroMemSp/sizeof (Quad)] ; #define ZeroMem /* Zero Memory bank */ \ - (*((ZeroMemType *) io_p2v (_ZeroMem))) + (*((ZeroMemType *) io_p2v (_ZeroMem))) #endif /* LANGUAGE == C */ @@ -134,12 +134,12 @@ typedef Quad ZeroMemType [ZeroMemSp/sizeof (Quad)] ; #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */ #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ - (0x20000000 + (Nb)*PCMCIASp) + (0x20000000 + (Nb)*PCMCIASp) #define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ - (_PCMCIA (Nb) + 2*PCMCIAPrtSp) + (_PCMCIA (Nb) + 2*PCMCIAPrtSp) #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ - (_PCMCIA (Nb) + 3*PCMCIAPrtSp) + (_PCMCIA (Nb) + 3*PCMCIAPrtSp) #define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */ #define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */ @@ -157,22 +157,22 @@ typedef Quad PCMCIAPrtType [PCMCIAPrtSp/sizeof (Quad)] ; typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define PCMCIA0 /* PCMCIA 0 */ \ - (*((PCMCIAType *) io_p2v (_PCMCIA0))) + (*((PCMCIAType *) io_p2v (_PCMCIA0))) #define PCMCIA0IO /* PCMCIA 0 I/O */ \ - (*((PCMCIAPrtType *) io_p2v (_PCMCIA0IO))) + (*((PCMCIAPrtType *) io_p2v (_PCMCIA0IO))) #define PCMCIA0Attr /* PCMCIA 0 Attribute */ \ - (*((PCMCIAPrtType *) io_p2v (_PCMCIA0Attr))) + (*((PCMCIAPrtType *) io_p2v (_PCMCIA0Attr))) #define PCMCIA0Mem /* PCMCIA 0 Memory */ \ - (*((PCMCIAPrtType *) io_p2v (_PCMCIA0Mem))) + (*((PCMCIAPrtType *) io_p2v (_PCMCIA0Mem))) #define PCMCIA1 /* PCMCIA 1 */ \ - (*((PCMCIAType *) io_p2v (_PCMCIA1))) + (*((PCMCIAType *) io_p2v (_PCMCIA1))) #define PCMCIA1IO /* PCMCIA 1 I/O */ \ - (*((PCMCIAPrtType *) io_p2v (_PCMCIA1IO))) + (*((PCMCIAPrtType *) io_p2v (_PCMCIA1IO))) #define PCMCIA1Attr /* PCMCIA 1 Attribute */ \ - (*((PCMCIAPrtType *) io_p2v (_PCMCIA1Attr))) + (*((PCMCIAPrtType *) io_p2v (_PCMCIA1Attr))) #define PCMCIA1Mem /* PCMCIA 1 Memory */ \ - (*((PCMCIAPrtType *) io_p2v (_PCMCIA1Mem))) + (*((PCMCIAPrtType *) io_p2v (_PCMCIA1Mem))) #endif /* LANGUAGE == C */ @@ -215,81 +215,81 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define _Ser0UDCCR 0x80000000 /* Ser. port 0 UDC Control Reg. */ #define _Ser0UDCAR 0x80000004 /* Ser. port 0 UDC Address Reg. */ #define _Ser0UDCOMP 0x80000008 /* Ser. port 0 UDC Output Maximum */ - /* Packet size reg. */ + /* Packet size reg. */ #define _Ser0UDCIMP 0x8000000C /* Ser. port 0 UDC Input Maximum */ - /* Packet size reg. */ + /* Packet size reg. */ #define _Ser0UDCCS0 0x80000010 /* Ser. port 0 UDC Control/Status */ - /* reg. end-point 0 */ + /* reg. end-point 0 */ #define _Ser0UDCCS1 0x80000014 /* Ser. port 0 UDC Control/Status */ - /* reg. end-point 1 (output) */ + /* reg. end-point 1 (output) */ #define _Ser0UDCCS2 0x80000018 /* Ser. port 0 UDC Control/Status */ - /* reg. end-point 2 (input) */ + /* reg. end-point 2 (input) */ #define _Ser0UDCD0 0x8000001C /* Ser. port 0 UDC Data reg. */ - /* end-point 0 */ + /* end-point 0 */ #define _Ser0UDCWC 0x80000020 /* Ser. port 0 UDC Write Count */ - /* reg. end-point 0 */ + /* reg. end-point 0 */ #define _Ser0UDCDR 0x80000028 /* Ser. port 0 UDC Data Reg. */ #define _Ser0UDCSR 0x80000030 /* Ser. port 0 UDC Status Reg. */ #if LANGUAGE == C #define Ser0UDCCR /* Ser. port 0 UDC Control Reg. */ \ - (*((volatile Word *) io_p2v (_Ser0UDCCR))) + (*((volatile Word *) io_p2v (_Ser0UDCCR))) #define Ser0UDCAR /* Ser. port 0 UDC Address Reg. */ \ - (*((volatile Word *) io_p2v (_Ser0UDCAR))) + (*((volatile Word *) io_p2v (_Ser0UDCAR))) #define Ser0UDCOMP /* Ser. port 0 UDC Output Maximum */ \ - /* Packet size reg. */ \ - (*((volatile Word *) io_p2v (_Ser0UDCOMP))) + /* Packet size reg. */ \ + (*((volatile Word *) io_p2v (_Ser0UDCOMP))) #define Ser0UDCIMP /* Ser. port 0 UDC Input Maximum */ \ - /* Packet size reg. */ \ - (*((volatile Word *) io_p2v (_Ser0UDCIMP))) + /* Packet size reg. */ \ + (*((volatile Word *) io_p2v (_Ser0UDCIMP))) #define Ser0UDCCS0 /* Ser. port 0 UDC Control/Status */ \ - /* reg. end-point 0 */ \ - (*((volatile Word *) io_p2v (_Ser0UDCCS0))) + /* reg. end-point 0 */ \ + (*((volatile Word *) io_p2v (_Ser0UDCCS0))) #define Ser0UDCCS1 /* Ser. port 0 UDC Control/Status */ \ - /* reg. end-point 1 (output) */ \ - (*((volatile Word *) io_p2v (_Ser0UDCCS1))) + /* reg. end-point 1 (output) */ \ + (*((volatile Word *) io_p2v (_Ser0UDCCS1))) #define Ser0UDCCS2 /* Ser. port 0 UDC Control/Status */ \ - /* reg. end-point 2 (input) */ \ - (*((volatile Word *) io_p2v (_Ser0UDCCS2))) + /* reg. end-point 2 (input) */ \ + (*((volatile Word *) io_p2v (_Ser0UDCCS2))) #define Ser0UDCD0 /* Ser. port 0 UDC Data reg. */ \ - /* end-point 0 */ \ - (*((volatile Word *) io_p2v (_Ser0UDCD0))) + /* end-point 0 */ \ + (*((volatile Word *) io_p2v (_Ser0UDCD0))) #define Ser0UDCWC /* Ser. port 0 UDC Write Count */ \ - /* reg. end-point 0 */ \ - (*((volatile Word *) io_p2v (_Ser0UDCWC))) + /* reg. end-point 0 */ \ + (*((volatile Word *) io_p2v (_Ser0UDCWC))) #define Ser0UDCDR /* Ser. port 0 UDC Data Reg. */ \ - (*((volatile Word *) io_p2v (_Ser0UDCDR))) + (*((volatile Word *) io_p2v (_Ser0UDCDR))) #define Ser0UDCSR /* Ser. port 0 UDC Status Reg. */ \ - (*((volatile Word *) io_p2v (_Ser0UDCSR))) + (*((volatile Word *) io_p2v (_Ser0UDCSR))) #endif /* LANGUAGE == C */ #define UDCCR_UDD 0x00000001 /* UDC Disable */ #define UDCCR_UDA 0x00000002 /* UDC Active (read) */ #define UDCCR_RESIM 0x00000004 /* Resume Interrupt Mask, per errata */ #define UDCCR_EIM 0x00000008 /* End-point 0 Interrupt Mask */ - /* (disable) */ + /* (disable) */ #define UDCCR_RIM 0x00000010 /* Receive Interrupt Mask */ - /* (disable) */ + /* (disable) */ #define UDCCR_TIM 0x00000020 /* Transmit Interrupt Mask */ - /* (disable) */ + /* (disable) */ #define UDCCR_SRM 0x00000040 /* Suspend/Resume interrupt Mask */ - /* (disable) */ + /* (disable) */ #define UDCCR_SUSIM UDCCR_SRM /* Per errata, SRM just masks suspend */ #define UDCCR_REM 0x00000080 /* REset interrupt Mask (disable) */ #define UDCAR_ADD Fld (7, 0) /* function ADDress */ #define UDCOMP_OUTMAXP Fld (8, 0) /* OUTput MAXimum Packet size - 1 */ - /* [byte] */ + /* [byte] */ #define UDCOMP_OutMaxPkt(Size) /* Output Maximum Packet size */ \ - /* [1..256 byte] */ \ - (((Size) - 1) << FShft (UDCOMP_OUTMAXP)) + /* [1..256 byte] */ \ + (((Size) - 1) << FShft (UDCOMP_OUTMAXP)) #define UDCIMP_INMAXP Fld (8, 0) /* INput MAXimum Packet size - 1 */ - /* [byte] */ + /* [byte] */ #define UDCIMP_InMaxPkt(Size) /* Input Maximum Packet size */ \ - /* [1..256 byte] */ \ - (((Size) - 1) << FShft (UDCIMP_INMAXP)) + /* [1..256 byte] */ \ + (((Size) - 1) << FShft (UDCIMP_INMAXP)) #define UDCCS0_OPR 0x00000001 /* Output Packet Ready (read) */ #define UDCCS0_IPR 0x00000002 /* Input Packet Ready */ @@ -298,11 +298,11 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define UDCCS0_DE 0x00000010 /* Data End */ #define UDCCS0_SE 0x00000020 /* Setup End (read) */ #define UDCCS0_SO 0x00000040 /* Serviced Output packet ready */ - /* (write) */ + /* (write) */ #define UDCCS0_SSE 0x00000080 /* Serviced Setup End (write) */ #define UDCCS1_RFS 0x00000001 /* Receive FIFO 12-bytes or more */ - /* Service request (read) */ + /* Service request (read) */ #define UDCCS1_RPC 0x00000002 /* Receive Packet Complete */ #define UDCCS1_RPE 0x00000004 /* Receive Packet Error (read) */ #define UDCCS1_SST 0x00000008 /* Sent STall */ @@ -310,7 +310,7 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define UDCCS1_RNE 0x00000020 /* Receive FIFO Not Empty (read) */ #define UDCCS2_TFS 0x00000001 /* Transmit FIFO 8-bytes or less */ - /* Service request (read) */ + /* Service request (read) */ #define UDCCS2_TPC 0x00000002 /* Transmit Packet Complete */ #define UDCCS2_TPE 0x00000004 /* Transmit Packet Error (read) */ #define UDCCS2_TUR 0x00000008 /* Transmit FIFO Under-Run */ @@ -408,21 +408,21 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; */ #define _UTCR0(Nb) /* UART Control Reg. 0 [1..3] */ \ - (0x80010000 + ((Nb) - 1)*0x00020000) + (0x80010000 + ((Nb) - 1)*0x00020000) #define _UTCR1(Nb) /* UART Control Reg. 1 [1..3] */ \ - (0x80010004 + ((Nb) - 1)*0x00020000) + (0x80010004 + ((Nb) - 1)*0x00020000) #define _UTCR2(Nb) /* UART Control Reg. 2 [1..3] */ \ - (0x80010008 + ((Nb) - 1)*0x00020000) + (0x80010008 + ((Nb) - 1)*0x00020000) #define _UTCR3(Nb) /* UART Control Reg. 3 [1..3] */ \ - (0x8001000C + ((Nb) - 1)*0x00020000) + (0x8001000C + ((Nb) - 1)*0x00020000) #define _UTCR4(Nb) /* UART Control Reg. 4 [2] */ \ - (0x80010010 + ((Nb) - 1)*0x00020000) + (0x80010010 + ((Nb) - 1)*0x00020000) #define _UTDR(Nb) /* UART Data Reg. [1..3] */ \ - (0x80010014 + ((Nb) - 1)*0x00020000) + (0x80010014 + ((Nb) - 1)*0x00020000) #define _UTSR0(Nb) /* UART Status Reg. 0 [1..3] */ \ - (0x8001001C + ((Nb) - 1)*0x00020000) + (0x8001001C + ((Nb) - 1)*0x00020000) #define _UTSR1(Nb) /* UART Status Reg. 1 [1..3] */ \ - (0x80010020 + ((Nb) - 1)*0x00020000) + (0x80010020 + ((Nb) - 1)*0x00020000) #define _Ser1UTCR0 _UTCR0 (1) /* Ser. port 1 UART Control Reg. 0 */ #define _Ser1UTCR1 _UTCR1 (1) /* Ser. port 1 UART Control Reg. 1 */ @@ -452,51 +452,51 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #if LANGUAGE == C #define Ser1UTCR0 /* Ser. port 1 UART Control Reg. 0 */ \ - (*((volatile Word *) io_p2v (_Ser1UTCR0))) + (*((volatile Word *) io_p2v (_Ser1UTCR0))) #define Ser1UTCR1 /* Ser. port 1 UART Control Reg. 1 */ \ - (*((volatile Word *) io_p2v (_Ser1UTCR1))) + (*((volatile Word *) io_p2v (_Ser1UTCR1))) #define Ser1UTCR2 /* Ser. port 1 UART Control Reg. 2 */ \ - (*((volatile Word *) io_p2v (_Ser1UTCR2))) + (*((volatile Word *) io_p2v (_Ser1UTCR2))) #define Ser1UTCR3 /* Ser. port 1 UART Control Reg. 3 */ \ - (*((volatile Word *) io_p2v (_Ser1UTCR3))) + (*((volatile Word *) io_p2v (_Ser1UTCR3))) #define Ser1UTDR /* Ser. port 1 UART Data Reg. */ \ - (*((volatile Word *) io_p2v (_Ser1UTDR))) + (*((volatile Word *) io_p2v (_Ser1UTDR))) #define Ser1UTSR0 /* Ser. port 1 UART Status Reg. 0 */ \ - (*((volatile Word *) io_p2v (_Ser1UTSR0))) + (*((volatile Word *) io_p2v (_Ser1UTSR0))) #define Ser1UTSR1 /* Ser. port 1 UART Status Reg. 1 */ \ - (*((volatile Word *) io_p2v (_Ser1UTSR1))) + (*((volatile Word *) io_p2v (_Ser1UTSR1))) #define Ser2UTCR0 /* Ser. port 2 UART Control Reg. 0 */ \ - (*((volatile Word *) io_p2v (_Ser2UTCR0))) + (*((volatile Word *) io_p2v (_Ser2UTCR0))) #define Ser2UTCR1 /* Ser. port 2 UART Control Reg. 1 */ \ - (*((volatile Word *) io_p2v (_Ser2UTCR1))) + (*((volatile Word *) io_p2v (_Ser2UTCR1))) #define Ser2UTCR2 /* Ser. port 2 UART Control Reg. 2 */ \ - (*((volatile Word *) io_p2v (_Ser2UTCR2))) + (*((volatile Word *) io_p2v (_Ser2UTCR2))) #define Ser2UTCR3 /* Ser. port 2 UART Control Reg. 3 */ \ - (*((volatile Word *) io_p2v (_Ser2UTCR3))) + (*((volatile Word *) io_p2v (_Ser2UTCR3))) #define Ser2UTCR4 /* Ser. port 2 UART Control Reg. 4 */ \ - (*((volatile Word *) io_p2v (_Ser2UTCR4))) + (*((volatile Word *) io_p2v (_Ser2UTCR4))) #define Ser2UTDR /* Ser. port 2 UART Data Reg. */ \ - (*((volatile Word *) io_p2v (_Ser2UTDR))) + (*((volatile Word *) io_p2v (_Ser2UTDR))) #define Ser2UTSR0 /* Ser. port 2 UART Status Reg. 0 */ \ - (*((volatile Word *) io_p2v (_Ser2UTSR0))) + (*((volatile Word *) io_p2v (_Ser2UTSR0))) #define Ser2UTSR1 /* Ser. port 2 UART Status Reg. 1 */ \ - (*((volatile Word *) io_p2v (_Ser2UTSR1))) + (*((volatile Word *) io_p2v (_Ser2UTSR1))) #define Ser3UTCR0 /* Ser. port 3 UART Control Reg. 0 */ \ - (*((volatile Word *) io_p2v (_Ser3UTCR0))) + (*((volatile Word *) io_p2v (_Ser3UTCR0))) #define Ser3UTCR1 /* Ser. port 3 UART Control Reg. 1 */ \ - (*((volatile Word *) io_p2v (_Ser3UTCR1))) + (*((volatile Word *) io_p2v (_Ser3UTCR1))) #define Ser3UTCR2 /* Ser. port 3 UART Control Reg. 2 */ \ - (*((volatile Word *) io_p2v (_Ser3UTCR2))) + (*((volatile Word *) io_p2v (_Ser3UTCR2))) #define Ser3UTCR3 /* Ser. port 3 UART Control Reg. 3 */ \ - (*((volatile Word *) io_p2v (_Ser3UTCR3))) + (*((volatile Word *) io_p2v (_Ser3UTCR3))) #define Ser3UTDR /* Ser. port 3 UART Data Reg. */ \ - (*((volatile Word *) io_p2v (_Ser3UTDR))) + (*((volatile Word *) io_p2v (_Ser3UTDR))) #define Ser3UTSR0 /* Ser. port 3 UART Status Reg. 0 */ \ - (*((volatile Word *) io_p2v (_Ser3UTSR0))) + (*((volatile Word *) io_p2v (_Ser3UTSR0))) #define Ser3UTSR1 /* Ser. port 3 UART Status Reg. 1 */ \ - (*((volatile Word *) io_p2v (_Ser3UTSR1))) + (*((volatile Word *) io_p2v (_Ser3UTSR1))) #elif LANGUAGE == Assembly #define Ser1UTCR0 ( io_p2v (_Ser1UTCR0)) @@ -537,8 +537,8 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define UTCR0_7BitData (UTCR0_DSS*0) /* 7-Bit Data */ #define UTCR0_8BitData (UTCR0_DSS*1) /* 8-Bit Data */ #define UTCR0_SCE 0x00000010 /* Sample Clock Enable */ - /* (ser. port 1: GPIO [18], */ - /* ser. port 3: GPIO [20]) */ + /* (ser. port 1: GPIO [18], */ + /* ser. port 3: GPIO [20]) */ #define UTCR0_RCE 0x00000020 /* Receive Clock Edge select */ #define UTCR0_RcRsEdg (UTCR0_RCE*0) /* Receive clock Rising-Edge */ #define UTCR0_RcFlEdg (UTCR0_RCE*1) /* Receive clock Falling-Edge */ @@ -546,43 +546,43 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define UTCR0_TrRsEdg (UTCR0_TCE*0) /* Transmit clock Rising-Edge */ #define UTCR0_TrFlEdg (UTCR0_TCE*1) /* Transmit clock Falling-Edge */ #define UTCR0_Ser2IrDA /* Ser. port 2 IrDA settings */ \ - (UTCR0_1StpBit + UTCR0_8BitData) + (UTCR0_1StpBit + UTCR0_8BitData) #define UTCR1_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */ #define UTCR2_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */ - /* fua = fxtl/(16*(BRD[11:0] + 1)) */ - /* Tua = 16*(BRD [11:0] + 1)*Txtl */ + /* fua = fxtl/(16*(BRD[11:0] + 1)) */ + /* Tua = 16*(BRD [11:0] + 1)*Txtl */ #define UTCR1_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ - (((Div) - 16)/16 >> FSize (UTCR2_BRD) << \ - FShft (UTCR1_BRD)) + (((Div) - 16)/16 >> FSize (UTCR2_BRD) << \ + FShft (UTCR1_BRD)) #define UTCR2_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ - (((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \ - FShft (UTCR2_BRD)) - /* fua = fxtl/(16*Floor (Div/16)) */ - /* Tua = 16*Floor (Div/16)*Txtl */ + (((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \ + FShft (UTCR2_BRD)) + /* fua = fxtl/(16*Floor (Div/16)) */ + /* Tua = 16*Floor (Div/16)*Txtl */ #define UTCR1_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ - (((Div) - 1)/16 >> FSize (UTCR2_BRD) << \ - FShft (UTCR1_BRD)) + (((Div) - 1)/16 >> FSize (UTCR2_BRD) << \ + FShft (UTCR1_BRD)) #define UTCR2_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ - (((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \ - FShft (UTCR2_BRD)) - /* fua = fxtl/(16*Ceil (Div/16)) */ - /* Tua = 16*Ceil (Div/16)*Txtl */ + (((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \ + FShft (UTCR2_BRD)) + /* fua = fxtl/(16*Ceil (Div/16)) */ + /* Tua = 16*Ceil (Div/16)*Txtl */ #define UTCR3_RXE 0x00000001 /* Receive Enable */ #define UTCR3_TXE 0x00000002 /* Transmit Enable */ #define UTCR3_BRK 0x00000004 /* BReaK mode */ #define UTCR3_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */ - /* more Interrupt Enable */ + /* more Interrupt Enable */ #define UTCR3_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */ - /* Interrupt Enable */ + /* Interrupt Enable */ #define UTCR3_LBM 0x00000020 /* Look-Back Mode */ #define UTCR3_Ser2IrDA /* Ser. port 2 IrDA settings (RIE, */ \ - /* TIE, LBM can be set or cleared) */ \ - (UTCR3_RXE + UTCR3_TXE) + /* TIE, LBM can be set or cleared) */ \ + (UTCR3_RXE + UTCR3_TXE) #define UTCR4_HSE 0x00000001 /* Hewlett-Packard Serial InfraRed */ - /* (HP-SIR) modulation Enable */ + /* (HP-SIR) modulation Enable */ #define UTCR4_NRZ (UTCR4_HSE*0) /* Non-Return to Zero modulation */ #define UTCR4_HPSIR (UTCR4_HSE*1) /* HP-SIR modulation */ #define UTCR4_LPM 0x00000002 /* Low-Power Mode */ @@ -597,9 +597,9 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #endif /* 0 */ #define UTSR0_TFS 0x00000001 /* Transmit FIFO 1/2-full or less */ - /* Service request (read) */ + /* Service request (read) */ #define UTSR0_RFS 0x00000002 /* Receive FIFO 1/3-to-2/3-full or */ - /* more Service request (read) */ + /* more Service request (read) */ #define UTSR0_RID 0x00000004 /* Receiver IDle */ #define UTSR0_RBB 0x00000008 /* Receive Beginning of Break */ #define UTSR0_REB 0x00000010 /* Receive End of Break */ @@ -651,21 +651,21 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #if LANGUAGE == C #define Ser1SDCR0 /* Ser. port 1 SDLC Control Reg. 0 */ \ - (*((volatile Word *) io_p2v (_Ser1SDCR0))) + (*((volatile Word *) io_p2v (_Ser1SDCR0))) #define Ser1SDCR1 /* Ser. port 1 SDLC Control Reg. 1 */ \ - (*((volatile Word *) io_p2v (_Ser1SDCR1))) + (*((volatile Word *) io_p2v (_Ser1SDCR1))) #define Ser1SDCR2 /* Ser. port 1 SDLC Control Reg. 2 */ \ - (*((volatile Word *) io_p2v (_Ser1SDCR2))) + (*((volatile Word *) io_p2v (_Ser1SDCR2))) #define Ser1SDCR3 /* Ser. port 1 SDLC Control Reg. 3 */ \ - (*((volatile Word *) io_p2v (_Ser1SDCR3))) + (*((volatile Word *) io_p2v (_Ser1SDCR3))) #define Ser1SDCR4 /* Ser. port 1 SDLC Control Reg. 4 */ \ - (*((volatile Word *) io_p2v (_Ser1SDCR4))) + (*((volatile Word *) io_p2v (_Ser1SDCR4))) #define Ser1SDDR /* Ser. port 1 SDLC Data Reg. */ \ - (*((volatile Word *) io_p2v (_Ser1SDDR))) + (*((volatile Word *) io_p2v (_Ser1SDDR))) #define Ser1SDSR0 /* Ser. port 1 SDLC Status Reg. 0 */ \ - (*((volatile Word *) io_p2v (_Ser1SDSR0))) + (*((volatile Word *) io_p2v (_Ser1SDSR0))) #define Ser1SDSR1 /* Ser. port 1 SDLC Status Reg. 1 */ \ - (*((volatile Word *) io_p2v (_Ser1SDSR1))) + (*((volatile Word *) io_p2v (_Ser1SDSR1))) #endif /* LANGUAGE == C */ #define SDCR0_SUS 0x00000001 /* SDLC/UART Select */ @@ -680,7 +680,7 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define SDCR0_NRZ (SDCR0_BMS*1) /* Non-Return to Zero modulation */ #define SDCR0_SCE 0x00000010 /* Sample Clock Enable (GPIO [16]) */ #define SDCR0_SCD 0x00000020 /* Sample Clock Direction select */ - /* (GPIO [16]) */ + /* (GPIO [16]) */ #define SDCR0_SClkIn (SDCR0_SCD*0) /* Sample Clock Input */ #define SDCR0_SClkOut (SDCR0_SCD*1) /* Sample Clock Output */ #define SDCR0_RCE 0x00000040 /* Receive Clock Edge select */ @@ -691,13 +691,13 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define SDCR0_TrFlEdg (SDCR0_TCE*1) /* Transmit clock Falling-Edge */ #define SDCR1_AAF 0x00000001 /* Abort After Frame enable */ - /* (GPIO [17]) */ + /* (GPIO [17]) */ #define SDCR1_TXE 0x00000002 /* Transmit Enable */ #define SDCR1_RXE 0x00000004 /* Receive Enable */ #define SDCR1_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */ - /* more Interrupt Enable */ + /* more Interrupt Enable */ #define SDCR1_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */ - /* Interrupt Enable */ + /* Interrupt Enable */ #define SDCR1_AME 0x00000020 /* Address Match Enable */ #define SDCR1_TUS 0x00000040 /* Transmit FIFO Under-run Select */ #define SDCR1_EFrmURn (SDCR1_TUS*0) /* End Frame on Under-Run */ @@ -708,24 +708,24 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define SDCR3_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */ #define SDCR4_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */ - /* fsd = fxtl/(16*(BRD[11:0] + 1)) */ - /* Tsd = 16*(BRD[11:0] + 1)*Txtl */ + /* fsd = fxtl/(16*(BRD[11:0] + 1)) */ + /* Tsd = 16*(BRD[11:0] + 1)*Txtl */ #define SDCR3_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ - (((Div) - 16)/16 >> FSize (SDCR4_BRD) << \ - FShft (SDCR3_BRD)) + (((Div) - 16)/16 >> FSize (SDCR4_BRD) << \ + FShft (SDCR3_BRD)) #define SDCR4_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ - (((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \ - FShft (SDCR4_BRD)) - /* fsd = fxtl/(16*Floor (Div/16)) */ - /* Tsd = 16*Floor (Div/16)*Txtl */ + (((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \ + FShft (SDCR4_BRD)) + /* fsd = fxtl/(16*Floor (Div/16)) */ + /* Tsd = 16*Floor (Div/16)*Txtl */ #define SDCR3_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ - (((Div) - 1)/16 >> FSize (SDCR4_BRD) << \ - FShft (SDCR3_BRD)) + (((Div) - 1)/16 >> FSize (SDCR4_BRD) << \ + FShft (SDCR3_BRD)) #define SDCR4_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ - (((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \ - FShft (SDCR4_BRD)) - /* fsd = fxtl/(16*Ceil (Div/16)) */ - /* Tsd = 16*Ceil (Div/16)*Txtl */ + (((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \ + FShft (SDCR4_BRD)) + /* fsd = fxtl/(16*Ceil (Div/16)) */ + /* Tsd = 16*Ceil (Div/16)*Txtl */ #define SDDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ #if 0 /* Hidden receive FIFO bits */ @@ -738,9 +738,9 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define SDSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */ #define SDSR0_RAB 0x00000004 /* Receive ABort */ #define SDSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */ - /* Service request (read) */ + /* Service request (read) */ #define SDSR0_RFS 0x00000010 /* Receive FIFO 1/3-to-2/3-full or */ - /* more Service request (read) */ + /* more Service request (read) */ #define SDSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */ #define SDSR1_TBY 0x00000002 /* Transmitter BusY (read) */ @@ -782,17 +782,17 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #if LANGUAGE == C #define Ser2HSCR0 /* Ser. port 2 HSSP Control Reg. 0 */ \ - (*((volatile Word *) io_p2v (_Ser2HSCR0))) + (*((volatile Word *) io_p2v (_Ser2HSCR0))) #define Ser2HSCR1 /* Ser. port 2 HSSP Control Reg. 1 */ \ - (*((volatile Word *) io_p2v (_Ser2HSCR1))) + (*((volatile Word *) io_p2v (_Ser2HSCR1))) #define Ser2HSDR /* Ser. port 2 HSSP Data Reg. */ \ - (*((volatile Word *) io_p2v (_Ser2HSDR))) + (*((volatile Word *) io_p2v (_Ser2HSDR))) #define Ser2HSSR0 /* Ser. port 2 HSSP Status Reg. 0 */ \ - (*((volatile Word *) io_p2v (_Ser2HSSR0))) + (*((volatile Word *) io_p2v (_Ser2HSSR0))) #define Ser2HSSR1 /* Ser. port 2 HSSP Status Reg. 1 */ \ - (*((volatile Word *) io_p2v (_Ser2HSSR1))) + (*((volatile Word *) io_p2v (_Ser2HSSR1))) #define Ser2HSCR2 /* Ser. port 2 HSSP Control Reg. 2 */ \ - (*((volatile Word *) io_p2v (_Ser2HSCR2))) + (*((volatile Word *) io_p2v (_Ser2HSCR2))) #endif /* LANGUAGE == C */ #define HSCR0_ITR 0x00000001 /* IrDA Transmission Rate */ @@ -805,9 +805,9 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define HSCR0_TXE 0x00000008 /* Transmit Enable */ #define HSCR0_RXE 0x00000010 /* Receive Enable */ #define HSCR0_RIE 0x00000020 /* Receive FIFO 2/5-to-3/5-full or */ - /* more Interrupt Enable */ + /* more Interrupt Enable */ #define HSCR0_TIE 0x00000040 /* Transmit FIFO 1/2-full or less */ - /* Interrupt Enable */ + /* Interrupt Enable */ #define HSCR0_AME 0x00000080 /* Address Match Enable */ #define HSCR1_AMV Fld (8, 0) /* Address Match Value */ @@ -823,9 +823,9 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define HSSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */ #define HSSR0_RAB 0x00000004 /* Receive ABort */ #define HSSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */ - /* Service request (read) */ + /* Service request (read) */ #define HSSR0_RFS 0x00000010 /* Receive FIFO 2/5-to-3/5-full or */ - /* more Service request (read) */ + /* more Service request (read) */ #define HSSR0_FRE 0x00000020 /* receive FRaming Error */ #define HSSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */ @@ -838,14 +838,14 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define HSCR2_TXP 0x00040000 /* Transmit data Polarity (TXD_2) */ #define HSCR2_TrDataL (HSCR2_TXP*0) /* Transmit Data active Low */ - /* (inverted) */ + /* (inverted) */ #define HSCR2_TrDataH (HSCR2_TXP*1) /* Transmit Data active High */ - /* (non-inverted) */ + /* (non-inverted) */ #define HSCR2_RXP 0x00080000 /* Receive data Polarity (RXD_2) */ #define HSCR2_RcDataL (HSCR2_RXP*0) /* Receive Data active Low */ - /* (inverted) */ + /* (inverted) */ #define HSCR2_RcDataH (HSCR2_RXP*1) /* Receive Data active High */ - /* (non-inverted) */ + /* (non-inverted) */ /* @@ -877,87 +877,87 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define _Ser4MCCR0 0x80060000 /* Ser. port 4 MCP Control Reg. 0 */ #define _Ser4MCDR0 0x80060008 /* Ser. port 4 MCP Data Reg. 0 */ - /* (audio) */ + /* (audio) */ #define _Ser4MCDR1 0x8006000C /* Ser. port 4 MCP Data Reg. 1 */ - /* (telecom) */ + /* (telecom) */ #define _Ser4MCDR2 0x80060010 /* Ser. port 4 MCP Data Reg. 2 */ - /* (CODEC reg.) */ + /* (CODEC reg.) */ #define _Ser4MCSR 0x80060018 /* Ser. port 4 MCP Status Reg. */ #define _Ser4MCCR1 0x90060030 /* Ser. port 4 MCP Control Reg. 1 */ #if LANGUAGE == C #define Ser4MCCR0 /* Ser. port 4 MCP Control Reg. 0 */ \ - (*((volatile Word *) io_p2v (_Ser4MCCR0))) + (*((volatile Word *) io_p2v (_Ser4MCCR0))) #define Ser4MCDR0 /* Ser. port 4 MCP Data Reg. 0 */ \ - /* (audio) */ \ - (*((volatile Word *) io_p2v (_Ser4MCDR0))) + /* (audio) */ \ + (*((volatile Word *) io_p2v (_Ser4MCDR0))) #define Ser4MCDR1 /* Ser. port 4 MCP Data Reg. 1 */ \ - /* (telecom) */ \ - (*((volatile Word *) io_p2v (_Ser4MCDR1))) + /* (telecom) */ \ + (*((volatile Word *) io_p2v (_Ser4MCDR1))) #define Ser4MCDR2 /* Ser. port 4 MCP Data Reg. 2 */ \ - /* (CODEC reg.) */ \ - (*((volatile Word *) io_p2v (_Ser4MCDR2))) + /* (CODEC reg.) */ \ + (*((volatile Word *) io_p2v (_Ser4MCDR2))) #define Ser4MCSR /* Ser. port 4 MCP Status Reg. */ \ - (*((volatile Word *) io_p2v (_Ser4MCSR))) + (*((volatile Word *) io_p2v (_Ser4MCSR))) #define Ser4MCCR1 /* Ser. port 4 MCP Control Reg. 1 */ \ - (*((volatile Word *) io_p2v (_Ser4MCCR1))) + (*((volatile Word *) io_p2v (_Ser4MCCR1))) #endif /* LANGUAGE == C */ #define MCCR0_ASD Fld (7, 0) /* Audio Sampling rate Divisor/32 */ - /* [6..127] */ - /* faud = fmc/(32*ASD) */ - /* Taud = 32*ASD*Tmc */ + /* [6..127] */ + /* faud = fmc/(32*ASD) */ + /* Taud = 32*ASD*Tmc */ #define MCCR0_AudSmpDiv(Div) /* Audio Sampling rate Divisor */ \ - /* [192..4064] */ \ - ((Div)/32 << FShft (MCCR0_ASD)) - /* faud = fmc/(32*Floor (Div/32)) */ - /* Taud = 32*Floor (Div/32)*Tmc */ + /* [192..4064] */ \ + ((Div)/32 << FShft (MCCR0_ASD)) + /* faud = fmc/(32*Floor (Div/32)) */ + /* Taud = 32*Floor (Div/32)*Tmc */ #define MCCR0_CeilAudSmpDiv(Div) /* Ceil. of AudSmpDiv [192..4064] */ \ - (((Div) + 31)/32 << FShft (MCCR0_ASD)) - /* faud = fmc/(32*Ceil (Div/32)) */ - /* Taud = 32*Ceil (Div/32)*Tmc */ + (((Div) + 31)/32 << FShft (MCCR0_ASD)) + /* faud = fmc/(32*Ceil (Div/32)) */ + /* Taud = 32*Ceil (Div/32)*Tmc */ #define MCCR0_TSD Fld (7, 8) /* Telecom Sampling rate */ - /* Divisor/32 [16..127] */ - /* ftcm = fmc/(32*TSD) */ - /* Ttcm = 32*TSD*Tmc */ + /* Divisor/32 [16..127] */ + /* ftcm = fmc/(32*TSD) */ + /* Ttcm = 32*TSD*Tmc */ #define MCCR0_TcmSmpDiv(Div) /* Telecom Sampling rate Divisor */ \ - /* [512..4064] */ \ - ((Div)/32 << FShft (MCCR0_TSD)) - /* ftcm = fmc/(32*Floor (Div/32)) */ - /* Ttcm = 32*Floor (Div/32)*Tmc */ + /* [512..4064] */ \ + ((Div)/32 << FShft (MCCR0_TSD)) + /* ftcm = fmc/(32*Floor (Div/32)) */ + /* Ttcm = 32*Floor (Div/32)*Tmc */ #define MCCR0_CeilTcmSmpDiv(Div) /* Ceil. of TcmSmpDiv [512..4064] */ \ - (((Div) + 31)/32 << FShft (MCCR0_TSD)) - /* ftcm = fmc/(32*Ceil (Div/32)) */ - /* Ttcm = 32*Ceil (Div/32)*Tmc */ + (((Div) + 31)/32 << FShft (MCCR0_TSD)) + /* ftcm = fmc/(32*Ceil (Div/32)) */ + /* Ttcm = 32*Ceil (Div/32)*Tmc */ #define MCCR0_MCE 0x00010000 /* MCP Enable */ #define MCCR0_ECS 0x00020000 /* External Clock Select */ #define MCCR0_IntClk (MCCR0_ECS*0) /* Internal Clock (10 or 12 MHz) */ #define MCCR0_ExtClk (MCCR0_ECS*1) /* External Clock (GPIO [21]) */ #define MCCR0_ADM 0x00040000 /* A/D (audio/telecom) data */ - /* sampling/storing Mode */ + /* sampling/storing Mode */ #define MCCR0_VldBit (MCCR0_ADM*0) /* Valid Bit storing mode */ #define MCCR0_SmpCnt (MCCR0_ADM*1) /* Sampling Counter storing mode */ #define MCCR0_TTE 0x00080000 /* Telecom Transmit FIFO 1/2-full */ - /* or less interrupt Enable */ + /* or less interrupt Enable */ #define MCCR0_TRE 0x00100000 /* Telecom Receive FIFO 1/2-full */ - /* or more interrupt Enable */ + /* or more interrupt Enable */ #define MCCR0_ATE 0x00200000 /* Audio Transmit FIFO 1/2-full */ - /* or less interrupt Enable */ + /* or less interrupt Enable */ #define MCCR0_ARE 0x00400000 /* Audio Receive FIFO 1/2-full or */ - /* more interrupt Enable */ + /* more interrupt Enable */ #define MCCR0_LBM 0x00800000 /* Look-Back Mode */ #define MCCR0_ECP Fld (2, 24) /* External Clock Prescaler - 1 */ #define MCCR0_ExtClkDiv(Div) /* External Clock Divisor [1..4] */ \ - (((Div) - 1) << FShft (MCCR0_ECP)) + (((Div) - 1) << FShft (MCCR0_ECP)) #define MCDR0_DATA Fld (12, 4) /* receive/transmit audio DATA */ - /* FIFOs */ + /* FIFOs */ #define MCDR1_DATA Fld (14, 2) /* receive/transmit telecom DATA */ - /* FIFOs */ + /* FIFOs */ - /* receive/transmit CODEC reg. */ - /* FIFOs: */ + /* receive/transmit CODEC reg. */ + /* FIFOs: */ #define MCDR2_DATA Fld (16, 0) /* reg. DATA */ #define MCDR2_RW 0x00010000 /* reg. Read/Write (transmit) */ #define MCDR2_Rd (MCDR2_RW*0) /* reg. Read */ @@ -965,37 +965,37 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define MCDR2_ADD Fld (4, 17) /* reg. ADDress */ #define MCSR_ATS 0x00000001 /* Audio Transmit FIFO 1/2-full */ - /* or less Service request (read) */ + /* or less Service request (read) */ #define MCSR_ARS 0x00000002 /* Audio Receive FIFO 1/2-full or */ - /* more Service request (read) */ + /* more Service request (read) */ #define MCSR_TTS 0x00000004 /* Telecom Transmit FIFO 1/2-full */ - /* or less Service request (read) */ + /* or less Service request (read) */ #define MCSR_TRS 0x00000008 /* Telecom Receive FIFO 1/2-full */ - /* or more Service request (read) */ + /* or more Service request (read) */ #define MCSR_ATU 0x00000010 /* Audio Transmit FIFO Under-run */ #define MCSR_ARO 0x00000020 /* Audio Receive FIFO Over-run */ #define MCSR_TTU 0x00000040 /* Telecom Transmit FIFO Under-run */ #define MCSR_TRO 0x00000080 /* Telecom Receive FIFO Over-run */ #define MCSR_ANF 0x00000100 /* Audio transmit FIFO Not Full */ - /* (read) */ + /* (read) */ #define MCSR_ANE 0x00000200 /* Audio receive FIFO Not Empty */ - /* (read) */ + /* (read) */ #define MCSR_TNF 0x00000400 /* Telecom transmit FIFO Not Full */ - /* (read) */ + /* (read) */ #define MCSR_TNE 0x00000800 /* Telecom receive FIFO Not Empty */ - /* (read) */ + /* (read) */ #define MCSR_CWC 0x00001000 /* CODEC register Write Completed */ - /* (read) */ + /* (read) */ #define MCSR_CRC 0x00002000 /* CODEC register Read Completed */ - /* (read) */ + /* (read) */ #define MCSR_ACE 0x00004000 /* Audio CODEC Enabled (read) */ #define MCSR_TCE 0x00008000 /* Telecom CODEC Enabled (read) */ #define MCCR1_CFS 0x00100000 /* Clock Freq. Select */ #define MCCR1_F12MHz (MCCR1_CFS*0) /* Freq. (fmc) = ~ 12 MHz */ - /* (11.981 MHz) */ + /* (11.981 MHz) */ #define MCCR1_F10MHz (MCCR1_CFS*1) /* Freq. (fmc) = ~ 10 MHz */ - /* (9.585 MHz) */ + /* (9.585 MHz) */ /* @@ -1026,53 +1026,53 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #if LANGUAGE == C #define Ser4SSCR0 /* Ser. port 4 SSP Control Reg. 0 */ \ - (*((volatile Word *) io_p2v (_Ser4SSCR0))) + (*((volatile Word *) io_p2v (_Ser4SSCR0))) #define Ser4SSCR1 /* Ser. port 4 SSP Control Reg. 1 */ \ - (*((volatile Word *) io_p2v (_Ser4SSCR1))) + (*((volatile Word *) io_p2v (_Ser4SSCR1))) #define Ser4SSDR /* Ser. port 4 SSP Data Reg. */ \ - (*((volatile Word *) io_p2v (_Ser4SSDR))) + (*((volatile Word *) io_p2v (_Ser4SSDR))) #define Ser4SSSR /* Ser. port 4 SSP Status Reg. */ \ - (*((volatile Word *) io_p2v (_Ser4SSSR))) + (*((volatile Word *) io_p2v (_Ser4SSSR))) #endif /* LANGUAGE == C */ #define SSCR0_DSS Fld (4, 0) /* Data Size - 1 Select [3..15] */ #define SSCR0_DataSize(Size) /* Data Size Select [4..16] */ \ - (((Size) - 1) << FShft (SSCR0_DSS)) + (((Size) - 1) << FShft (SSCR0_DSS)) #define SSCR0_FRF Fld (2, 4) /* FRame Format */ #define SSCR0_Motorola /* Motorola Serial Peripheral */ \ - /* Interface (SPI) format */ \ - (0 << FShft (SSCR0_FRF)) + /* Interface (SPI) format */ \ + (0 << FShft (SSCR0_FRF)) #define SSCR0_TI /* Texas Instruments Synchronous */ \ - /* Serial format */ \ - (1 << FShft (SSCR0_FRF)) + /* Serial format */ \ + (1 << FShft (SSCR0_FRF)) #define SSCR0_National /* National Microwire format */ \ - (2 << FShft (SSCR0_FRF)) + (2 << FShft (SSCR0_FRF)) #define SSCR0_SSE 0x00000080 /* SSP Enable */ #define SSCR0_SCR Fld (8, 8) /* Serial Clock Rate divisor/2 - 1 */ - /* fss = fxtl/(2*(SCR + 1)) */ - /* Tss = 2*(SCR + 1)*Txtl */ + /* fss = fxtl/(2*(SCR + 1)) */ + /* Tss = 2*(SCR + 1)*Txtl */ #define SSCR0_SerClkDiv(Div) /* Serial Clock Divisor [2..512] */ \ - (((Div) - 2)/2 << FShft (SSCR0_SCR)) - /* fss = fxtl/(2*Floor (Div/2)) */ - /* Tss = 2*Floor (Div/2)*Txtl */ + (((Div) - 2)/2 << FShft (SSCR0_SCR)) + /* fss = fxtl/(2*Floor (Div/2)) */ + /* Tss = 2*Floor (Div/2)*Txtl */ #define SSCR0_CeilSerClkDiv(Div) /* Ceil. of SerClkDiv [2..512] */ \ - (((Div) - 1)/2 << FShft (SSCR0_SCR)) - /* fss = fxtl/(2*Ceil (Div/2)) */ - /* Tss = 2*Ceil (Div/2)*Txtl */ + (((Div) - 1)/2 << FShft (SSCR0_SCR)) + /* fss = fxtl/(2*Ceil (Div/2)) */ + /* Tss = 2*Ceil (Div/2)*Txtl */ #define SSCR1_RIE 0x00000001 /* Receive FIFO 1/2-full or more */ - /* Interrupt Enable */ + /* Interrupt Enable */ #define SSCR1_TIE 0x00000002 /* Transmit FIFO 1/2-full or less */ - /* Interrupt Enable */ + /* Interrupt Enable */ #define SSCR1_LBM 0x00000004 /* Look-Back Mode */ #define SSCR1_SPO 0x00000008 /* Sample clock (SCLK) POlarity */ #define SSCR1_SClkIactL (SSCR1_SPO*0) /* Sample Clock Inactive Low */ #define SSCR1_SClkIactH (SSCR1_SPO*1) /* Sample Clock Inactive High */ #define SSCR1_SP 0x00000010 /* Sample clock (SCLK) Phase */ #define SSCR1_SClk1P (SSCR1_SP*0) /* Sample Clock active 1 Period */ - /* after frame (SFRM, 1st edge) */ + /* after frame (SFRM, 1st edge) */ #define SSCR1_SClk1_2P (SSCR1_SP*1) /* Sample Clock active 1/2 Period */ - /* after frame (SFRM, 1st edge) */ + /* after frame (SFRM, 1st edge) */ #define SSCR1_ECS 0x00000020 /* External Clock Select */ #define SSCR1_IntClk (SSCR1_ECS*0) /* Internal Clock */ #define SSCR1_ExtClk (SSCR1_ECS*1) /* External Clock (GPIO [19]) */ @@ -1083,9 +1083,9 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define SSSR_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ #define SSSR_BSY 0x00000008 /* SSP BuSY (read) */ #define SSSR_TFS 0x00000010 /* Transmit FIFO 1/2-full or less */ - /* Service request (read) */ + /* Service request (read) */ #define SSSR_RFS 0x00000020 /* Receive FIFO 1/2-full or more */ - /* Service request (read) */ + /* Service request (read) */ #define SSSR_ROR 0x00000040 /* Receive FIFO Over-Run */ @@ -1112,7 +1112,7 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; */ #define _OSMR(Nb) /* OS timer Match Reg. [0..3] */ \ - (0x90000000 + (Nb)*4) + (0x90000000 + (Nb)*4) #define _OSMR0 _OSMR (0) /* OS timer Match Reg. 0 */ #define _OSMR1 _OSMR (1) /* OS timer Match Reg. 1 */ #define _OSMR2 _OSMR (2) /* OS timer Match Reg. 2 */ @@ -1124,33 +1124,33 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #if LANGUAGE == C #define OSMR /* OS timer Match Reg. [0..3] */ \ - ((volatile Word *) io_p2v (_OSMR (0))) + ((volatile Word *) io_p2v (_OSMR (0))) #define OSMR0 (OSMR [0]) /* OS timer Match Reg. 0 */ #define OSMR1 (OSMR [1]) /* OS timer Match Reg. 1 */ #define OSMR2 (OSMR [2]) /* OS timer Match Reg. 2 */ #define OSMR3 (OSMR [3]) /* OS timer Match Reg. 3 */ #define OSCR /* OS timer Counter Reg. */ \ - (*((volatile Word *) io_p2v (_OSCR))) + (*((volatile Word *) io_p2v (_OSCR))) #define OSSR /* OS timer Status Reg. */ \ - (*((volatile Word *) io_p2v (_OSSR))) + (*((volatile Word *) io_p2v (_OSSR))) #define OWER /* OS timer Watch-dog Enable Reg. */ \ - (*((volatile Word *) io_p2v (_OWER))) + (*((volatile Word *) io_p2v (_OWER))) #define OIER /* OS timer Interrupt Enable Reg. */ \ - (*((volatile Word *) io_p2v (_OIER))) + (*((volatile Word *) io_p2v (_OIER))) #endif /* LANGUAGE == C */ #define OSSR_M(Nb) /* Match detected [0..3] */ \ - (0x00000001 << (Nb)) + (0x00000001 << (Nb)) #define OSSR_M0 OSSR_M (0) /* Match detected 0 */ #define OSSR_M1 OSSR_M (1) /* Match detected 1 */ #define OSSR_M2 OSSR_M (2) /* Match detected 2 */ #define OSSR_M3 OSSR_M (3) /* Match detected 3 */ #define OWER_WME 0x00000001 /* Watch-dog Match Enable */ - /* (set only) */ + /* (set only) */ #define OIER_E(Nb) /* match interrupt Enable [0..3] */ \ - (0x00000001 << (Nb)) + (0x00000001 << (Nb)) #define OIER_E0 OIER_E (0) /* match interrupt Enable 0 */ #define OIER_E1 OIER_E (1) /* match interrupt Enable 1 */ #define OIER_E2 OIER_E (2) /* match interrupt Enable 2 */ @@ -1180,21 +1180,21 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #if LANGUAGE == C #define RTAR /* RTC Alarm Reg. */ \ - (*((volatile Word *) io_p2v (_RTAR))) + (*((volatile Word *) io_p2v (_RTAR))) #define RCNR /* RTC CouNt Reg. */ \ - (*((volatile Word *) io_p2v (_RCNR))) + (*((volatile Word *) io_p2v (_RCNR))) #define RTTR /* RTC Trim Reg. */ \ - (*((volatile Word *) io_p2v (_RTTR))) + (*((volatile Word *) io_p2v (_RTTR))) #define RTSR /* RTC Status Reg. */ \ - (*((volatile Word *) io_p2v (_RTSR))) + (*((volatile Word *) io_p2v (_RTSR))) #endif /* LANGUAGE == C */ #define RTTR_C Fld (16, 0) /* clock divider Count - 1 */ #define RTTR_D Fld (10, 16) /* trim Delete count */ - /* frtc = (1023*(C + 1) - D)*frtx/ */ - /* (1023*(C + 1)^2) */ - /* Trtc = (1023*(C + 1)^2)*Trtx/ */ - /* (1023*(C + 1) - D) */ + /* frtc = (1023*(C + 1) - D)*frtx/ */ + /* (1023*(C + 1)^2) */ + /* Trtc = (1023*(C + 1)^2)*Trtx/ */ + /* (1023*(C + 1) - D) */ #define RTSR_AL 0x00000001 /* ALarm detected */ #define RTSR_HZ 0x00000002 /* 1 Hz clock detected */ @@ -1236,21 +1236,21 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #if LANGUAGE == C #define PMCR /* PM Control Reg. */ \ - (*((volatile Word *) io_p2v (_PMCR))) + (*((volatile Word *) io_p2v (_PMCR))) #define PSSR /* PM Sleep Status Reg. */ \ - (*((volatile Word *) io_p2v (_PSSR))) + (*((volatile Word *) io_p2v (_PSSR))) #define PSPR /* PM Scratch-Pad Reg. */ \ - (*((volatile Word *) io_p2v (_PSPR))) + (*((volatile Word *) io_p2v (_PSPR))) #define PWER /* PM Wake-up Enable Reg. */ \ - (*((volatile Word *) io_p2v (_PWER))) + (*((volatile Word *) io_p2v (_PWER))) #define PCFR /* PM general ConFiguration Reg. */ \ - (*((volatile Word *) io_p2v (_PCFR))) + (*((volatile Word *) io_p2v (_PCFR))) #define PPCR /* PM PLL Configuration Reg. */ \ - (*((volatile Word *) io_p2v (_PPCR))) + (*((volatile Word *) io_p2v (_PPCR))) #define PGSR /* PM GPIO Sleep state Reg. */ \ - (*((volatile Word *) io_p2v (_PGSR))) + (*((volatile Word *) io_p2v (_PGSR))) #define POSR /* PM Oscillator Status Reg. */ \ - (*((volatile Word *) io_p2v (_POSR))) + (*((volatile Word *) io_p2v (_POSR))) #elif LANGUAGE == Assembly #define PMCR (io_p2v (_PMCR)) @@ -1268,7 +1268,7 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define PSSR_SS 0x00000001 /* Software Sleep */ #define PSSR_BFS 0x00000002 /* Battery Fault Status */ - /* (BATT_FAULT) */ + /* (BATT_FAULT) */ #define PSSR_VFS 0x00000004 /* Vdd Fault Status (VDD_FAULT) */ #define PSSR_DH 0x00000008 /* DRAM control Hold */ #define PSSR_PH 0x00000010 /* Peripheral control Hold */ @@ -1314,42 +1314,42 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define PCFR_StMemNeg (PCFR_FS*0) /* Static Memory pins Negated (1) */ #define PCFR_StMemFlt (PCFR_FS*1) /* Static Memory pins Floating */ #define PCFR_FO 0x00000008 /* Force RTC oscillator */ - /* (32.768 kHz) enable On */ + /* (32.768 kHz) enable On */ #define PPCR_CCF Fld (5, 0) /* CPU core Clock (CCLK) Freq. */ #define PPCR_Fx16 /* Freq. x 16 (fcpu = 16*fxtl) */ \ - (0x00 << FShft (PPCR_CCF)) + (0x00 << FShft (PPCR_CCF)) #define PPCR_Fx20 /* Freq. x 20 (fcpu = 20*fxtl) */ \ - (0x01 << FShft (PPCR_CCF)) + (0x01 << FShft (PPCR_CCF)) #define PPCR_Fx24 /* Freq. x 24 (fcpu = 24*fxtl) */ \ - (0x02 << FShft (PPCR_CCF)) + (0x02 << FShft (PPCR_CCF)) #define PPCR_Fx28 /* Freq. x 28 (fcpu = 28*fxtl) */ \ - (0x03 << FShft (PPCR_CCF)) + (0x03 << FShft (PPCR_CCF)) #define PPCR_Fx32 /* Freq. x 32 (fcpu = 32*fxtl) */ \ - (0x04 << FShft (PPCR_CCF)) + (0x04 << FShft (PPCR_CCF)) #define PPCR_Fx36 /* Freq. x 36 (fcpu = 36*fxtl) */ \ - (0x05 << FShft (PPCR_CCF)) + (0x05 << FShft (PPCR_CCF)) #define PPCR_Fx40 /* Freq. x 40 (fcpu = 40*fxtl) */ \ - (0x06 << FShft (PPCR_CCF)) + (0x06 << FShft (PPCR_CCF)) #define PPCR_Fx44 /* Freq. x 44 (fcpu = 44*fxtl) */ \ - (0x07 << FShft (PPCR_CCF)) + (0x07 << FShft (PPCR_CCF)) #define PPCR_Fx48 /* Freq. x 48 (fcpu = 48*fxtl) */ \ - (0x08 << FShft (PPCR_CCF)) + (0x08 << FShft (PPCR_CCF)) #define PPCR_Fx52 /* Freq. x 52 (fcpu = 52*fxtl) */ \ - (0x09 << FShft (PPCR_CCF)) + (0x09 << FShft (PPCR_CCF)) #define PPCR_Fx56 /* Freq. x 56 (fcpu = 56*fxtl) */ \ - (0x0A << FShft (PPCR_CCF)) + (0x0A << FShft (PPCR_CCF)) #define PPCR_Fx60 /* Freq. x 60 (fcpu = 60*fxtl) */ \ - (0x0B << FShft (PPCR_CCF)) + (0x0B << FShft (PPCR_CCF)) #define PPCR_Fx64 /* Freq. x 64 (fcpu = 64*fxtl) */ \ - (0x0C << FShft (PPCR_CCF)) + (0x0C << FShft (PPCR_CCF)) #define PPCR_Fx68 /* Freq. x 68 (fcpu = 68*fxtl) */ \ - (0x0D << FShft (PPCR_CCF)) + (0x0D << FShft (PPCR_CCF)) #define PPCR_Fx72 /* Freq. x 72 (fcpu = 72*fxtl) */ \ - (0x0E << FShft (PPCR_CCF)) + (0x0E << FShft (PPCR_CCF)) #define PPCR_Fx76 /* Freq. x 76 (fcpu = 76*fxtl) */ \ - (0x0F << FShft (PPCR_CCF)) - /* 3.6864 MHz crystal (fxtl): */ + (0x0F << FShft (PPCR_CCF)) + /* 3.6864 MHz crystal (fxtl): */ #define PPCR_F59_0MHz PPCR_Fx16 /* Freq. (fcpu) = 59.0 MHz */ #define PPCR_F73_7MHz PPCR_Fx20 /* Freq. (fcpu) = 73.7 MHz */ #define PPCR_F88_5MHz PPCR_Fx24 /* Freq. (fcpu) = 88.5 MHz */ @@ -1366,7 +1366,7 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define PPCR_F250_7MHz PPCR_Fx68 /* Freq. (fcpu) = 250.7 MHz */ #define PPCR_F265_4MHz PPCR_Fx72 /* Freq. (fcpu) = 265.4 MHz */ #define PPCR_F280_2MHz PPCR_Fx76 /* Freq. (fcpu) = 280.2 MHz */ - /* 3.5795 MHz crystal (fxtl): */ + /* 3.5795 MHz crystal (fxtl): */ #define PPCR_F57_3MHz PPCR_Fx16 /* Freq. (fcpu) = 57.3 MHz */ #define PPCR_F71_6MHz PPCR_Fx20 /* Freq. (fcpu) = 71.6 MHz */ #define PPCR_F85_9MHz PPCR_Fx24 /* Freq. (fcpu) = 85.9 MHz */ @@ -1401,9 +1401,9 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #if LANGUAGE == C #define RSRR /* RC Software Reset Reg. */ \ - (*((volatile Word *) io_p2v (_RSRR))) + (*((volatile Word *) io_p2v (_RSRR))) #define RCSR /* RC Status Reg. */ \ - (*((volatile Word *) io_p2v (_RCSR))) + (*((volatile Word *) io_p2v (_RCSR))) #endif /* LANGUAGE == C */ #define RSRR_SWR 0x00000001 /* SoftWare Reset (set only) */ @@ -1425,18 +1425,18 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #if LANGUAGE == C #define TUCR /* Test Unit Control Reg. */ \ - (*((volatile Word *) io_p2v (_TUCR))) + (*((volatile Word *) io_p2v (_TUCR))) #endif /* LANGUAGE == C */ #define TUCR_TIC 0x00000040 /* TIC mode */ #define TUCR_TTST 0x00000080 /* Trim TeST mode */ #define TUCR_RCRC 0x00000100 /* Richard's Cyclic Redundancy */ - /* Check */ + /* Check */ #define TUCR_PMD 0x00000200 /* Power Management Disable */ #define TUCR_MR 0x00000400 /* Memory Request mode */ #define TUCR_NoMB (TUCR_MR*0) /* No Memory Bus request & grant */ #define TUCR_MBGPIO (TUCR_MR*1) /* Memory Bus request (MBREQ) & */ - /* grant (MBGNT) on GPIO [22:21] */ + /* grant (MBGNT) on GPIO [22:21] */ #define TUCR_CTB Fld (3, 20) /* Clock Test Bits */ #define TUCR_FDC 0x00800000 /* RTC Force Delete Count */ #define TUCR_FMC 0x01000000 /* Force Michelle's Control mode */ @@ -1444,23 +1444,23 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define TUCR_DPS 0x04000000 /* Disallow Pad Sleep */ #define TUCR_TSEL Fld (3, 29) /* clock Test SELect on GPIO [27] */ #define TUCR_32_768kHz /* 32.768 kHz osc. on GPIO [27] */ \ - (0 << FShft (TUCR_TSEL)) + (0 << FShft (TUCR_TSEL)) #define TUCR_3_6864MHz /* 3.6864 MHz osc. on GPIO [27] */ \ - (1 << FShft (TUCR_TSEL)) + (1 << FShft (TUCR_TSEL)) #define TUCR_VDD /* VDD ring osc./16 on GPIO [27] */ \ - (2 << FShft (TUCR_TSEL)) + (2 << FShft (TUCR_TSEL)) #define TUCR_96MHzPLL /* 96 MHz PLL/4 on GPIO [27] */ \ - (3 << FShft (TUCR_TSEL)) + (3 << FShft (TUCR_TSEL)) #define TUCR_Clock /* internal (fcpu/2) & 32.768 kHz */ \ - /* Clocks on GPIO [26:27] */ \ - (4 << FShft (TUCR_TSEL)) + /* Clocks on GPIO [26:27] */ \ + (4 << FShft (TUCR_TSEL)) #define TUCR_3_6864MHzA /* 3.6864 MHz osc. on GPIO [27] */ \ - /* (Alternative) */ \ - (5 << FShft (TUCR_TSEL)) + /* (Alternative) */ \ + (5 << FShft (TUCR_TSEL)) #define TUCR_MainPLL /* Main PLL/16 on GPIO [27] */ \ - (6 << FShft (TUCR_TSEL)) + (6 << FShft (TUCR_TSEL)) #define TUCR_VDDL /* VDDL ring osc./4 on GPIO [27] */ \ - (7 << FShft (TUCR_TSEL)) + (7 << FShft (TUCR_TSEL)) /* @@ -1499,21 +1499,21 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #if LANGUAGE == C #define GPLR /* GPIO Pin Level Reg. */ \ - (*((volatile Word *) io_p2v (_GPLR))) + (*((volatile Word *) io_p2v (_GPLR))) #define GPDR /* GPIO Pin Direction Reg. */ \ - (*((volatile Word *) io_p2v (_GPDR))) + (*((volatile Word *) io_p2v (_GPDR))) #define GPSR /* GPIO Pin output Set Reg. */ \ - (*((volatile Word *) io_p2v (_GPSR))) + (*((volatile Word *) io_p2v (_GPSR))) #define GPCR /* GPIO Pin output Clear Reg. */ \ - (*((volatile Word *) io_p2v (_GPCR))) + (*((volatile Word *) io_p2v (_GPCR))) #define GRER /* GPIO Rising-Edge detect Reg. */ \ - (*((volatile Word *) io_p2v (_GRER))) + (*((volatile Word *) io_p2v (_GRER))) #define GFER /* GPIO Falling-Edge detect Reg. */ \ - (*((volatile Word *) io_p2v (_GFER))) + (*((volatile Word *) io_p2v (_GFER))) #define GEDR /* GPIO Edge Detect status Reg. */ \ - (*((volatile Word *) io_p2v (_GEDR))) + (*((volatile Word *) io_p2v (_GEDR))) #define GAFR /* GPIO Alternate Function Reg. */ \ - (*((volatile Word *) io_p2v (_GAFR))) + (*((volatile Word *) io_p2v (_GAFR))) #elif LANGUAGE == Assembly #define GPLR (io_p2v (_GPLR)) @@ -1531,7 +1531,7 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define GPIO_MAX (27) #define GPIO_GPIO(Nb) /* GPIO [0..27] */ \ - (0x00000001 << (Nb)) + (0x00000001 << (Nb)) #define GPIO_GPIO0 GPIO_GPIO (0) /* GPIO [0] */ #define GPIO_GPIO1 GPIO_GPIO (1) /* GPIO [1] */ #define GPIO_GPIO2 GPIO_GPIO (2) /* GPIO [2] */ @@ -1562,7 +1562,7 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define GPIO_GPIO27 GPIO_GPIO (27) /* GPIO [27] */ #define GPIO_LDD(Nb) /* LCD Data [8..15] (O) */ \ - GPIO_GPIO ((Nb) - 6) + GPIO_GPIO ((Nb) - 6) #define GPIO_LDD8 GPIO_LDD (8) /* LCD Data [8] (O) */ #define GPIO_LDD9 GPIO_LDD (9) /* LCD Data [9] (O) */ #define GPIO_LDD10 GPIO_LDD (10) /* LCD Data [10] (O) */ @@ -1571,24 +1571,24 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define GPIO_LDD13 GPIO_LDD (13) /* LCD Data [13] (O) */ #define GPIO_LDD14 GPIO_LDD (14) /* LCD Data [14] (O) */ #define GPIO_LDD15 GPIO_LDD (15) /* LCD Data [15] (O) */ - /* ser. port 4: */ + /* ser. port 4: */ #define GPIO_SSP_TXD GPIO_GPIO (10) /* SSP Transmit Data (O) */ #define GPIO_SSP_RXD GPIO_GPIO (11) /* SSP Receive Data (I) */ #define GPIO_SSP_SCLK GPIO_GPIO (12) /* SSP Sample CLocK (O) */ #define GPIO_SSP_SFRM GPIO_GPIO (13) /* SSP Sample FRaMe (O) */ - /* ser. port 1: */ + /* ser. port 1: */ #define GPIO_UART_TXD GPIO_GPIO (14) /* UART Transmit Data (O) */ #define GPIO_UART_RXD GPIO_GPIO (15) /* UART Receive Data (I) */ #define GPIO_SDLC_SCLK GPIO_GPIO (16) /* SDLC Sample CLocK (I/O) */ #define GPIO_SDLC_AAF GPIO_GPIO (17) /* SDLC Abort After Frame (O) */ #define GPIO_UART_SCLK1 GPIO_GPIO (18) /* UART Sample CLocK 1 (I) */ - /* ser. port 4: */ + /* ser. port 4: */ #define GPIO_SSP_CLK GPIO_GPIO (19) /* SSP external CLocK (I) */ - /* ser. port 3: */ + /* ser. port 3: */ #define GPIO_UART_SCLK3 GPIO_GPIO (20) /* UART Sample CLocK 3 (I) */ - /* ser. port 4: */ + /* ser. port 4: */ #define GPIO_MCP_CLK GPIO_GPIO (21) /* MCP CLocK (I) */ - /* test controller: */ + /* test controller: */ #define GPIO_TIC_ACK GPIO_GPIO (21) /* TIC ACKnowledge (O) */ #define GPIO_MBGNT GPIO_GPIO (21) /* Memory Bus GraNT (O) */ #define GPIO_TREQA GPIO_GPIO (22) /* TIC REQuest A (I) */ @@ -1632,21 +1632,21 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #if LANGUAGE == C #define ICIP /* IC IRQ Pending reg. */ \ - (*((volatile Word *) io_p2v (_ICIP))) + (*((volatile Word *) io_p2v (_ICIP))) #define ICMR /* IC Mask Reg. */ \ - (*((volatile Word *) io_p2v (_ICMR))) + (*((volatile Word *) io_p2v (_ICMR))) #define ICLR /* IC Level Reg. */ \ - (*((volatile Word *) io_p2v (_ICLR))) + (*((volatile Word *) io_p2v (_ICLR))) #define ICCR /* IC Control Reg. */ \ - (*((volatile Word *) io_p2v (_ICCR))) + (*((volatile Word *) io_p2v (_ICCR))) #define ICFP /* IC FIQ Pending reg. */ \ - (*((volatile Word *) io_p2v (_ICFP))) + (*((volatile Word *) io_p2v (_ICFP))) #define ICPR /* IC Pending Reg. */ \ - (*((volatile Word *) io_p2v (_ICPR))) + (*((volatile Word *) io_p2v (_ICPR))) #endif /* LANGUAGE == C */ #define IC_GPIO(Nb) /* GPIO [0..10] */ \ - (0x00000001 << (Nb)) + (0x00000001 << (Nb)) #define IC_GPIO0 IC_GPIO (0) /* GPIO [0] */ #define IC_GPIO1 IC_GPIO (1) /* GPIO [1] */ #define IC_GPIO2 IC_GPIO (2) /* GPIO [2] */ @@ -1668,7 +1668,7 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define IC_Ser4MCP 0x00040000 /* Ser. port 4 MCP */ #define IC_Ser4SSP 0x00080000 /* Ser. port 4 SSP */ #define IC_DMA(Nb) /* DMA controller channel [0..5] */ \ - (0x00100000 << (Nb)) + (0x00100000 << (Nb)) #define IC_DMA0 IC_DMA (0) /* DMA controller channel 0 */ #define IC_DMA1 IC_DMA (1) /* DMA controller channel 1 */ #define IC_DMA2 IC_DMA (2) /* DMA controller channel 2 */ @@ -1676,7 +1676,7 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define IC_DMA4 IC_DMA (4) /* DMA controller channel 4 */ #define IC_DMA5 IC_DMA (5) /* DMA controller channel 5 */ #define IC_OST(Nb) /* OS Timer match [0..3] */ \ - (0x04000000 << (Nb)) + (0x04000000 << (Nb)) #define IC_OST0 IC_OST (0) /* OS Timer match 0 */ #define IC_OST1 IC_OST (1) /* OS Timer match 1 */ #define IC_OST2 IC_OST (2) /* OS Timer match 2 */ @@ -1688,11 +1688,11 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define ICLR_FIQ 1 /* Fast Interrupt reQuest */ #define ICCR_DIM 0x00000001 /* Disable Idle-mode interrupt */ - /* Mask */ + /* Mask */ #define ICCR_IdleAllInt (ICCR_DIM*0) /* Idle-mode All Interrupt enable */ - /* (ICMR ignored) */ + /* (ICMR ignored) */ #define ICCR_IdleMskInt (ICCR_DIM*1) /* Idle-mode non-Masked Interrupt */ - /* enable (ICMR used) */ + /* enable (ICMR used) */ /* @@ -1715,25 +1715,25 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define _PPSR 0x90060004 /* PPC Pin State Reg. */ #define _PPAR 0x90060008 /* PPC Pin Assignment Reg. */ #define _PSDR 0x9006000C /* PPC Sleep-mode pin Direction */ - /* Reg. */ + /* Reg. */ #define _PPFR 0x90060010 /* PPC Pin Flag Reg. */ #if LANGUAGE == C #define PPDR /* PPC Pin Direction Reg. */ \ - (*((volatile Word *) io_p2v (_PPDR))) + (*((volatile Word *) io_p2v (_PPDR))) #define PPSR /* PPC Pin State Reg. */ \ - (*((volatile Word *) io_p2v (_PPSR))) + (*((volatile Word *) io_p2v (_PPSR))) #define PPAR /* PPC Pin Assignment Reg. */ \ - (*((volatile Word *) io_p2v (_PPAR))) + (*((volatile Word *) io_p2v (_PPAR))) #define PSDR /* PPC Sleep-mode pin Direction */ \ - /* Reg. */ \ - (*((volatile Word *) io_p2v (_PSDR))) + /* Reg. */ \ + (*((volatile Word *) io_p2v (_PSDR))) #define PPFR /* PPC Pin Flag Reg. */ \ - (*((volatile Word *) io_p2v (_PPFR))) + (*((volatile Word *) io_p2v (_PPFR))) #endif /* LANGUAGE == C */ #define PPC_LDD(Nb) /* LCD Data [0..7] */ \ - (0x00000001 << (Nb)) + (0x00000001 << (Nb)) #define PPC_LDD0 PPC_LDD (0) /* LCD Data [0] */ #define PPC_LDD1 PPC_LDD (1) /* LCD Data [1] */ #define PPC_LDD2 PPC_LDD (2) /* LCD Data [2] */ @@ -1746,16 +1746,16 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define PPC_L_LCLK 0x00000200 /* LCD Line CLocK */ #define PPC_L_FCLK 0x00000400 /* LCD Frame CLocK */ #define PPC_L_BIAS 0x00000800 /* LCD AC BIAS */ - /* ser. port 1: */ + /* ser. port 1: */ #define PPC_TXD1 0x00001000 /* SDLC/UART Transmit Data 1 */ #define PPC_RXD1 0x00002000 /* SDLC/UART Receive Data 1 */ - /* ser. port 2: */ + /* ser. port 2: */ #define PPC_TXD2 0x00004000 /* IPC Transmit Data 2 */ #define PPC_RXD2 0x00008000 /* IPC Receive Data 2 */ - /* ser. port 3: */ + /* ser. port 3: */ #define PPC_TXD3 0x00010000 /* UART Transmit Data 3 */ #define PPC_RXD3 0x00020000 /* UART Receive Data 3 */ - /* ser. port 4: */ + /* ser. port 4: */ #define PPC_TXD4 0x00040000 /* MCP/SSP Transmit Data 4 */ #define PPC_RXD4 0x00080000 /* MCP/SSP Receive Data 4 */ #define PPC_SCLK 0x00100000 /* MCP/SSP Sample CLocK */ @@ -1764,14 +1764,14 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define PPDR_In 0 /* Input */ #define PPDR_Out 1 /* Output */ - /* ser. port 1: */ + /* ser. port 1: */ #define PPAR_UPR 0x00001000 /* UART Pin Reassignment */ #define PPAR_UARTTR (PPAR_UPR*0) /* UART on TXD_1 & RXD_1 */ #define PPAR_UARTGPIO (PPAR_UPR*1) /* UART on GPIO [14:15] */ - /* ser. port 4: */ + /* ser. port 4: */ #define PPAR_SPR 0x00040000 /* SSP Pin Reassignment */ #define PPAR_SSPTRSS (PPAR_SPR*0) /* SSP on TXD_C, RXD_C, SCLK_C, */ - /* & SFRM_C */ + /* & SFRM_C */ #define PPAR_SSPGPIO (PPAR_SPR*1) /* SSP on GPIO [10:13] */ #define PSDR_OutL 0 /* Output Low in sleep mode */ @@ -1811,20 +1811,20 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; * fcas, Tcas Frequency, period of the DRAM CAS shift registers. */ - /* Memory system: */ + /* Memory system: */ #define _MDCNFG 0xA0000000 /* DRAM CoNFiGuration reg. */ #define _MDCAS(Nb) /* DRAM CAS shift reg. [0..3] */ \ - (0xA0000004 + (Nb)*4) + (0xA0000004 + (Nb)*4) #define _MDCAS0 _MDCAS (0) /* DRAM CAS shift reg. 0 */ #define _MDCAS1 _MDCAS (1) /* DRAM CAS shift reg. 1 */ #define _MDCAS2 _MDCAS (2) /* DRAM CAS shift reg. 2 */ #if LANGUAGE == C - /* Memory system: */ + /* Memory system: */ #define MDCNFG /* DRAM CoNFiGuration reg. */ \ - (*((volatile Word *) io_p2v (_MDCNFG))) + (*((volatile Word *) io_p2v (_MDCNFG))) #define MDCAS /* DRAM CAS shift reg. [0..3] */ \ - ((volatile Word *) io_p2v (_MDCAS (0))) + ((volatile Word *) io_p2v (_MDCAS (0))) #define MDCAS0 (MDCAS [0]) /* DRAM CAS shift reg. 0 */ #define MDCAS1 (MDCAS [1]) /* DRAM CAS shift reg. 1 */ #define MDCAS2 (MDCAS [2]) /* DRAM CAS shift reg. 2 */ @@ -1837,34 +1837,34 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; /* SA1100 MDCNFG values */ #define MDCNFG_DE(Nb) /* DRAM Enable bank [0..3] */ \ - (0x00000001 << (Nb)) + (0x00000001 << (Nb)) #define MDCNFG_DE0 MDCNFG_DE (0) /* DRAM Enable bank 0 */ #define MDCNFG_DE1 MDCNFG_DE (1) /* DRAM Enable bank 1 */ #define MDCNFG_DE2 MDCNFG_DE (2) /* DRAM Enable bank 2 */ #define MDCNFG_DE3 MDCNFG_DE (3) /* DRAM Enable bank 3 */ #define MDCNFG_DRAC Fld (2, 4) /* DRAM Row Address Count - 9 */ #define MDCNFG_RowAdd(Add) /* Row Address count [9..12] */ \ - (((Add) - 9) << FShft (MDCNFG_DRAC)) + (((Add) - 9) << FShft (MDCNFG_DRAC)) #define MDCNFG_CDB2 0x00000040 /* shift reg. Clock Divide By 2 */ - /* (fcas = fcpu/2) */ + /* (fcas = fcpu/2) */ #define MDCNFG_TRP Fld (4, 7) /* Time RAS Pre-charge - 1 [Tmem] */ #define MDCNFG_PrChrg(Tcpu) /* Pre-Charge time [2..32 Tcpu] */ \ - (((Tcpu) - 2)/2 << FShft (MDCNFG_TRP)) + (((Tcpu) - 2)/2 << FShft (MDCNFG_TRP)) #define MDCNFG_CeilPrChrg(Tcpu) /* Ceil. of PrChrg [2..32 Tcpu] */ \ - (((Tcpu) - 1)/2 << FShft (MDCNFG_TRP)) + (((Tcpu) - 1)/2 << FShft (MDCNFG_TRP)) #define MDCNFG_TRASR Fld (4, 11) /* Time RAS Refresh - 1 [Tmem] */ #define MDCNFG_Ref(Tcpu) /* Refresh time [2..32 Tcpu] */ \ - (((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR)) + (((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR)) #define MDCNFG_CeilRef(Tcpu) /* Ceil. of Ref [2..32 Tcpu] */ \ - (((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR)) + (((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR)) #define MDCNFG_TDL Fld (2, 15) /* Time Data Latch [Tcpu] */ #define MDCNFG_DataLtch(Tcpu) /* Data Latch delay [0..3 Tcpu] */ \ - ((Tcpu) << FShft (MDCNFG_TDL)) + ((Tcpu) << FShft (MDCNFG_TDL)) #define MDCNFG_DRI Fld (15, 17) /* min. DRAM Refresh Interval/4 */ - /* [Tmem] */ + /* [Tmem] */ #define MDCNFG_RefInt(Tcpu) /* min. Refresh Interval */ \ - /* [0..262136 Tcpu] */ \ - ((Tcpu)/8 << FShft (MDCNFG_DRI)) + /* [0..262136 Tcpu] */ \ + ((Tcpu)/8 << FShft (MDCNFG_DRI)) /* SA1110 MDCNFG values */ #define MDCNFG_SA1110_DE0 0x00000001 /* DRAM Enable bank 0 */ @@ -1872,22 +1872,22 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define MDCNFG_SA1110_DTIM0 0x00000004 /* DRAM timing type 0/1 */ #define MDCNFG_SA1110_DWID0 0x00000008 /* DRAM bus width 0/1 */ #define MDCNFG_SA1110_DRAC0 Fld(3, 4) /* DRAM row addr bit count */ - /* bank 0/1 */ + /* bank 0/1 */ #define MDCNFG_SA1110_CDB20 0x00000080 /* Mem Clock divide by 2 0/1 */ #define MDCNFG_SA1110_TRP0 Fld(3, 8) /* RAS precharge 0/1 */ #define MDCNFG_SA1110_TDL0 Fld(2, 12) /* Data input latch after CAS*/ - /* deassertion 0/1 */ + /* deassertion 0/1 */ #define MDCNFG_SA1110_TWR0 Fld(2, 14) /* SDRAM write recovery 0/1 */ #define MDCNFG_SA1110_DE2 0x00010000 /* DRAM Enable bank 0 */ #define MDCNFG_SA1110_DE3 0x00020000 /* DRAM Enable bank 1 */ #define MDCNFG_SA1110_DTIM2 0x00040000 /* DRAM timing type 0/1 */ #define MDCNFG_SA1110_DWID2 0x00080000 /* DRAM bus width 0/1 */ #define MDCNFG_SA1110_DRAC2 Fld(3, 20) /* DRAM row addr bit count */ - /* bank 0/1 */ + /* bank 0/1 */ #define MDCNFG_SA1110_CDB22 0x00800000 /* Mem Clock divide by 2 0/1 */ #define MDCNFG_SA1110_TRP2 Fld(3, 24) /* RAS precharge 0/1 */ #define MDCNFG_SA1110_TDL2 Fld(2, 28) /* Data input latch after CAS*/ - /* deassertion 0/1 */ + /* deassertion 0/1 */ #define MDCNFG_SA1110_TWR2 Fld(2, 30) /* SDRAM write recovery 0/1 */ @@ -1905,19 +1905,19 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). */ - /* Memory system: */ + /* Memory system: */ #define _MSC(Nb) /* Static memory Control reg. */ \ - /* [0..1] */ \ - (0xA0000010 + (Nb)*4) + /* [0..1] */ \ + (0xA0000010 + (Nb)*4) #define _MSC0 _MSC (0) /* Static memory Control reg. 0 */ #define _MSC1 _MSC (1) /* Static memory Control reg. 1 */ #define _MSC2 0xA000002C /* Static memory Control reg. 2, not contiguous */ #if LANGUAGE == C - /* Memory system: */ + /* Memory system: */ #define MSC /* Static memory Control reg. */ \ - /* [0..1] */ \ - ((volatile Word *) io_p2v (_MSC (0))) + /* [0..1] */ \ + ((volatile Word *) io_p2v (_MSC (0))) #define MSC0 (MSC [0]) /* Static memory Control reg. 0 */ #define MSC1 (MSC [1]) /* Static memory Control reg. 1 */ #define MSC2 (*(volatile Word *) io_p2v (_MSC2)) /* Static memory Control reg. 2 */ @@ -1931,7 +1931,7 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #endif /* LANGUAGE == C */ #define MSC_Bnk(Nb) /* static memory Bank [0..3] */ \ - Fld (16, ((Nb) Modulo 2)*16) + Fld (16, ((Nb) Modulo 2)*16) #define MSC0_Bnk0 MSC_Bnk (0) /* static memory Bank 0 */ #define MSC0_Bnk1 MSC_Bnk (1) /* static memory Bank 1 */ #define MSC1_Bnk2 MSC_Bnk (2) /* static memory Bank 2 */ @@ -1939,46 +1939,46 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define MSC_RT Fld (2, 0) /* ROM/static memory Type */ #define MSC_NonBrst /* Non-Burst static memory */ \ - (0 << FShft (MSC_RT)) + (0 << FShft (MSC_RT)) #define MSC_SRAM /* 32-bit byte-writable SRAM */ \ - (1 << FShft (MSC_RT)) + (1 << FShft (MSC_RT)) #define MSC_Brst4 /* Burst-of-4 static memory */ \ - (2 << FShft (MSC_RT)) + (2 << FShft (MSC_RT)) #define MSC_Brst8 /* Burst-of-8 static memory */ \ - (3 << FShft (MSC_RT)) + (3 << FShft (MSC_RT)) #define MSC_RBW 0x0004 /* ROM/static memory Bus Width */ #define MSC_32BitStMem (MSC_RBW*0) /* 32-Bit Static Memory */ #define MSC_16BitStMem (MSC_RBW*1) /* 16-Bit Static Memory */ #define MSC_RDF Fld (5, 3) /* ROM/static memory read Delay */ - /* First access - 1(.5) [Tmem] */ + /* First access - 1(.5) [Tmem] */ #define MSC_1stRdAcc(Tcpu) /* 1st Read Access time (burst */ \ - /* static memory) [3..65 Tcpu] */ \ - ((((Tcpu) - 3)/2) << FShft (MSC_RDF)) + /* static memory) [3..65 Tcpu] */ \ + ((((Tcpu) - 3)/2) << FShft (MSC_RDF)) #define MSC_Ceil1stRdAcc(Tcpu) /* Ceil. of 1stRdAcc [3..65 Tcpu] */ \ - ((((Tcpu) - 2)/2) << FShft (MSC_RDF)) + ((((Tcpu) - 2)/2) << FShft (MSC_RDF)) #define MSC_RdAcc(Tcpu) /* Read Access time (non-burst */ \ - /* static memory) [2..64 Tcpu] */ \ - ((((Tcpu) - 2)/2) << FShft (MSC_RDF)) + /* static memory) [2..64 Tcpu] */ \ + ((((Tcpu) - 2)/2) << FShft (MSC_RDF)) #define MSC_CeilRdAcc(Tcpu) /* Ceil. of RdAcc [2..64 Tcpu] */ \ - ((((Tcpu) - 1)/2) << FShft (MSC_RDF)) + ((((Tcpu) - 1)/2) << FShft (MSC_RDF)) #define MSC_RDN Fld (5, 8) /* ROM/static memory read Delay */ - /* Next access - 1 [Tmem] */ + /* Next access - 1 [Tmem] */ #define MSC_NxtRdAcc(Tcpu) /* Next Read Access time (burst */ \ - /* static memory) [2..64 Tcpu] */ \ - ((((Tcpu) - 2)/2) << FShft (MSC_RDN)) + /* static memory) [2..64 Tcpu] */ \ + ((((Tcpu) - 2)/2) << FShft (MSC_RDN)) #define MSC_CeilNxtRdAcc(Tcpu) /* Ceil. of NxtRdAcc [2..64 Tcpu] */ \ - ((((Tcpu) - 1)/2) << FShft (MSC_RDN)) + ((((Tcpu) - 1)/2) << FShft (MSC_RDN)) #define MSC_WrAcc(Tcpu) /* Write Access time (non-burst */ \ - /* static memory) [2..64 Tcpu] */ \ - ((((Tcpu) - 2)/2) << FShft (MSC_RDN)) + /* static memory) [2..64 Tcpu] */ \ + ((((Tcpu) - 2)/2) << FShft (MSC_RDN)) #define MSC_CeilWrAcc(Tcpu) /* Ceil. of WrAcc [2..64 Tcpu] */ \ - ((((Tcpu) - 1)/2) << FShft (MSC_RDN)) + ((((Tcpu) - 1)/2) << FShft (MSC_RDN)) #define MSC_RRR Fld (3, 13) /* ROM/static memory RecoveRy */ - /* time/2 [Tmem] */ + /* time/2 [Tmem] */ #define MSC_Rec(Tcpu) /* Recovery time [0..28 Tcpu] */ \ - (((Tcpu)/4) << FShft (MSC_RRR)) + (((Tcpu)/4) << FShft (MSC_RRR)) #define MSC_CeilRec(Tcpu) /* Ceil. of Rec [0..28 Tcpu] */ \ - ((((Tcpu) + 3)/4) << FShft (MSC_RRR)) + ((((Tcpu) + 3)/4) << FShft (MSC_RRR)) /* @@ -1995,38 +1995,38 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; * fbclk, Tbclk Frequency, period of the PCMCIA clock (BCLK). */ - /* Memory system: */ + /* Memory system: */ #define _MECR 0xA0000018 /* Expansion memory bus (PCMCIA) */ - /* Configuration Reg. */ + /* Configuration Reg. */ #if LANGUAGE == C - /* Memory system: */ + /* Memory system: */ #define MECR /* Expansion memory bus (PCMCIA) */ \ - /* Configuration Reg. */ \ - (*((volatile Word *) io_p2v (_MECR))) + /* Configuration Reg. */ \ + (*((volatile Word *) io_p2v (_MECR))) #endif /* LANGUAGE == C */ #define MECR_PCMCIA(Nb) /* PCMCIA [0..1] */ \ - Fld (15, (Nb)*16) + Fld (15, (Nb)*16) #define MECR_PCMCIA0 MECR_PCMCIA (0) /* PCMCIA 0 */ #define MECR_PCMCIA1 MECR_PCMCIA (1) /* PCMCIA 1 */ #define MECR_BSIO Fld (5, 0) /* BCLK Select I/O - 1 [Tmem] */ #define MECR_IOClk(Tcpu) /* I/O Clock [2..64 Tcpu] */ \ - ((((Tcpu) - 2)/2) << FShft (MECR_BSIO)) + ((((Tcpu) - 2)/2) << FShft (MECR_BSIO)) #define MECR_CeilIOClk(Tcpu) /* Ceil. of IOClk [2..64 Tcpu] */ \ - ((((Tcpu) - 1)/2) << FShft (MECR_BSIO)) + ((((Tcpu) - 1)/2) << FShft (MECR_BSIO)) #define MECR_BSA Fld (5, 5) /* BCLK Select Attribute - 1 */ - /* [Tmem] */ + /* [Tmem] */ #define MECR_AttrClk(Tcpu) /* Attribute Clock [2..64 Tcpu] */ \ - ((((Tcpu) - 2)/2) << FShft (MECR_BSA)) + ((((Tcpu) - 2)/2) << FShft (MECR_BSA)) #define MECR_CeilAttrClk(Tcpu) /* Ceil. of AttrClk [2..64 Tcpu] */ \ - ((((Tcpu) - 1)/2) << FShft (MECR_BSA)) + ((((Tcpu) - 1)/2) << FShft (MECR_BSA)) #define MECR_BSM Fld (5, 10) /* BCLK Select Memory - 1 [Tmem] */ #define MECR_MemClk(Tcpu) /* Memory Clock [2..64 Tcpu] */ \ - ((((Tcpu) - 2)/2) << FShft (MECR_BSM)) + ((((Tcpu) - 2)/2) << FShft (MECR_BSM)) #define MECR_CeilMemClk(Tcpu) /* Ceil. of MemClk [2..64 Tcpu] */ \ - ((((Tcpu) - 1)/2) << FShft (MECR_BSM)) + ((((Tcpu) - 1)/2) << FShft (MECR_BSM)) /* * On SA1110 only @@ -2035,9 +2035,9 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define _MDREFR 0xA000001C #if LANGUAGE == C - /* Memory system: */ + /* Memory system: */ #define MDREFR \ - (*((volatile Word *) io_p2v (_MDREFR))) + (*((volatile Word *) io_p2v (_MDREFR))) #elif LANGUAGE == Assembly @@ -2146,291 +2146,291 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define DMASp 0x00000020 /* DMA control reg. Space [byte] */ #define _DDAR(Nb) /* DMA Device Address Reg. */ \ - /* channel [0..5] */ \ - (0xB0000000 + (Nb)*DMASp) + /* channel [0..5] */ \ + (0xB0000000 + (Nb)*DMASp) #define _SetDCSR(Nb) /* Set DMA Control & Status Reg. */ \ - /* channel [0..5] (write) */ \ - (0xB0000004 + (Nb)*DMASp) + /* channel [0..5] (write) */ \ + (0xB0000004 + (Nb)*DMASp) #define _ClrDCSR(Nb) /* Clear DMA Control & Status Reg. */ \ - /* channel [0..5] (write) */ \ - (0xB0000008 + (Nb)*DMASp) + /* channel [0..5] (write) */ \ + (0xB0000008 + (Nb)*DMASp) #define _RdDCSR(Nb) /* Read DMA Control & Status Reg. */ \ - /* channel [0..5] (read) */ \ - (0xB000000C + (Nb)*DMASp) + /* channel [0..5] (read) */ \ + (0xB000000C + (Nb)*DMASp) #define _DBSA(Nb) /* DMA Buffer Start address reg. A */ \ - /* channel [0..5] */ \ - (0xB0000010 + (Nb)*DMASp) + /* channel [0..5] */ \ + (0xB0000010 + (Nb)*DMASp) #define _DBTA(Nb) /* DMA Buffer Transfer count */ \ - /* reg. A channel [0..5] */ \ - (0xB0000014 + (Nb)*DMASp) + /* reg. A channel [0..5] */ \ + (0xB0000014 + (Nb)*DMASp) #define _DBSB(Nb) /* DMA Buffer Start address reg. B */ \ - /* channel [0..5] */ \ - (0xB0000018 + (Nb)*DMASp) + /* channel [0..5] */ \ + (0xB0000018 + (Nb)*DMASp) #define _DBTB(Nb) /* DMA Buffer Transfer count */ \ - /* reg. B channel [0..5] */ \ - (0xB000001C + (Nb)*DMASp) + /* reg. B channel [0..5] */ \ + (0xB000001C + (Nb)*DMASp) #define _DDAR0 _DDAR (0) /* DMA Device Address Reg. */ - /* channel 0 */ + /* channel 0 */ #define _SetDCSR0 _SetDCSR (0) /* Set DMA Control & Status Reg. */ - /* channel 0 (write) */ + /* channel 0 (write) */ #define _ClrDCSR0 _ClrDCSR (0) /* Clear DMA Control & Status Reg. */ - /* channel 0 (write) */ + /* channel 0 (write) */ #define _RdDCSR0 _RdDCSR (0) /* Read DMA Control & Status Reg. */ - /* channel 0 (read) */ + /* channel 0 (read) */ #define _DBSA0 _DBSA (0) /* DMA Buffer Start address reg. A */ - /* channel 0 */ + /* channel 0 */ #define _DBTA0 _DBTA (0) /* DMA Buffer Transfer count */ - /* reg. A channel 0 */ + /* reg. A channel 0 */ #define _DBSB0 _DBSB (0) /* DMA Buffer Start address reg. B */ - /* channel 0 */ + /* channel 0 */ #define _DBTB0 _DBTB (0) /* DMA Buffer Transfer count */ - /* reg. B channel 0 */ + /* reg. B channel 0 */ #define _DDAR1 _DDAR (1) /* DMA Device Address Reg. */ - /* channel 1 */ + /* channel 1 */ #define _SetDCSR1 _SetDCSR (1) /* Set DMA Control & Status Reg. */ - /* channel 1 (write) */ + /* channel 1 (write) */ #define _ClrDCSR1 _ClrDCSR (1) /* Clear DMA Control & Status Reg. */ - /* channel 1 (write) */ + /* channel 1 (write) */ #define _RdDCSR1 _RdDCSR (1) /* Read DMA Control & Status Reg. */ - /* channel 1 (read) */ + /* channel 1 (read) */ #define _DBSA1 _DBSA (1) /* DMA Buffer Start address reg. A */ - /* channel 1 */ + /* channel 1 */ #define _DBTA1 _DBTA (1) /* DMA Buffer Transfer count */ - /* reg. A channel 1 */ + /* reg. A channel 1 */ #define _DBSB1 _DBSB (1) /* DMA Buffer Start address reg. B */ - /* channel 1 */ + /* channel 1 */ #define _DBTB1 _DBTB (1) /* DMA Buffer Transfer count */ - /* reg. B channel 1 */ + /* reg. B channel 1 */ #define _DDAR2 _DDAR (2) /* DMA Device Address Reg. */ - /* channel 2 */ + /* channel 2 */ #define _SetDCSR2 _SetDCSR (2) /* Set DMA Control & Status Reg. */ - /* channel 2 (write) */ + /* channel 2 (write) */ #define _ClrDCSR2 _ClrDCSR (2) /* Clear DMA Control & Status Reg. */ - /* channel 2 (write) */ + /* channel 2 (write) */ #define _RdDCSR2 _RdDCSR (2) /* Read DMA Control & Status Reg. */ - /* channel 2 (read) */ + /* channel 2 (read) */ #define _DBSA2 _DBSA (2) /* DMA Buffer Start address reg. A */ - /* channel 2 */ + /* channel 2 */ #define _DBTA2 _DBTA (2) /* DMA Buffer Transfer count */ - /* reg. A channel 2 */ + /* reg. A channel 2 */ #define _DBSB2 _DBSB (2) /* DMA Buffer Start address reg. B */ - /* channel 2 */ + /* channel 2 */ #define _DBTB2 _DBTB (2) /* DMA Buffer Transfer count */ - /* reg. B channel 2 */ + /* reg. B channel 2 */ #define _DDAR3 _DDAR (3) /* DMA Device Address Reg. */ - /* channel 3 */ + /* channel 3 */ #define _SetDCSR3 _SetDCSR (3) /* Set DMA Control & Status Reg. */ - /* channel 3 (write) */ + /* channel 3 (write) */ #define _ClrDCSR3 _ClrDCSR (3) /* Clear DMA Control & Status Reg. */ - /* channel 3 (write) */ + /* channel 3 (write) */ #define _RdDCSR3 _RdDCSR (3) /* Read DMA Control & Status Reg. */ - /* channel 3 (read) */ + /* channel 3 (read) */ #define _DBSA3 _DBSA (3) /* DMA Buffer Start address reg. A */ - /* channel 3 */ + /* channel 3 */ #define _DBTA3 _DBTA (3) /* DMA Buffer Transfer count */ - /* reg. A channel 3 */ + /* reg. A channel 3 */ #define _DBSB3 _DBSB (3) /* DMA Buffer Start address reg. B */ - /* channel 3 */ + /* channel 3 */ #define _DBTB3 _DBTB (3) /* DMA Buffer Transfer count */ - /* reg. B channel 3 */ + /* reg. B channel 3 */ #define _DDAR4 _DDAR (4) /* DMA Device Address Reg. */ - /* channel 4 */ + /* channel 4 */ #define _SetDCSR4 _SetDCSR (4) /* Set DMA Control & Status Reg. */ - /* channel 4 (write) */ + /* channel 4 (write) */ #define _ClrDCSR4 _ClrDCSR (4) /* Clear DMA Control & Status Reg. */ - /* channel 4 (write) */ + /* channel 4 (write) */ #define _RdDCSR4 _RdDCSR (4) /* Read DMA Control & Status Reg. */ - /* channel 4 (read) */ + /* channel 4 (read) */ #define _DBSA4 _DBSA (4) /* DMA Buffer Start address reg. A */ - /* channel 4 */ + /* channel 4 */ #define _DBTA4 _DBTA (4) /* DMA Buffer Transfer count */ - /* reg. A channel 4 */ + /* reg. A channel 4 */ #define _DBSB4 _DBSB (4) /* DMA Buffer Start address reg. B */ - /* channel 4 */ + /* channel 4 */ #define _DBTB4 _DBTB (4) /* DMA Buffer Transfer count */ - /* reg. B channel 4 */ + /* reg. B channel 4 */ #define _DDAR5 _DDAR (5) /* DMA Device Address Reg. */ - /* channel 5 */ + /* channel 5 */ #define _SetDCSR5 _SetDCSR (5) /* Set DMA Control & Status Reg. */ - /* channel 5 (write) */ + /* channel 5 (write) */ #define _ClrDCSR5 _ClrDCSR (5) /* Clear DMA Control & Status Reg. */ - /* channel 5 (write) */ + /* channel 5 (write) */ #define _RdDCSR5 _RdDCSR (5) /* Read DMA Control & Status Reg. */ - /* channel 5 (read) */ + /* channel 5 (read) */ #define _DBSA5 _DBSA (5) /* DMA Buffer Start address reg. A */ - /* channel 5 */ + /* channel 5 */ #define _DBTA5 _DBTA (5) /* DMA Buffer Transfer count */ - /* reg. A channel 5 */ + /* reg. A channel 5 */ #define _DBSB5 _DBSB (5) /* DMA Buffer Start address reg. B */ - /* channel 5 */ + /* channel 5 */ #define _DBTB5 _DBTB (5) /* DMA Buffer Transfer count */ - /* reg. B channel 5 */ + /* reg. B channel 5 */ #if LANGUAGE == C #define DDAR0 /* DMA Device Address Reg. */ \ - /* channel 0 */ \ - (*((volatile Word *) io_p2v (_DDAR0))) + /* channel 0 */ \ + (*((volatile Word *) io_p2v (_DDAR0))) #define SetDCSR0 /* Set DMA Control & Status Reg. */ \ - /* channel 0 (write) */ \ - (*((volatile Word *) io_p2v (_SetDCSR0))) + /* channel 0 (write) */ \ + (*((volatile Word *) io_p2v (_SetDCSR0))) #define ClrDCSR0 /* Clear DMA Control & Status Reg. */ \ - /* channel 0 (write) */ \ - (*((volatile Word *) io_p2v (_ClrDCSR0))) + /* channel 0 (write) */ \ + (*((volatile Word *) io_p2v (_ClrDCSR0))) #define RdDCSR0 /* Read DMA Control & Status Reg. */ \ - /* channel 0 (read) */ \ - (*((volatile Word *) io_p2v (_RdDCSR0))) + /* channel 0 (read) */ \ + (*((volatile Word *) io_p2v (_RdDCSR0))) #define DBSA0 /* DMA Buffer Start address reg. A */ \ - /* channel 0 */ \ - (*((volatile Address *) io_p2v (_DBSA0))) + /* channel 0 */ \ + (*((volatile Address *) io_p2v (_DBSA0))) #define DBTA0 /* DMA Buffer Transfer count */ \ - /* reg. A channel 0 */ \ - (*((volatile Word *) io_p2v (_DBTA0))) + /* reg. A channel 0 */ \ + (*((volatile Word *) io_p2v (_DBTA0))) #define DBSB0 /* DMA Buffer Start address reg. B */ \ - /* channel 0 */ \ - (*((volatile Address *) io_p2v (_DBSB0))) + /* channel 0 */ \ + (*((volatile Address *) io_p2v (_DBSB0))) #define DBTB0 /* DMA Buffer Transfer count */ \ - /* reg. B channel 0 */ \ - (*((volatile Word *) io_p2v (_DBTB0))) + /* reg. B channel 0 */ \ + (*((volatile Word *) io_p2v (_DBTB0))) #define DDAR1 /* DMA Device Address Reg. */ \ - /* channel 1 */ \ - (*((volatile Word *) io_p2v (_DDAR1))) + /* channel 1 */ \ + (*((volatile Word *) io_p2v (_DDAR1))) #define SetDCSR1 /* Set DMA Control & Status Reg. */ \ - /* channel 1 (write) */ \ - (*((volatile Word *) io_p2v (_SetDCSR1))) + /* channel 1 (write) */ \ + (*((volatile Word *) io_p2v (_SetDCSR1))) #define ClrDCSR1 /* Clear DMA Control & Status Reg. */ \ - /* channel 1 (write) */ \ - (*((volatile Word *) io_p2v (_ClrDCSR1))) + /* channel 1 (write) */ \ + (*((volatile Word *) io_p2v (_ClrDCSR1))) #define RdDCSR1 /* Read DMA Control & Status Reg. */ \ - /* channel 1 (read) */ \ - (*((volatile Word *) io_p2v (_RdDCSR1))) + /* channel 1 (read) */ \ + (*((volatile Word *) io_p2v (_RdDCSR1))) #define DBSA1 /* DMA Buffer Start address reg. A */ \ - /* channel 1 */ \ - (*((volatile Address *) io_p2v (_DBSA1))) + /* channel 1 */ \ + (*((volatile Address *) io_p2v (_DBSA1))) #define DBTA1 /* DMA Buffer Transfer count */ \ - /* reg. A channel 1 */ \ - (*((volatile Word *) io_p2v (_DBTA1))) + /* reg. A channel 1 */ \ + (*((volatile Word *) io_p2v (_DBTA1))) #define DBSB1 /* DMA Buffer Start address reg. B */ \ - /* channel 1 */ \ - (*((volatile Address *) io_p2v (_DBSB1))) + /* channel 1 */ \ + (*((volatile Address *) io_p2v (_DBSB1))) #define DBTB1 /* DMA Buffer Transfer count */ \ - /* reg. B channel 1 */ \ - (*((volatile Word *) io_p2v (_DBTB1))) + /* reg. B channel 1 */ \ + (*((volatile Word *) io_p2v (_DBTB1))) #define DDAR2 /* DMA Device Address Reg. */ \ - /* channel 2 */ \ - (*((volatile Word *) io_p2v (_DDAR2))) + /* channel 2 */ \ + (*((volatile Word *) io_p2v (_DDAR2))) #define SetDCSR2 /* Set DMA Control & Status Reg. */ \ - /* channel 2 (write) */ \ - (*((volatile Word *) io_p2v (_SetDCSR2))) + /* channel 2 (write) */ \ + (*((volatile Word *) io_p2v (_SetDCSR2))) #define ClrDCSR2 /* Clear DMA Control & Status Reg. */ \ - /* channel 2 (write) */ \ - (*((volatile Word *) io_p2v (_ClrDCSR2))) + /* channel 2 (write) */ \ + (*((volatile Word *) io_p2v (_ClrDCSR2))) #define RdDCSR2 /* Read DMA Control & Status Reg. */ \ - /* channel 2 (read) */ \ - (*((volatile Word *) io_p2v (_RdDCSR2))) + /* channel 2 (read) */ \ + (*((volatile Word *) io_p2v (_RdDCSR2))) #define DBSA2 /* DMA Buffer Start address reg. A */ \ - /* channel 2 */ \ - (*((volatile Address *) io_p2v (_DBSA2))) + /* channel 2 */ \ + (*((volatile Address *) io_p2v (_DBSA2))) #define DBTA2 /* DMA Buffer Transfer count */ \ - /* reg. A channel 2 */ \ - (*((volatile Word *) io_p2v (_DBTA2))) + /* reg. A channel 2 */ \ + (*((volatile Word *) io_p2v (_DBTA2))) #define DBSB2 /* DMA Buffer Start address reg. B */ \ - /* channel 2 */ \ - (*((volatile Address *) io_p2v (_DBSB2))) + /* channel 2 */ \ + (*((volatile Address *) io_p2v (_DBSB2))) #define DBTB2 /* DMA Buffer Transfer count */ \ - /* reg. B channel 2 */ \ - (*((volatile Word *) io_p2v (_DBTB2))) + /* reg. B channel 2 */ \ + (*((volatile Word *) io_p2v (_DBTB2))) #define DDAR3 /* DMA Device Address Reg. */ \ - /* channel 3 */ \ - (*((volatile Word *) io_p2v (_DDAR3))) + /* channel 3 */ \ + (*((volatile Word *) io_p2v (_DDAR3))) #define SetDCSR3 /* Set DMA Control & Status Reg. */ \ - /* channel 3 (write) */ \ - (*((volatile Word *) io_p2v (_SetDCSR3))) + /* channel 3 (write) */ \ + (*((volatile Word *) io_p2v (_SetDCSR3))) #define ClrDCSR3 /* Clear DMA Control & Status Reg. */ \ - /* channel 3 (write) */ \ - (*((volatile Word *) io_p2v (_ClrDCSR3))) + /* channel 3 (write) */ \ + (*((volatile Word *) io_p2v (_ClrDCSR3))) #define RdDCSR3 /* Read DMA Control & Status Reg. */ \ - /* channel 3 (read) */ \ - (*((volatile Word *) io_p2v (_RdDCSR3))) + /* channel 3 (read) */ \ + (*((volatile Word *) io_p2v (_RdDCSR3))) #define DBSA3 /* DMA Buffer Start address reg. A */ \ - /* channel 3 */ \ - (*((volatile Address *) io_p2v (_DBSA3))) + /* channel 3 */ \ + (*((volatile Address *) io_p2v (_DBSA3))) #define DBTA3 /* DMA Buffer Transfer count */ \ - /* reg. A channel 3 */ \ - (*((volatile Word *) io_p2v (_DBTA3))) + /* reg. A channel 3 */ \ + (*((volatile Word *) io_p2v (_DBTA3))) #define DBSB3 /* DMA Buffer Start address reg. B */ \ - /* channel 3 */ \ - (*((volatile Address *) io_p2v (_DBSB3))) + /* channel 3 */ \ + (*((volatile Address *) io_p2v (_DBSB3))) #define DBTB3 /* DMA Buffer Transfer count */ \ - /* reg. B channel 3 */ \ - (*((volatile Word *) io_p2v (_DBTB3))) + /* reg. B channel 3 */ \ + (*((volatile Word *) io_p2v (_DBTB3))) #define DDAR4 /* DMA Device Address Reg. */ \ - /* channel 4 */ \ - (*((volatile Word *) io_p2v (_DDAR4))) + /* channel 4 */ \ + (*((volatile Word *) io_p2v (_DDAR4))) #define SetDCSR4 /* Set DMA Control & Status Reg. */ \ - /* channel 4 (write) */ \ - (*((volatile Word *) io_p2v (_SetDCSR4))) + /* channel 4 (write) */ \ + (*((volatile Word *) io_p2v (_SetDCSR4))) #define ClrDCSR4 /* Clear DMA Control & Status Reg. */ \ - /* channel 4 (write) */ \ - (*((volatile Word *) io_p2v (_ClrDCSR4))) + /* channel 4 (write) */ \ + (*((volatile Word *) io_p2v (_ClrDCSR4))) #define RdDCSR4 /* Read DMA Control & Status Reg. */ \ - /* channel 4 (read) */ \ - (*((volatile Word *) io_p2v (_RdDCSR4))) + /* channel 4 (read) */ \ + (*((volatile Word *) io_p2v (_RdDCSR4))) #define DBSA4 /* DMA Buffer Start address reg. A */ \ - /* channel 4 */ \ - (*((volatile Address *) io_p2v (_DBSA4))) + /* channel 4 */ \ + (*((volatile Address *) io_p2v (_DBSA4))) #define DBTA4 /* DMA Buffer Transfer count */ \ - /* reg. A channel 4 */ \ - (*((volatile Word *) io_p2v (_DBTA4))) + /* reg. A channel 4 */ \ + (*((volatile Word *) io_p2v (_DBTA4))) #define DBSB4 /* DMA Buffer Start address reg. B */ \ - /* channel 4 */ \ - (*((volatile Address *) io_p2v (_DBSB4))) + /* channel 4 */ \ + (*((volatile Address *) io_p2v (_DBSB4))) #define DBTB4 /* DMA Buffer Transfer count */ \ - /* reg. B channel 4 */ \ - (*((volatile Word *) io_p2v (_DBTB4))) + /* reg. B channel 4 */ \ + (*((volatile Word *) io_p2v (_DBTB4))) #define DDAR5 /* DMA Device Address Reg. */ \ - /* channel 5 */ \ - (*((volatile Word *) io_p2v (_DDAR5))) + /* channel 5 */ \ + (*((volatile Word *) io_p2v (_DDAR5))) #define SetDCSR5 /* Set DMA Control & Status Reg. */ \ - /* channel 5 (write) */ \ - (*((volatile Word *) io_p2v (_SetDCSR5))) + /* channel 5 (write) */ \ + (*((volatile Word *) io_p2v (_SetDCSR5))) #define ClrDCSR5 /* Clear DMA Control & Status Reg. */ \ - /* channel 5 (write) */ \ - (*((volatile Word *) io_p2v (_ClrDCSR5))) + /* channel 5 (write) */ \ + (*((volatile Word *) io_p2v (_ClrDCSR5))) #define RdDCSR5 /* Read DMA Control & Status Reg. */ \ - /* channel 5 (read) */ \ - (*((volatile Word *) io_p2v (_RdDCSR5))) + /* channel 5 (read) */ \ + (*((volatile Word *) io_p2v (_RdDCSR5))) #define DBSA5 /* DMA Buffer Start address reg. A */ \ - /* channel 5 */ \ - (*((volatile Address *) io_p2v (_DBSA5))) + /* channel 5 */ \ + (*((volatile Address *) io_p2v (_DBSA5))) #define DBTA5 /* DMA Buffer Transfer count */ \ - /* reg. A channel 5 */ \ - (*((volatile Word *) io_p2v (_DBTA5))) + /* reg. A channel 5 */ \ + (*((volatile Word *) io_p2v (_DBTA5))) #define DBSB5 /* DMA Buffer Start address reg. B */ \ - /* channel 5 */ \ - (*((volatile Address *) io_p2v (_DBSB5))) + /* channel 5 */ \ + (*((volatile Address *) io_p2v (_DBSB5))) #define DBTB5 /* DMA Buffer Transfer count */ \ - /* reg. B channel 5 */ \ - (*((volatile Word *) io_p2v (_DBTB5))) + /* reg. B channel 5 */ \ + (*((volatile Word *) io_p2v (_DBTB5))) #endif /* LANGUAGE == C */ #define DDAR_RW 0x00000001 /* device data Read/Write */ #define DDAR_DevWr (DDAR_RW*0) /* Device data Write */ - /* (memory -> device) */ + /* (memory -> device) */ #define DDAR_DevRd (DDAR_RW*1) /* Device data Read */ - /* (device -> memory) */ + /* (device -> memory) */ #define DDAR_E 0x00000002 /* big/little Endian device */ #define DDAR_LtlEnd (DDAR_E*0) /* Little Endian device */ #define DDAR_BigEnd (DDAR_E*1) /* Big Endian device */ @@ -2442,101 +2442,101 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define DDAR_16BitDev (DDAR_DW*1) /* 16-Bit Device */ #define DDAR_DS Fld (4, 4) /* Device Select */ #define DDAR_Ser0UDCTr /* Ser. port 0 UDC Transmit */ \ - (0x0 << FShft (DDAR_DS)) + (0x0 << FShft (DDAR_DS)) #define DDAR_Ser0UDCRc /* Ser. port 0 UDC Receive */ \ - (0x1 << FShft (DDAR_DS)) + (0x1 << FShft (DDAR_DS)) #define DDAR_Ser1SDLCTr /* Ser. port 1 SDLC Transmit */ \ - (0x2 << FShft (DDAR_DS)) + (0x2 << FShft (DDAR_DS)) #define DDAR_Ser1SDLCRc /* Ser. port 1 SDLC Receive */ \ - (0x3 << FShft (DDAR_DS)) + (0x3 << FShft (DDAR_DS)) #define DDAR_Ser1UARTTr /* Ser. port 1 UART Transmit */ \ - (0x4 << FShft (DDAR_DS)) + (0x4 << FShft (DDAR_DS)) #define DDAR_Ser1UARTRc /* Ser. port 1 UART Receive */ \ - (0x5 << FShft (DDAR_DS)) + (0x5 << FShft (DDAR_DS)) #define DDAR_Ser2ICPTr /* Ser. port 2 ICP Transmit */ \ - (0x6 << FShft (DDAR_DS)) + (0x6 << FShft (DDAR_DS)) #define DDAR_Ser2ICPRc /* Ser. port 2 ICP Receive */ \ - (0x7 << FShft (DDAR_DS)) + (0x7 << FShft (DDAR_DS)) #define DDAR_Ser3UARTTr /* Ser. port 3 UART Transmit */ \ - (0x8 << FShft (DDAR_DS)) + (0x8 << FShft (DDAR_DS)) #define DDAR_Ser3UARTRc /* Ser. port 3 UART Receive */ \ - (0x9 << FShft (DDAR_DS)) + (0x9 << FShft (DDAR_DS)) #define DDAR_Ser4MCP0Tr /* Ser. port 4 MCP 0 Transmit */ \ - /* (audio) */ \ - (0xA << FShft (DDAR_DS)) + /* (audio) */ \ + (0xA << FShft (DDAR_DS)) #define DDAR_Ser4MCP0Rc /* Ser. port 4 MCP 0 Receive */ \ - /* (audio) */ \ - (0xB << FShft (DDAR_DS)) + /* (audio) */ \ + (0xB << FShft (DDAR_DS)) #define DDAR_Ser4MCP1Tr /* Ser. port 4 MCP 1 Transmit */ \ - /* (telecom) */ \ - (0xC << FShft (DDAR_DS)) + /* (telecom) */ \ + (0xC << FShft (DDAR_DS)) #define DDAR_Ser4MCP1Rc /* Ser. port 4 MCP 1 Receive */ \ - /* (telecom) */ \ - (0xD << FShft (DDAR_DS)) + /* (telecom) */ \ + (0xD << FShft (DDAR_DS)) #define DDAR_Ser4SSPTr /* Ser. port 4 SSP Transmit */ \ - (0xE << FShft (DDAR_DS)) + (0xE << FShft (DDAR_DS)) #define DDAR_Ser4SSPRc /* Ser. port 4 SSP Receive */ \ - (0xF << FShft (DDAR_DS)) + (0xF << FShft (DDAR_DS)) #define DDAR_DA Fld (24, 8) /* Device Address */ #define DDAR_DevAdd(Add) /* Device Address */ \ - (((Add) & 0xF0000000) | \ - (((Add) & 0X003FFFFC) << (FShft (DDAR_DA) - 2))) + (((Add) & 0xF0000000) | \ + (((Add) & 0X003FFFFC) << (FShft (DDAR_DA) - 2))) #define DDAR_Ser0UDCWr /* Ser. port 0 UDC Write */ \ - (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \ - DDAR_Ser0UDCTr + DDAR_DevAdd (_Ser0UDCDR)) + (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \ + DDAR_Ser0UDCTr + DDAR_DevAdd (_Ser0UDCDR)) #define DDAR_Ser0UDCRd /* Ser. port 0 UDC Read */ \ - (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \ - DDAR_Ser0UDCRc + DDAR_DevAdd (_Ser0UDCDR)) + (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \ + DDAR_Ser0UDCRc + DDAR_DevAdd (_Ser0UDCDR)) #define DDAR_Ser1UARTWr /* Ser. port 1 UART Write */ \ - (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser1UARTTr + DDAR_DevAdd (_Ser1UTDR)) + (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ + DDAR_Ser1UARTTr + DDAR_DevAdd (_Ser1UTDR)) #define DDAR_Ser1UARTRd /* Ser. port 1 UART Read */ \ - (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser1UARTRc + DDAR_DevAdd (_Ser1UTDR)) + (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ + DDAR_Ser1UARTRc + DDAR_DevAdd (_Ser1UTDR)) #define DDAR_Ser1SDLCWr /* Ser. port 1 SDLC Write */ \ - (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser1SDLCTr + DDAR_DevAdd (_Ser1SDDR)) + (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ + DDAR_Ser1SDLCTr + DDAR_DevAdd (_Ser1SDDR)) #define DDAR_Ser1SDLCRd /* Ser. port 1 SDLC Read */ \ - (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser1SDLCRc + DDAR_DevAdd (_Ser1SDDR)) + (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ + DDAR_Ser1SDLCRc + DDAR_DevAdd (_Ser1SDDR)) #define DDAR_Ser2UARTWr /* Ser. port 2 UART Write */ \ - (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2UTDR)) + (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ + DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2UTDR)) #define DDAR_Ser2UARTRd /* Ser. port 2 UART Read */ \ - (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2UTDR)) + (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ + DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2UTDR)) #define DDAR_Ser2HSSPWr /* Ser. port 2 HSSP Write */ \ - (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \ - DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2HSDR)) + (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \ + DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2HSDR)) #define DDAR_Ser2HSSPRd /* Ser. port 2 HSSP Read */ \ - (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \ - DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2HSDR)) + (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \ + DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2HSDR)) #define DDAR_Ser3UARTWr /* Ser. port 3 UART Write */ \ - (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser3UARTTr + DDAR_DevAdd (_Ser3UTDR)) + (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ + DDAR_Ser3UARTTr + DDAR_DevAdd (_Ser3UTDR)) #define DDAR_Ser3UARTRd /* Ser. port 3 UART Read */ \ - (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ - DDAR_Ser3UARTRc + DDAR_DevAdd (_Ser3UTDR)) + (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ + DDAR_Ser3UARTRc + DDAR_DevAdd (_Ser3UTDR)) #define DDAR_Ser4MCP0Wr /* Ser. port 4 MCP 0 Write (audio) */ \ - (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ - DDAR_Ser4MCP0Tr + DDAR_DevAdd (_Ser4MCDR0)) + (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ + DDAR_Ser4MCP0Tr + DDAR_DevAdd (_Ser4MCDR0)) #define DDAR_Ser4MCP0Rd /* Ser. port 4 MCP 0 Read (audio) */ \ - (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ - DDAR_Ser4MCP0Rc + DDAR_DevAdd (_Ser4MCDR0)) + (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ + DDAR_Ser4MCP0Rc + DDAR_DevAdd (_Ser4MCDR0)) #define DDAR_Ser4MCP1Wr /* Ser. port 4 MCP 1 Write */ \ - /* (telecom) */ \ - (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ - DDAR_Ser4MCP1Tr + DDAR_DevAdd (_Ser4MCDR1)) + /* (telecom) */ \ + (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ + DDAR_Ser4MCP1Tr + DDAR_DevAdd (_Ser4MCDR1)) #define DDAR_Ser4MCP1Rd /* Ser. port 4 MCP 1 Read */ \ - /* (telecom) */ \ - (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ - DDAR_Ser4MCP1Rc + DDAR_DevAdd (_Ser4MCDR1)) + /* (telecom) */ \ + (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ + DDAR_Ser4MCP1Rc + DDAR_DevAdd (_Ser4MCDR1)) #define DDAR_Ser4SSPWr /* Ser. port 4 SSP Write (16 bits) */ \ - (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ - DDAR_Ser4SSPTr + DDAR_DevAdd (_Ser4SSDR)) + (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ + DDAR_Ser4SSPTr + DDAR_DevAdd (_Ser4SSDR)) #define DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ \ - (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ - DDAR_Ser4SSPRc + DDAR_DevAdd (_Ser4SSDR)) + (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ + DDAR_Ser4SSPRc + DDAR_DevAdd (_Ser4SSDR)) #define DCSR_RUN 0x00000001 /* DMA RUNing */ #define DCSR_IE 0x00000002 /* DMA Interrupt Enable */ @@ -2608,14 +2608,14 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define LCD_PEntrySp 2 /* LCD Palette Entry Space [byte] */ #define LCD_4BitPSp /* LCD 4-Bit pixel Palette Space */ \ - /* [byte] */ \ - (16*LCD_PEntrySp) + /* [byte] */ \ + (16*LCD_PEntrySp) #define LCD_8BitPSp /* LCD 8-Bit pixel Palette Space */ \ - /* [byte] */ \ - (256*LCD_PEntrySp) + /* [byte] */ \ + (256*LCD_PEntrySp) #define LCD_12_16BitPSp /* LCD 12/16-Bit pixel */ \ - /* dummy-Palette Space [byte] */ \ - (16*LCD_PEntrySp) + /* dummy-Palette Space [byte] */ \ + (16*LCD_PEntrySp) #define LCD_PGrey Fld (4, 0) /* LCD Palette entry Grey value */ #define LCD_PBlue Fld (4, 0) /* LCD Palette entry Blue value */ @@ -2623,11 +2623,11 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define LCD_PRed Fld (4, 8) /* LCD Palette entry Red value */ #define LCD_PBS Fld (2, 12) /* LCD Pixel Bit Size */ #define LCD_4Bit /* LCD 4-Bit pixel mode */ \ - (0 << FShft (LCD_PBS)) + (0 << FShft (LCD_PBS)) #define LCD_8Bit /* LCD 8-Bit pixel mode */ \ - (1 << FShft (LCD_PBS)) + (1 << FShft (LCD_PBS)) #define LCD_12_16Bit /* LCD 12/16-Bit pixel mode */ \ - (2 << FShft (LCD_PBS)) + (2 << FShft (LCD_PBS)) #define LCD_Int0_0 0x0 /* LCD Intensity = 0.0% = 0 */ #define LCD_Int11_1 0x1 /* LCD Intensity = 11.1% = 1/9 */ @@ -2645,45 +2645,45 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define LCD_Int88_9 0xD /* LCD Intensity = 88.9% = 8/9 */ #define LCD_Int100_0 0xE /* LCD Intensity = 100.0% = 1 */ #define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */ - /* (Alternative) */ + /* (Alternative) */ #define _LCCR0 0xB0100000 /* LCD Control Reg. 0 */ #define _LCSR 0xB0100004 /* LCD Status Reg. */ #define _DBAR1 0xB0100010 /* LCD DMA Base Address Reg. */ - /* channel 1 */ + /* channel 1 */ #define _DCAR1 0xB0100014 /* LCD DMA Current Address Reg. */ - /* channel 1 */ + /* channel 1 */ #define _DBAR2 0xB0100018 /* LCD DMA Base Address Reg. */ - /* channel 2 */ + /* channel 2 */ #define _DCAR2 0xB010001C /* LCD DMA Current Address Reg. */ - /* channel 2 */ + /* channel 2 */ #define _LCCR1 0xB0100020 /* LCD Control Reg. 1 */ #define _LCCR2 0xB0100024 /* LCD Control Reg. 2 */ #define _LCCR3 0xB0100028 /* LCD Control Reg. 3 */ #if LANGUAGE == C #define LCCR0 /* LCD Control Reg. 0 */ \ - (*((volatile Word *) io_p2v (_LCCR0))) + (*((volatile Word *) io_p2v (_LCCR0))) #define LCSR /* LCD Status Reg. */ \ - (*((volatile Word *) io_p2v (_LCSR))) + (*((volatile Word *) io_p2v (_LCSR))) #define DBAR1 /* LCD DMA Base Address Reg. */ \ - /* channel 1 */ \ - (*((volatile Address *) io_p2v (_DBAR1))) + /* channel 1 */ \ + (*((volatile Address *) io_p2v (_DBAR1))) #define DCAR1 /* LCD DMA Current Address Reg. */ \ - /* channel 1 */ \ - (*((volatile Address *) io_p2v (_DCAR1))) + /* channel 1 */ \ + (*((volatile Address *) io_p2v (_DCAR1))) #define DBAR2 /* LCD DMA Base Address Reg. */ \ - /* channel 2 */ \ - (*((volatile Address *) io_p2v (_DBAR2))) + /* channel 2 */ \ + (*((volatile Address *) io_p2v (_DBAR2))) #define DCAR2 /* LCD DMA Current Address Reg. */ \ - /* channel 2 */ \ - (*((volatile Address *) io_p2v (_DCAR2))) + /* channel 2 */ \ + (*((volatile Address *) io_p2v (_DCAR2))) #define LCCR1 /* LCD Control Reg. 1 */ \ - (*((volatile Word *) io_p2v (_LCCR1))) + (*((volatile Word *) io_p2v (_LCCR1))) #define LCCR2 /* LCD Control Reg. 2 */ \ - (*((volatile Word *) io_p2v (_LCCR2))) + (*((volatile Word *) io_p2v (_LCCR2))) #define LCCR3 /* LCD Control Reg. 3 */ \ - (*((volatile Word *) io_p2v (_LCCR3))) + (*((volatile Word *) io_p2v (_LCCR3))) #endif /* LANGUAGE == C */ #define LCCR0_LEN 0x00000001 /* LCD ENable */ @@ -2691,16 +2691,16 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define LCCR0_Color (LCCR0_CMS*0) /* Color display */ #define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */ #define LCCR0_SDS 0x00000004 /* Single/Dual panel display */ - /* Select */ + /* Select */ #define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */ #define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */ #define LCCR0_LDM 0x00000008 /* LCD Disable done (LDD) */ - /* interrupt Mask (disable) */ + /* interrupt Mask (disable) */ #define LCCR0_BAM 0x00000010 /* Base Address update (BAU) */ - /* interrupt Mask (disable) */ + /* interrupt Mask (disable) */ #define LCCR0_ERM 0x00000020 /* LCD ERror (BER, IOL, IUL, IOU, */ - /* IUU, OOL, OUL, OOU, and OUU) */ - /* interrupt Mask (disable) */ + /* IUU, OOL, OUL, OOU, and OUU) */ + /* interrupt Mask (disable) */ #define LCCR0_PAS 0x00000080 /* Passive/Active display Select */ #define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */ #define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */ @@ -2708,127 +2708,126 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define LCCR0_LtlEnd (LCCR0_BLE*0) /* Little Endian frame buffer */ #define LCCR0_BigEnd (LCCR0_BLE*1) /* Big Endian frame buffer */ #define LCCR0_DPD 0x00000200 /* Double Pixel Data (monochrome */ - /* display mode) */ + /* display mode) */ #define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */ - /* display */ + /* display */ #define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */ - /* display */ + /* display */ #define LCCR0_PDD Fld (8, 12) /* Palette DMA request Delay */ - /* [Tmem] */ + /* [Tmem] */ #define LCCR0_DMADel(Tcpu) /* palette DMA request Delay */ \ - /* [0..510 Tcpu] */ \ - ((Tcpu)/2 << FShft (LCCR0_PDD)) + /* [0..510 Tcpu] */ \ + ((Tcpu)/2 << FShft (LCCR0_PDD)) #define LCSR_LDD 0x00000001 /* LCD Disable Done */ #define LCSR_BAU 0x00000002 /* Base Address Update (read) */ #define LCSR_BER 0x00000004 /* Bus ERror */ #define LCSR_ABC 0x00000008 /* AC Bias clock Count */ #define LCSR_IOL 0x00000010 /* Input FIFO Over-run Lower */ - /* panel */ + /* panel */ #define LCSR_IUL 0x00000020 /* Input FIFO Under-run Lower */ - /* panel */ + /* panel */ #define LCSR_IOU 0x00000040 /* Input FIFO Over-run Upper */ - /* panel */ + /* panel */ #define LCSR_IUU 0x00000080 /* Input FIFO Under-run Upper */ - /* panel */ + /* panel */ #define LCSR_OOL 0x00000100 /* Output FIFO Over-run Lower */ - /* panel */ + /* panel */ #define LCSR_OUL 0x00000200 /* Output FIFO Under-run Lower */ - /* panel */ + /* panel */ #define LCSR_OOU 0x00000400 /* Output FIFO Over-run Upper */ - /* panel */ + /* panel */ #define LCSR_OUU 0x00000800 /* Output FIFO Under-run Upper */ - /* panel */ + /* panel */ #define LCCR1_PPL Fld (6, 4) /* Pixels Per Line/16 - 1 */ #define LCCR1_DisWdth(Pixel) /* Display Width [16..1024 pix.] */ \ - (((Pixel) - 16)/16 << FShft (LCCR1_PPL)) + (((Pixel) - 16)/16 << FShft (LCCR1_PPL)) #define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ - /* pulse Width - 2 [Tpix] (L_LCLK) */ + /* pulse Width - 2 [Tpix] (L_LCLK) */ #define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \ - /* pulse Width [2..65 Tpix] */ \ - (((Tpix) - 2) << FShft (LCCR1_HSW)) + /* pulse Width [2..65 Tpix] */ \ + (((Tpix) - 2) << FShft (LCCR1_HSW)) #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */ - /* count - 1 [Tpix] */ + /* count - 1 [Tpix] */ #define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \ - /* [1..256 Tpix] */ \ - (((Tpix) - 1) << FShft (LCCR1_ELW)) + /* [1..256 Tpix] */ \ + (((Tpix) - 1) << FShft (LCCR1_ELW)) #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */ - /* Wait count - 1 [Tpix] */ + /* Wait count - 1 [Tpix] */ #define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \ - /* [1..256 Tpix] */ \ - (((Tpix) - 1) << FShft (LCCR1_BLW)) + /* [1..256 Tpix] */ \ + (((Tpix) - 1) << FShft (LCCR1_BLW)) #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ #define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \ - (((Line) - 1) << FShft (LCCR2_LPP)) + (((Line) - 1) << FShft (LCCR2_LPP)) #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ - /* Width - 1 [Tln] (L_FCLK) */ + /* Width - 1 [Tln] (L_FCLK) */ #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ - /* Width [1..64 Tln] */ \ - (((Tln) - 1) << FShft (LCCR2_VSW)) + /* Width [1..64 Tln] */ \ + (((Tln) - 1) << FShft (LCCR2_VSW)) #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */ - /* count [Tln] */ + /* count [Tln] */ #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ - /* [0..255 Tln] */ \ - ((Tln) << FShft (LCCR2_EFW)) + /* [0..255 Tln] */ \ + ((Tln) << FShft (LCCR2_EFW)) #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */ - /* Wait count [Tln] */ + /* Wait count [Tln] */ #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ - /* [0..255 Tln] */ \ - ((Tln) << FShft (LCCR2_BFW)) + /* [0..255 Tln] */ \ + ((Tln) << FShft (LCCR2_BFW)) #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor/2 - 2 */ - /* [1..255] (L_PCLK) */ - /* fpix = fcpu/(2*(PCD + 2)) */ - /* Tpix = 2*(PCD + 2)*Tcpu */ + /* [1..255] (L_PCLK) */ + /* fpix = fcpu/(2*(PCD + 2)) */ + /* Tpix = 2*(PCD + 2)*Tcpu */ #define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor [6..514] */ \ - (((Div) - 4)/2 << FShft (LCCR3_PCD)) - /* fpix = fcpu/(2*Floor (Div/2)) */ - /* Tpix = 2*Floor (Div/2)*Tcpu */ + (((Div) - 4)/2 << FShft (LCCR3_PCD)) + /* fpix = fcpu/(2*Floor (Div/2)) */ + /* Tpix = 2*Floor (Div/2)*Tcpu */ #define LCCR3_CeilPixClkDiv(Div) /* Ceil. of PixClkDiv [6..514] */ \ - (((Div) - 3)/2 << FShft (LCCR3_PCD)) - /* fpix = fcpu/(2*Ceil (Div/2)) */ - /* Tpix = 2*Ceil (Div/2)*Tcpu */ + (((Div) - 3)/2 << FShft (LCCR3_PCD)) + /* fpix = fcpu/(2*Ceil (Div/2)) */ + /* Tpix = 2*Ceil (Div/2)*Tcpu */ #define LCCR3_ACB Fld (8, 8) /* AC Bias clock half period - 1 */ - /* [Tln] (L_BIAS) */ + /* [Tln] (L_BIAS) */ #define LCCR3_ACBsDiv(Div) /* AC Bias clock Divisor [2..512] */ \ - (((Div) - 2)/2 << FShft (LCCR3_ACB)) - /* fac = fln/(2*Floor (Div/2)) */ - /* Tac = 2*Floor (Div/2)*Tln */ + (((Div) - 2)/2 << FShft (LCCR3_ACB)) + /* fac = fln/(2*Floor (Div/2)) */ + /* Tac = 2*Floor (Div/2)*Tln */ #define LCCR3_CeilACBsDiv(Div) /* Ceil. of ACBsDiv [2..512] */ \ - (((Div) - 1)/2 << FShft (LCCR3_ACB)) - /* fac = fln/(2*Ceil (Div/2)) */ - /* Tac = 2*Ceil (Div/2)*Tln */ + (((Div) - 1)/2 << FShft (LCCR3_ACB)) + /* fac = fln/(2*Ceil (Div/2)) */ + /* Tac = 2*Ceil (Div/2)*Tln */ #define LCCR3_API Fld (4, 16) /* AC bias Pin transitions per */ - /* Interrupt */ + /* Interrupt */ #define LCCR3_ACBsCntOff /* AC Bias clock transition Count */ \ - /* Off */ \ - (0 << FShft (LCCR3_API)) + /* Off */ \ + (0 << FShft (LCCR3_API)) #define LCCR3_ACBsCnt(Trans) /* AC Bias clock transition Count */ \ - /* [1..15] */ \ - ((Trans) << FShft (LCCR3_API)) + /* [1..15] */ \ + ((Trans) << FShft (LCCR3_API)) #define LCCR3_VSP 0x00100000 /* Vertical Synchronization pulse */ - /* Polarity (L_FCLK) */ + /* Polarity (L_FCLK) */ #define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */ - /* active High */ + /* active High */ #define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */ - /* active Low */ + /* active Low */ #define LCCR3_HSP 0x00200000 /* Horizontal Synchronization */ - /* pulse Polarity (L_LCLK) */ + /* pulse Polarity (L_LCLK) */ #define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */ - /* pulse active High */ + /* pulse active High */ #define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */ - /* pulse active Low */ + /* pulse active Low */ #define LCCR3_PCP 0x00400000 /* Pixel Clock Polarity (L_PCLK) */ #define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */ #define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */ #define LCCR3_OEP 0x00800000 /* Output Enable Polarity (L_BIAS, */ - /* active display mode) */ + /* active display mode) */ #define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */ #define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */ #undef C #undef Assembly - diff --git a/include/arm920t.h b/include/arm920t.h index 4592665ac54..95f33235a0d 100644 --- a/include/arm920t.h +++ b/include/arm920t.h @@ -10,4 +10,3 @@ #endif /*__ARM920T_H__*/ - diff --git a/include/asm-arm/arch-arm920t/memory.h b/include/asm-arm/arch-arm920t/memory.h index 8a4e3f8716a..333f218679a 100644 --- a/include/asm-arm/arch-arm920t/memory.h +++ b/include/asm-arm/arch-arm920t/memory.h @@ -92,17 +92,17 @@ extern unsigned long __phys_to_virt(unsigned long ppage); #ifdef CONFIG_DISCONTIGMEM #error "CONFIG_DISCONTIGMEM will not work on S3C2400" /* - * Because of the wide memory address space between physical RAM banks on the + * Because of the wide memory address space between physical RAM banks on the * SA1100, it's much more convenient to use Linux's NUMA support to implement - * our memory map representation. Assuming all memory nodes have equal access + * our memory map representation. Assuming all memory nodes have equal access * characteristics, we then have generic discontiguous memory support. * * Of course, all this isn't mandatory for SA1100 implementations with only * one used memory bank. For those, simply undefine CONFIG_DISCONTIGMEM. * - * The nodes are matched with the physical memory bank addresses which are + * The nodes are matched with the physical memory bank addresses which are * incidentally the same as virtual addresses. - * + * * node 0: 0xc0000000 - 0xc7ffffff * node 1: 0xc8000000 - 0xcfffffff * node 2: 0xd0000000 - 0xd7ffffff @@ -138,7 +138,7 @@ extern unsigned long __phys_to_virt(unsigned long ppage); (((unsigned long)(kvaddr) & 0x07ffffff) >> PAGE_SHIFT) /* - * Given a kaddr, virt_to_page returns a pointer to the corresponding + * Given a kaddr, virt_to_page returns a pointer to the corresponding * mem_map entry. */ #define virt_to_page(kaddr) \ diff --git a/include/asm-arm/arch-at91rm9200/AT91RM9200.h b/include/asm-arm/arch-at91rm9200/AT91RM9200.h index c0e52119c8f..60f17376bd3 100644 --- a/include/asm-arm/arch-at91rm9200/AT91RM9200.h +++ b/include/asm-arm/arch-at91rm9200/AT91RM9200.h @@ -21,7 +21,7 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ - + #ifndef AT91RM9200_H #define AT91RM9200_H @@ -205,13 +205,13 @@ typedef struct _AT91S_PMC { AT91_REG PMC_SCER; /* System Clock Enable Register */ AT91_REG PMC_SCDR; /* System Clock Disable Register */ AT91_REG PMC_SCSR; /* System Clock Status Register */ - AT91_REG Reserved0[1]; /* */ + AT91_REG Reserved0[1]; /* */ AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */ AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */ AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */ - AT91_REG Reserved1[5]; /* */ + AT91_REG Reserved1[5]; /* */ AT91_REG PMC_MCKR; /* Master Clock Register */ - AT91_REG Reserved2[3]; /* */ + AT91_REG Reserved2[3]; /* */ AT91_REG PMC_PCKR[8]; /* Programmable Clock Register */ AT91_REG PMC_IER; /* Interrupt Enable Register */ AT91_REG PMC_IDR; /* Interrupt Disable Register */ @@ -281,9 +281,9 @@ typedef struct _AT91S_EMAC { #define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) /* (EMAC) Back pressure. */ /* -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- */ #define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) /* (EMAC) Speed. */ -#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) /* (EMAC) Full duplex. */ +#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) /* (EMAC) Full duplex. */ #define AT91C_EMAC_BR ((unsigned int) 0x1 << 2) /* (EMAC) Bit rate. */ -#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) /* (EMAC) Copy all frames. */ +#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) /* (EMAC) Copy all frames. */ #define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) /* (EMAC) No broadcast. */ #define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) /* (EMAC) Multicast hash enable */ #define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) /* (EMAC) Unicast hash enable. */ @@ -328,10 +328,10 @@ typedef struct _AT91S_EMAC { #define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) /* (EMAC) */ #define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) /* (EMAC) */ /* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */ -/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */ +/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */ /* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */ /* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */ -#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) /* (EMAC) */ +#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) /* (EMAC) */ #define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) /* (EMAC) */ #define AT91C_EMAC_CODE_802_3 ((unsigned int) 0x2 << 16) /* (EMAC) Write Operation */ #define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) /* (EMAC) */ @@ -356,7 +356,7 @@ typedef struct _AT91S_SPI { AT91_REG SPI_IMR; /* Interrupt Mask Register */ AT91_REG Reserved0[4]; /* */ AT91_REG SPI_CSR[4]; /* Chip Select Register */ - AT91_REG Reserved1[48]; /* */ + AT91_REG Reserved1[48]; /* */ AT91_REG SPI_RPR; /* Receive Pointer Register */ AT91_REG SPI_RCR; /* Receive Counter Register */ AT91_REG SPI_TPR; /* Transmit Pointer Register */ diff --git a/include/asm-arm/arch-pxa/bitfield.h b/include/asm-arm/arch-pxa/bitfield.h index f1f0e3387d9..2ac5ea21cfd 100644 --- a/include/asm-arm/arch-pxa/bitfield.h +++ b/include/asm-arm/arch-pxa/bitfield.h @@ -11,7 +11,6 @@ */ - #ifndef __BITFIELD_H #define __BITFIELD_H @@ -88,7 +87,7 @@ */ #define FInsrt(Value, Field) \ - (UData (Value) << FShft (Field)) + (UData (Value) << FShft (Field)) /* @@ -107,7 +106,7 @@ */ #define FExtr(Data, Field) \ - ((UData (Data) >> FShft (Field)) & FAlnMsk (Field)) + ((UData (Data) >> FShft (Field)) & FAlnMsk (Field)) #endif /* __BITFIELD_H */ diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h index b84ea48df1a..d40f05ed4db 100644 --- a/include/asm-arm/arch-pxa/hardware.h +++ b/include/asm-arm/arch-pxa/hardware.h @@ -4,7 +4,7 @@ * Author: Nicolas Pitre * Created: Jun 15, 2001 * Copyright: MontaVista Software Inc. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. @@ -86,16 +86,16 @@ typedef struct { volatile u32 offset[4096]; } __regbase; #endif #endif /* UBOOT_REG_FIX */ - + #ifdef UBOOT_REG_FIX # undef io_p2v # undef __REG # ifndef __ASSEMBLY__ # define io_p2v(PhAdd) (PhAdd) # define __REG(x) (*((volatile u32 *)io_p2v(x))) -# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y))) +# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y))) # else -# define __REG(x) (x) +# define __REG(x) (x) #endif /* UBOOT_REG_FIX */ #include "pxa-regs.h" diff --git a/include/asm-arm/arch-pxa/mmc.h b/include/asm-arm/arch-pxa/mmc.h index 4d61adeaf62..a62679a1a1a 100644 --- a/include/asm-arm/arch-pxa/mmc.h +++ b/include/asm-arm/arch-pxa/mmc.h @@ -1,7 +1,7 @@ /* - * linux/drivers/mmc/mmc_pxa.h + * linux/drivers/mmc/mmc_pxa.h * - * Author: Vladimir Shebordaev, Igor Oblakov + * Author: Vladimir Shebordaev, Igor Oblakov * Copyright: MontaVista Software Inc. * * $Id: mmc_pxa.h,v 0.3.1.6 2002/09/25 19:25:48 ted Exp ted $ @@ -76,7 +76,7 @@ #define MMC_BLK_LEN_MAX (0x03ffUL) /* [9:0] */ /* MMC_PRTBUF */ -#define MMC_PRTBUF_BUF_PART_FULL (0x01UL) +#define MMC_PRTBUF_BUF_PART_FULL (0x01UL) #define MMC_PRTBUF_BUF_FULL (0x00UL ) /* MMC_I_MASK */ diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index 208c1101041..a59838c183c 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -63,12 +63,12 @@ typedef void (*ExcpHndlr) (void) ; #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */ #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ - (0x20000000 + (Nb)*PCMCIASp) + (0x20000000 + (Nb)*PCMCIASp) #define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ - (_PCMCIA (Nb) + 2*PCMCIAPrtSp) + (_PCMCIA (Nb) + 2*PCMCIAPrtSp) #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ - (_PCMCIA (Nb) + 3*PCMCIAPrtSp) + (_PCMCIA (Nb) + 3*PCMCIAPrtSp) #define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */ #define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */ @@ -81,7 +81,6 @@ typedef void (*ExcpHndlr) (void) ; #define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */ - /* * DMA Controller */ @@ -402,18 +401,18 @@ typedef void (*ExcpHndlr) (void) ; #define IrSR_XMITIR_UART_MODE 0x0 #define IrSR_IR_RECEIVE_ON (\ - IrSR_RXPL_NEG_IS_ZERO | \ - IrSR_TXPL_POS_IS_ZERO | \ - IrSR_XMODE_PULSE_3_16 | \ - IrSR_RCVEIR_IR_MODE | \ - IrSR_XMITIR_UART_MODE) + IrSR_RXPL_NEG_IS_ZERO | \ + IrSR_TXPL_POS_IS_ZERO | \ + IrSR_XMODE_PULSE_3_16 | \ + IrSR_RCVEIR_IR_MODE | \ + IrSR_XMITIR_UART_MODE) #define IrSR_IR_TRANSMIT_ON (\ - IrSR_RXPL_NEG_IS_ZERO | \ - IrSR_TXPL_POS_IS_ZERO | \ - IrSR_XMODE_PULSE_3_16 | \ - IrSR_RCVEIR_UART_MODE | \ - IrSR_XMITIR_IR_MODE) + IrSR_RXPL_NEG_IS_ZERO | \ + IrSR_TXPL_POS_IS_ZERO | \ + IrSR_XMODE_PULSE_3_16 | \ + IrSR_RCVEIR_UART_MODE | \ + IrSR_XMITIR_IR_MODE) /* * I2C registers @@ -1198,47 +1197,47 @@ typedef void (*ExcpHndlr) (void) ; #define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */ #define LCCR1_DisWdth(Pixel) /* Display Width [1..800 pix.] */ \ - (((Pixel) - 1) << FShft (LCCR1_PPL)) + (((Pixel) - 1) << FShft (LCCR1_PPL)) #define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ #define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \ - /* pulse Width [1..64 Tpix] */ \ - (((Tpix) - 1) << FShft (LCCR1_HSW)) + /* pulse Width [1..64 Tpix] */ \ + (((Tpix) - 1) << FShft (LCCR1_HSW)) #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */ - /* count - 1 [Tpix] */ + /* count - 1 [Tpix] */ #define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \ - /* [1..256 Tpix] */ \ - (((Tpix) - 1) << FShft (LCCR1_ELW)) + /* [1..256 Tpix] */ \ + (((Tpix) - 1) << FShft (LCCR1_ELW)) #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */ - /* Wait count - 1 [Tpix] */ + /* Wait count - 1 [Tpix] */ #define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \ - /* [1..256 Tpix] */ \ - (((Tpix) - 1) << FShft (LCCR1_BLW)) + /* [1..256 Tpix] */ \ + (((Tpix) - 1) << FShft (LCCR1_BLW)) #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ #define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \ - (((Line) - 1) << FShft (LCCR2_LPP)) + (((Line) - 1) << FShft (LCCR2_LPP)) #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ - /* Width - 1 [Tln] (L_FCLK) */ + /* Width - 1 [Tln] (L_FCLK) */ #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ - /* Width [1..64 Tln] */ \ - (((Tln) - 1) << FShft (LCCR2_VSW)) + /* Width [1..64 Tln] */ \ + (((Tln) - 1) << FShft (LCCR2_VSW)) #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */ - /* count [Tln] */ + /* count [Tln] */ #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ - /* [0..255 Tln] */ \ - ((Tln) << FShft (LCCR2_EFW)) + /* [0..255 Tln] */ \ + ((Tln) << FShft (LCCR2_EFW)) #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */ - /* Wait count [Tln] */ + /* Wait count [Tln] */ #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ - /* [0..255 Tln] */ \ - ((Tln) << FShft (LCCR2_BFW)) + /* [0..255 Tln] */ \ + ((Tln) << FShft (LCCR2_BFW)) #if 0 #define LCCR3_PCD (0xff) /* Pixel clock divisor */ @@ -1261,25 +1260,25 @@ typedef void (*ExcpHndlr) (void) ; #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */ #define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor */ \ - (((Div) << FShft (LCCR3_PCD))) + (((Div) << FShft (LCCR3_PCD))) #define LCCR3_BPP Fld (3, 24) /* Bit Per Pixel */ #define LCCR3_Bpp(Bpp) /* Bit Per Pixel */ \ - (((Bpp) << FShft (LCCR3_BPP))) + (((Bpp) << FShft (LCCR3_BPP))) #define LCCR3_ACB Fld (8, 8) /* AC Bias */ #define LCCR3_Acb(Acb) /* BAC Bias */ \ - (((Acb) << FShft (LCCR3_ACB))) + (((Acb) << FShft (LCCR3_ACB))) #define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */ - /* pulse active High */ + /* pulse active High */ #define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */ #define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */ - /* active High */ + /* active High */ #define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */ - /* active Low */ + /* active Low */ #define LCSR_LDD (1 << 0) /* LCD Disable Done */ #define LCSR_SOF (1 << 1) /* Start of frame */ @@ -1338,7 +1337,7 @@ typedef void (*ExcpHndlr) (void) ; #define MDCNFG_DE2 0x00010000 #define MDCNFG_DE3 0x00020000 #define MDCNFG_DWID0 0x00000004 - + #define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */ #define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */ #define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */ diff --git a/include/asm-arm/arch-sa1100/bitfield.h b/include/asm-arm/arch-sa1100/bitfield.h index f1f0e3387d9..2ac5ea21cfd 100644 --- a/include/asm-arm/arch-sa1100/bitfield.h +++ b/include/asm-arm/arch-sa1100/bitfield.h @@ -11,7 +11,6 @@ */ - #ifndef __BITFIELD_H #define __BITFIELD_H @@ -88,7 +87,7 @@ */ #define FInsrt(Value, Field) \ - (UData (Value) << FShft (Field)) + (UData (Value) << FShft (Field)) /* @@ -107,7 +106,7 @@ */ #define FExtr(Data, Field) \ - ((UData (Data) >> FShft (Field)) & FAlnMsk (Field)) + ((UData (Data) >> FShft (Field)) & FAlnMsk (Field)) #endif /* __BITFIELD_H */ diff --git a/include/asm-arm/bitops.h b/include/asm-arm/bitops.h index 47338585a38..4b8bab28373 100644 --- a/include/asm-arm/bitops.h +++ b/include/asm-arm/bitops.h @@ -106,7 +106,7 @@ static inline unsigned long ffz(unsigned long word) if (word & 0x0f000000) { k -= 4; word <<= 4; } if (word & 0x30000000) { k -= 2; word <<= 2; } if (word & 0x40000000) { k -= 1; } - return k; + return k; } /* diff --git a/include/asm-arm/byteorder.h b/include/asm-arm/byteorder.h index d648a1915c3..c3489f1e1fc 100644 --- a/include/asm-arm/byteorder.h +++ b/include/asm-arm/byteorder.h @@ -30,4 +30,3 @@ #endif #endif - diff --git a/include/asm-arm/proc-armv/ptrace.h b/include/asm-arm/proc-armv/ptrace.h index 51708b9b1ac..79cc6443f43 100644 --- a/include/asm-arm/proc-armv/ptrace.h +++ b/include/asm-arm/proc-armv/ptrace.h @@ -107,4 +107,3 @@ static inline int valid_user_regs(struct pt_regs *regs) #endif /* __ASSEMBLY__ */ #endif - diff --git a/include/asm-arm/proc-armv/system.h b/include/asm-arm/proc-armv/system.h index 479f5532085..e7b0fe6fb7a 100644 --- a/include/asm-arm/proc-armv/system.h +++ b/include/asm-arm/proc-armv/system.h @@ -56,7 +56,7 @@ extern unsigned long cr_alignment; /* defined in entry-armv.S */ : \ : "memory"); \ }) - + /* * Enable IRQs */ diff --git a/include/asm-arm/ptrace.h b/include/asm-arm/ptrace.h index 0e4482b8c7a..73c9087b508 100644 --- a/include/asm-arm/ptrace.h +++ b/include/asm-arm/ptrace.h @@ -31,4 +31,3 @@ extern void show_regs(struct pt_regs *); #endif /* __ASSEMBLY__ */ #endif - diff --git a/include/asm-arm/setup.h b/include/asm-arm/setup.h index c20b44813b8..89df4dc708f 100644 --- a/include/asm-arm/setup.h +++ b/include/asm-arm/setup.h @@ -76,7 +76,6 @@ struct param_struct { }; - /* * The new way of passing information: a list of tagged entries */ diff --git a/include/asm-arm/types.h b/include/asm-arm/types.h index 39d5290f54f..13e9806bdc0 100644 --- a/include/asm-arm/types.h +++ b/include/asm-arm/types.h @@ -48,4 +48,3 @@ typedef u32 dma_addr_t; #endif /* __KERNEL__ */ #endif - diff --git a/include/asm-i386/bitops.h b/include/asm-i386/bitops.h index 7d29335fdee..b768e20fbb6 100644 --- a/include/asm-i386/bitops.h +++ b/include/asm-i386/bitops.h @@ -116,7 +116,7 @@ static __inline__ void change_bit(int nr, volatile void * addr) * @nr: Bit to set * @addr: Address to count from * - * This operation is atomic and cannot be reordered. + * This operation is atomic and cannot be reordered. * It also implies a memory barrier. */ static __inline__ int test_and_set_bit(int nr, volatile void * addr) @@ -135,7 +135,7 @@ static __inline__ int test_and_set_bit(int nr, volatile void * addr) * @nr: Bit to set * @addr: Address to count from * - * This operation is non-atomic and can be reordered. + * This operation is non-atomic and can be reordered. * If two examples of this operation race, one can appear to succeed * but actually fail. You must protect multiple accesses with a lock. */ @@ -155,7 +155,7 @@ static __inline__ int __test_and_set_bit(int nr, volatile void * addr) * @nr: Bit to set * @addr: Address to count from * - * This operation is atomic and cannot be reordered. + * This operation is atomic and cannot be reordered. * It also implies a memory barrier. */ static __inline__ int test_and_clear_bit(int nr, volatile void * addr) @@ -174,7 +174,7 @@ static __inline__ int test_and_clear_bit(int nr, volatile void * addr) * @nr: Bit to set * @addr: Address to count from * - * This operation is non-atomic and can be reordered. + * This operation is non-atomic and can be reordered. * If two examples of this operation race, one can appear to succeed * but actually fail. You must protect multiple accesses with a lock. */ @@ -206,7 +206,7 @@ static __inline__ int __test_and_change_bit(int nr, volatile void * addr) * @nr: Bit to set * @addr: Address to count from * - * This operation is atomic and cannot be reordered. + * This operation is atomic and cannot be reordered. * It also implies a memory barrier. */ static __inline__ int test_and_change_bit(int nr, volatile void * addr) @@ -292,7 +292,7 @@ static __inline__ int find_next_zero_bit (void * addr, int size, int offset) { unsigned long * p = ((unsigned long *) addr) + (offset >> 5); int set = 0, bit = offset & 31, res; - + if (bit) { /* * Look for zero in first byte diff --git a/include/asm-i386/i8254.h b/include/asm-i386/i8254.h index e13f04e589d..aafdfb8060d 100644 --- a/include/asm-i386/i8254.h +++ b/include/asm-i386/i8254.h @@ -29,7 +29,6 @@ #define _ASMI386_I8954_H_ 1 - #define PIT_T0 0x00 /* PIT channel 0 count/status */ #define PIT_T1 0x01 /* PIT channel 1 count/status */ #define PIT_T2 0x02 /* PIT channel 2 count/status */ diff --git a/include/asm-i386/i8259.h b/include/asm-i386/i8259.h index 0419e0e266a..774d7a31e79 100644 --- a/include/asm-i386/i8259.h +++ b/include/asm-i386/i8259.h @@ -78,7 +78,7 @@ /* ICW2 is the starting vector number */ -/* ICW2 is bit-mask of present slaves for a master device, +/* ICW2 is bit-mask of present slaves for a master device, * or the slave ID for a slave device */ /* ICW4 bits */ diff --git a/include/asm-i386/ibmpc.h b/include/asm-i386/ibmpc.h index abdd1d76292..e35cbd887ad 100644 --- a/include/asm-i386/ibmpc.h +++ b/include/asm-i386/ibmpc.h @@ -1,7 +1,7 @@ /* * (C) Copyright 2002 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se - * + * * See file CREDITS for list of people who contributed to this * project. * diff --git a/include/asm-i386/ic/sc520.h b/include/asm-i386/ic/sc520.h index 1836f99a6de..d5abbbe52af 100644 --- a/include/asm-i386/ic/sc520.h +++ b/include/asm-i386/ic/sc520.h @@ -230,7 +230,7 @@ #define UART1_DIS 0x01 /* UART1 Disable */ /* bus mapping constants (used for PCI core initialization) */ /* bus mapping constants */ -#define SC520_REG_ADDR 0x00000cf8 +#define SC520_REG_ADDR 0x00000cf8 #define SC520_REG_DATA 0x00000cfc @@ -242,7 +242,7 @@ #define SC520_ISA_IO_BUS 0x00000000 #define SC520_ISA_IO_SIZE 0x00001000 -/* PCI I/O space from 0x1000 to 0xdfff +/* PCI I/O space from 0x1000 to 0xdfff * (make 0xe000-0xfdff available for stuff like PCCard boot) */ #define SC520_PCI_IO_PHYS 0x00001000 #define SC520_PCI_IO_BUS 0x00001000 @@ -253,7 +253,7 @@ #define SC520_PCI_MEMORY_BUS 0x00000000 #define SC520_PCI_MEMORY_SIZE 0x10000000 -/* PCI bus memory from 0x10000000 to 0x26ffffff +/* PCI bus memory from 0x10000000 to 0x26ffffff * (make 0x27000000 - 0x27ffffff available for stuff like PCCard boot) */ #define SC520_PCI_MEM_PHYS 0x10000000 #define SC520_PCI_MEM_BUS 0x10000000 @@ -275,7 +275,7 @@ #define SC520_IRQ7 22 #define SC520_IRQ8 3 #define SC520_IRQ9 4 -#define SC520_IRQ10 5 +#define SC520_IRQ10 5 #define SC520_IRQ11 6 #define SC520_IRQ12 7 #define SC520_IRQ13 8 diff --git a/include/asm-i386/io.h b/include/asm-i386/io.h index d17d45e9188..85d44aaa15b 100644 --- a/include/asm-i386/io.h +++ b/include/asm-i386/io.h @@ -84,7 +84,6 @@ #define isa_memcpy_toio(a,b,c) memcpy_toio((a),(b),(c)) - static inline int check_signature(unsigned long io_addr, const unsigned char *signature, int length) { @@ -103,7 +102,7 @@ out: /** * isa_check_signature - find BIOS signatures - * @io_addr: mmio address to check + * @io_addr: mmio address to check * @signature: signature block * @length: length of signature * @@ -113,7 +112,7 @@ out: * This function is deprecated. New drivers should use ioremap and * check_signature. */ - + static inline int isa_check_signature(unsigned long io_addr, const unsigned char *signature, int length) @@ -158,7 +157,7 @@ __asm__ __volatile__ ("out" #s " %" s1 "0,%" s2 "1" #define __OUT(s,s1,x) \ __OUT1(s,x) __OUT2(s,s1,"w") : : "a" (value), "Nd" (port)); } \ -__OUT1(s##_p,x) __OUT2(s,s1,"w") __FULL_SLOW_DOWN_IO : : "a" (value), "Nd" (port));} +__OUT1(s##_p,x) __OUT2(s,s1,"w") __FULL_SLOW_DOWN_IO : : "a" (value), "Nd" (port));} #define __IN1(s) \ static inline RETURN_TYPE in##s(unsigned short port) { RETURN_TYPE _v; @@ -168,7 +167,7 @@ __asm__ __volatile__ ("in" #s " %" s2 "1,%" s1 "0" #define __IN(s,s1,i...) \ __IN1(s) __IN2(s,s1,"w") : "=a" (_v) : "Nd" (port) ,##i ); return _v; } \ -__IN1(s##_p) __IN2(s,s1,"w") __FULL_SLOW_DOWN_IO : "=a" (_v) : "Nd" (port) ,##i ); return _v; } +__IN1(s##_p) __IN2(s,s1,"w") __FULL_SLOW_DOWN_IO : "=a" (_v) : "Nd" (port) ,##i ); return _v; } #define __INS(s) \ static inline void ins##s(unsigned short port, void * addr, unsigned long count) \ diff --git a/include/asm-i386/pci.h b/include/asm-i386/pci.h index 3a91f57cf4b..bde95509a4b 100644 --- a/include/asm-i386/pci.h +++ b/include/asm-i386/pci.h @@ -32,6 +32,4 @@ int pci_shadow_rom(pci_dev_t dev, unsigned char *dest); void pci_remove_rom_window(struct pci_controller* hose, u32 addr); u32 pci_get_rom_window(struct pci_controller* hose, int size); - - #endif diff --git a/include/asm-i386/processor.h b/include/asm-i386/processor.h index c175193315f..5dedba82ca7 100644 --- a/include/asm-i386/processor.h +++ b/include/asm-i386/processor.h @@ -1,7 +1,7 @@ /* * (C) Copyright 2002 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se - * + * * See file CREDITS for list of people who contributed to this * project. * diff --git a/include/asm-i386/ptrace.h b/include/asm-i386/ptrace.h index d99e464007b..750e40d030c 100644 --- a/include/asm-i386/ptrace.h +++ b/include/asm-i386/ptrace.h @@ -20,7 +20,7 @@ #define SS 16 #define FRAME_SIZE 17 -/* this struct defines the way the registers are stored on the +/* this struct defines the way the registers are stored on the stack during a system call. */ struct pt_regs { diff --git a/include/asm-i386/realmode.h b/include/asm-i386/realmode.h index a84f1281733..9177e4ec0d4 100644 --- a/include/asm-i386/realmode.h +++ b/include/asm-i386/realmode.h @@ -1,7 +1,7 @@ /* * (C) Copyright 2002 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se - * + * * See file CREDITS for list of people who contributed to this * project. * diff --git a/include/asm-i386/types.h b/include/asm-i386/types.h index bb100ec4e3c..69f8a5a7c6d 100644 --- a/include/asm-i386/types.h +++ b/include/asm-i386/types.h @@ -48,4 +48,3 @@ typedef u32 dma_addr_t; #endif /* __KERNEL__ */ #endif - diff --git a/include/asm-i386/u-boot.h b/include/asm-i386/u-boot.h index dc5dd727c9c..346673228ec 100644 --- a/include/asm-i386/u-boot.h +++ b/include/asm-i386/u-boot.h @@ -2,7 +2,7 @@ * (C) Copyright 2002 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> * Marius Groeger <mgroeger@sysgo.de> - * + * * (C) Copyright 2002 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> * Alex Zuepke <azu@sysgo.de> @@ -47,7 +47,7 @@ typedef struct bd_info { unsigned long bi_boot_params; /* where this board expects params */ struct environment_s *bi_env; struct /* RAM configuration */ - { + { ulong start; ulong size; }bi_dram[CONFIG_NR_DRAM_BANKS]; diff --git a/include/asm-i386/zimage.h b/include/asm-i386/zimage.h index 688682611fd..c7103b1f37e 100644 --- a/include/asm-i386/zimage.h +++ b/include/asm-i386/zimage.h @@ -1,7 +1,7 @@ /* * (C) Copyright 2002 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se - * + * * See file CREDITS for list of people who contributed to this * project. * @@ -24,7 +24,7 @@ #ifndef _ASM_ZIMAGE_H_ #define _ASM_ZIMAGE_H_ -/* linux i386 zImage/bzImage header. Offsets relative to +/* linux i386 zImage/bzImage header. Offsets relative to * the start of the image */ #define CMD_LINE_MAGIC_OFF 0x020 /* Magic 0xa33f if the offset below is valid */ @@ -62,10 +62,10 @@ #define SETUP_MAX_SIZE 32768 #define SETUP_START_OFFSET 0x200 -#define BZIMAGE_LOAD_ADDR 0x100000 +#define BZIMAGE_LOAD_ADDR 0x100000 #define ZIMAGE_LOAD_ADDR 0x10000 - -void *load_zimage(char *image, unsigned long kernel_size, + +void *load_zimage(char *image, unsigned long kernel_size, unsigned long initrd_addr, unsigned long initrd_size, int auto_boot); diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index edff4c0fe86..56d7225bb7b 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h @@ -161,7 +161,7 @@ extern __inline__ void __change_bit(int nr, volatile void * addr) * @nr: Bit to set * @addr: Address to count from * - * This operation is atomic and cannot be reordered. + * This operation is atomic and cannot be reordered. * It also implies a memory barrier. */ extern __inline__ int @@ -190,7 +190,7 @@ test_and_set_bit(int nr, volatile void *addr) * @nr: Bit to set * @addr: Address to count from * - * This operation is non-atomic and can be reordered. + * This operation is non-atomic and can be reordered. * If two examples of this operation race, one can appear to succeed * but actually fail. You must protect multiple accesses with a lock. */ @@ -212,7 +212,7 @@ extern __inline__ int __test_and_set_bit(int nr, volatile void * addr) * @nr: Bit to set * @addr: Address to count from * - * This operation is atomic and cannot be reordered. + * This operation is atomic and cannot be reordered. * It also implies a memory barrier. */ extern __inline__ int @@ -242,7 +242,7 @@ test_and_clear_bit(int nr, volatile void *addr) * @nr: Bit to set * @addr: Address to count from * - * This operation is non-atomic and can be reordered. + * This operation is non-atomic and can be reordered. * If two examples of this operation race, one can appear to succeed * but actually fail. You must protect multiple accesses with a lock. */ @@ -264,7 +264,7 @@ extern __inline__ int __test_and_clear_bit(int nr, volatile void * addr) * @nr: Bit to set * @addr: Address to count from * - * This operation is atomic and cannot be reordered. + * This operation is atomic and cannot be reordered. * It also implies a memory barrier. */ extern __inline__ int @@ -293,7 +293,7 @@ test_and_change_bit(int nr, volatile void *addr) * @nr: Bit to set * @addr: Address to count from * - * This operation is non-atomic and can be reordered. + * This operation is non-atomic and can be reordered. * If two examples of this operation race, one can appear to succeed * but actually fail. You must protect multiple accesses with a lock. */ @@ -420,7 +420,7 @@ extern __inline__ void __change_bit(int nr, volatile void * addr) * @nr: Bit to set * @addr: Address to count from * - * This operation is atomic and cannot be reordered. + * This operation is atomic and cannot be reordered. * It also implies a memory barrier. */ extern __inline__ int test_and_set_bit(int nr, volatile void * addr) @@ -444,7 +444,7 @@ extern __inline__ int test_and_set_bit(int nr, volatile void * addr) * @nr: Bit to set * @addr: Address to count from * - * This operation is non-atomic and can be reordered. + * This operation is non-atomic and can be reordered. * If two examples of this operation race, one can appear to succeed * but actually fail. You must protect multiple accesses with a lock. */ @@ -466,7 +466,7 @@ extern __inline__ int __test_and_set_bit(int nr, volatile void * addr) * @nr: Bit to set * @addr: Address to count from * - * This operation is atomic and cannot be reordered. + * This operation is atomic and cannot be reordered. * It also implies a memory barrier. */ extern __inline__ int test_and_clear_bit(int nr, volatile void * addr) @@ -490,7 +490,7 @@ extern __inline__ int test_and_clear_bit(int nr, volatile void * addr) * @nr: Bit to set * @addr: Address to count from * - * This operation is non-atomic and can be reordered. + * This operation is non-atomic and can be reordered. * If two examples of this operation race, one can appear to succeed * but actually fail. You must protect multiple accesses with a lock. */ @@ -512,7 +512,7 @@ extern __inline__ int __test_and_clear_bit(int nr, volatile void * addr) * @nr: Bit to set * @addr: Address to count from * - * This operation is atomic and cannot be reordered. + * This operation is atomic and cannot be reordered. * It also implies a memory barrier. */ extern __inline__ int test_and_change_bit(int nr, volatile void * addr) @@ -536,7 +536,7 @@ extern __inline__ int test_and_change_bit(int nr, volatile void * addr) * @nr: Bit to set * @addr: Address to count from * - * This operation is non-atomic and can be reordered. + * This operation is non-atomic and can be reordered. * If two examples of this operation race, one can appear to succeed * but actually fail. You must protect multiple accesses with a lock. */ @@ -638,7 +638,7 @@ extern __inline__ int find_next_zero_bit (void * addr, int size, int offset) unsigned int *p = ((unsigned int *) addr) + (offset >> 5); int set = 0, bit = offset & 31, res; unsigned long dummy; - + if (bit) { /* * Look for zero in first byte @@ -789,7 +789,7 @@ extern int find_first_zero_bit (void *addr, unsigned size); #endif #define find_first_zero_bit(addr, size) \ - find_next_zero_bit((addr), (size), 0) + find_next_zero_bit((addr), (size), 0) #endif /* (__MIPSEB__) */ @@ -835,7 +835,7 @@ extern __inline__ int ext2_test_bit(int nr, const void * addr) } #define ext2_find_first_zero_bit(addr, size) \ - ext2_find_next_zero_bit((addr), (size), 0) + ext2_find_next_zero_bit((addr), (size), 0) extern __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset) { @@ -894,8 +894,8 @@ found_middle: #define ext2_test_bit(nr, addr) test_bit((nr), (addr)) #define ext2_find_first_zero_bit(addr, size) find_first_zero_bit((addr), (size)) #define ext2_find_next_zero_bit(addr, size, offset) \ - find_next_zero_bit((addr), (size), (offset)) - + find_next_zero_bit((addr), (size), (offset)) + #endif /* !(__MIPSEB__) */ /* diff --git a/include/asm-mips/inca-ip.h b/include/asm-mips/inca-ip.h index 0c5f1d73cb5..e787a1dee65 100644 --- a/include/asm-mips/inca-ip.h +++ b/include/asm-mips/inca-ip.h @@ -2,41 +2,41 @@ /****************************************************************************** Copyright (c) 2002, Infineon Technologies. All rights reserved. - No Warranty - Because the program is licensed free of charge, there is no warranty for - the program, to the extent permitted by applicable law. Except when - otherwise stated in writing the copyright holders and/or other parties - provide the program "as is" without warranty of any kind, either - expressed or implied, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose. The - entire risk as to the quality and performance of the program is with - you. should the program prove defective, you assume the cost of all - necessary servicing, repair or correction. - - In no event unless required by applicable law or agreed to in writing - will any copyright holder, or any other party who may modify and/or - redistribute the program as permitted above, be liable to you for - damages, including any general, special, incidental or consequential - damages arising out of the use or inability to use the program - (including but not limited to loss of data or data being rendered - inaccurate or losses sustained by you or third parties or a failure of - the program to operate with any other programs), even if such holder or - other party has been advised of the possibility of such damages. + No Warranty + Because the program is licensed free of charge, there is no warranty for + the program, to the extent permitted by applicable law. Except when + otherwise stated in writing the copyright holders and/or other parties + provide the program "as is" without warranty of any kind, either + expressed or implied, including, but not limited to, the implied + warranties of merchantability and fitness for a particular purpose. The + entire risk as to the quality and performance of the program is with + you. should the program prove defective, you assume the cost of all + necessary servicing, repair or correction. + + In no event unless required by applicable law or agreed to in writing + will any copyright holder, or any other party who may modify and/or + redistribute the program as permitted above, be liable to you for + damages, including any general, special, incidental or consequential + damages arising out of the use or inability to use the program + (including but not limited to loss of data or data being rendered + inaccurate or losses sustained by you or third parties or a failure of + the program to operate with any other programs), even if such holder or + other party has been advised of the possibility of such damages. ******************************************************************************/ - - + + /***********************************************************************/ /* Module : WDT register address and bits */ /***********************************************************************/ - + #define INCA_IP_WDT (0xB8000000) -/***********************************************************************/ +/***********************************************************************/ + - -/***Reset Status Register Power On***/ +/***Reset Status Register Power On***/ #define INCA_IP_WDT_RST_SR ((volatile u32*)(INCA_IP_WDT+ 0x0014)) - -/***Reset Request Register***/ + +/***Reset Request Register***/ #define INCA_IP_WDT_RST_REQ ((volatile u32*)(INCA_IP_WDT+ 0x0010)) #define INCA_IP_WDT_RST_REQ_SWBOOT (1 << 24) #define INCA_IP_WDT_RST_REQ_SWCFG (1 << 16) @@ -46,37 +46,37 @@ #define INCA_IP_WDT_RST_REQ_RREXT (1 << 2) #define INCA_IP_WDT_RST_REQ_RRDSP (1 << 1) #define INCA_IP_WDT_RST_REQ_RRCPU (1 << 0) - -/***NMI Status Register***/ + +/***NMI Status Register***/ #define INCA_IP_WDT_NMISR ((volatile u32*)(INCA_IP_WDT+ 0x002C)) #define INCA_IP_WDT_NMISR_NMIWDT (1 << 2) #define INCA_IP_WDT_NMISR_NMIPLL (1 << 1) #define INCA_IP_WDT_NMISR_NMIEXT (1 << 0) - -/***Manufacturer Identification Register***/ + +/***Manufacturer Identification Register***/ #define INCA_IP_WDT_MANID ((volatile u32*)(INCA_IP_WDT+ 0x0070)) #define INCA_IP_WDT_MANID_MANUF (value) (((( 1 << 11) - 1) & (value)) << 5) - -/***Chip Identification Register***/ + +/***Chip Identification Register***/ #define INCA_IP_WDT_CHIPID ((volatile u32*)(INCA_IP_WDT+ 0x0074)) #define INCA_IP_WDT_CHIPID_VERSION (value) (((( 1 << 4) - 1) & (value)) << 28) #define INCA_IP_WDT_CHIPID_PART_NUMBER (value) (((( 1 << 16) - 1) & (value)) << 12) #define INCA_IP_WDT_CHIPID_MANID (value) (((( 1 << 11) - 1) & (value)) << 1) - -/***Redesign Tracing Identification Register***/ + +/***Redesign Tracing Identification Register***/ #define INCA_IP_WDT_RTID ((volatile u32*)(INCA_IP_WDT+ 0x0078)) #define INCA_IP_WDT_RTID_LC (1 << 15) #define INCA_IP_WDT_RTID_RIX (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***Watchdog Timer Control Register 0***/ + +/***Watchdog Timer Control Register 0***/ #define INCA_IP_WDT_WDT_CON0 ((volatile u32*)(INCA_IP_WDT+ 0x0020)) - -/***Watchdog Timer Control Register 1***/ + +/***Watchdog Timer Control Register 1***/ #define INCA_IP_WDT_WDT_CON1 ((volatile u32*)(INCA_IP_WDT+ 0x0024)) #define INCA_IP_WDT_WDT_CON1_WDTDR (1 << 3) #define INCA_IP_WDT_WDT_CON1_WDTIR (1 << 2) - -/***Watchdog Timer Status Register***/ + +/***Watchdog Timer Status Register***/ #define INCA_IP_WDT_WDT_SR ((volatile u32*)(INCA_IP_WDT+ 0x0028)) #define INCA_IP_WDT_WDT_SR_WDTTIM (value) (((( 1 << 16) - 1) & (value)) << 16) #define INCA_IP_WDT_WDT_SR_WDTPR (1 << 5) @@ -84,66 +84,66 @@ #define INCA_IP_WDT_WDT_SR_WDTDS (1 << 3) #define INCA_IP_WDT_WDT_SR_WDTIS (1 << 2) #define INCA_IP_WDT_WDT_SR_WDTOE (1 << 1) -#define INCA_IP_WDT_WDT_SR_WDTAE (1 << 0) - +#define INCA_IP_WDT_WDT_SR_WDTAE (1 << 0) + /***********************************************************************/ /* Module : CGU register address and bits */ /***********************************************************************/ - + #define INCA_IP_CGU (0xBF107000) -/***********************************************************************/ +/***********************************************************************/ + - -/***CGU PLL1 Control Register***/ +/***CGU PLL1 Control Register***/ #define INCA_IP_CGU_CGU_PLL1CR ((volatile u32*)(INCA_IP_CGU+ 0x0008)) #define INCA_IP_CGU_CGU_PLL1CR_SWRST (1 << 31) #define INCA_IP_CGU_CGU_PLL1CR_EN (1 << 30) #define INCA_IP_CGU_CGU_PLL1CR_NDIV (value) (((( 1 << 6) - 1) & (value)) << 16) #define INCA_IP_CGU_CGU_PLL1CR_MDIV (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***CGU PLL0 Control Register***/ + +/***CGU PLL0 Control Register***/ #define INCA_IP_CGU_CGU_PLL0CR ((volatile u32*)(INCA_IP_CGU+ 0x0000)) #define INCA_IP_CGU_CGU_PLL0CR_SWRST (1 << 31) #define INCA_IP_CGU_CGU_PLL0CR_EN (1 << 30) #define INCA_IP_CGU_CGU_PLL0CR_NDIV (value) (((( 1 << 6) - 1) & (value)) << 16) #define INCA_IP_CGU_CGU_PLL0CR_MDIV (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***CGU PLL0 Status Register***/ + +/***CGU PLL0 Status Register***/ #define INCA_IP_CGU_CGU_PLL0SR ((volatile u32*)(INCA_IP_CGU+ 0x0004)) #define INCA_IP_CGU_CGU_PLL0SR_LOCK (1 << 31) #define INCA_IP_CGU_CGU_PLL0SR_RCF (1 << 29) #define INCA_IP_CGU_CGU_PLL0SR_PLLBYP (1 << 15) - -/***CGU PLL1 Status Register***/ + +/***CGU PLL1 Status Register***/ #define INCA_IP_CGU_CGU_PLL1SR ((volatile u32*)(INCA_IP_CGU+ 0x000C)) #define INCA_IP_CGU_CGU_PLL1SR_LOCK (1 << 31) #define INCA_IP_CGU_CGU_PLL1SR_RCF (1 << 29) #define INCA_IP_CGU_CGU_PLL1SR_PLLBYP (1 << 15) - -/***CGU Divider Control Register***/ + +/***CGU Divider Control Register***/ #define INCA_IP_CGU_CGU_DIVCR ((volatile u32*)(INCA_IP_CGU+ 0x0010)) - -/***CGU Multiplexer Control Register***/ + +/***CGU Multiplexer Control Register***/ #define INCA_IP_CGU_CGU_MUXCR ((volatile u32*)(INCA_IP_CGU+ 0x0014)) #define INCA_IP_CGU_CGU_MUXCR_SWRST (1 << 31) #define INCA_IP_CGU_CGU_MUXCR_MUXII (1 << 1) #define INCA_IP_CGU_CGU_MUXCR_MUXI (1 << 0) - -/***CGU Fractional Divider Control Register***/ + +/***CGU Fractional Divider Control Register***/ #define INCA_IP_CGU_CGU_FDCR ((volatile u32*)(INCA_IP_CGU+ 0x0018)) #define INCA_IP_CGU_CGU_FDCR_FDEN (1 << 31) #define INCA_IP_CGU_CGU_FDCR_INTEGER (value) (((( 1 << 12) - 1) & (value)) << 16) -#define INCA_IP_CGU_CGU_FDCR_FRACTION (value) (((( 1 << 16) - 1) & (value)) << 0) - +#define INCA_IP_CGU_CGU_FDCR_FRACTION (value) (((( 1 << 16) - 1) & (value)) << 0) + /***********************************************************************/ /* Module : PMU register address and bits */ /***********************************************************************/ - + #define INCA_IP_PMU (0xBF102000) -/***********************************************************************/ +/***********************************************************************/ + - -/***PM Global Enable Register***/ +/***PM Global Enable Register***/ #define INCA_IP_PMU_PM_GEN ((volatile u32*)(INCA_IP_PMU+ 0x0000)) #define INCA_IP_PMU_PM_GEN_EN16 (1 << 16) #define INCA_IP_PMU_PM_GEN_EN15 (1 << 15) @@ -161,8 +161,8 @@ #define INCA_IP_PMU_PM_GEN_EN3 (1 << 3) #define INCA_IP_PMU_PM_GEN_EN2 (1 << 2) #define INCA_IP_PMU_PM_GEN_EN0 (1 << 0) - -/***PM Power Down Enable Register***/ + +/***PM Power Down Enable Register***/ #define INCA_IP_PMU_PM_PDEN ((volatile u32*)(INCA_IP_PMU+ 0x0008)) #define INCA_IP_PMU_PM_PDEN_EN16 (1 << 16) #define INCA_IP_PMU_PM_PDEN_EN15 (1 << 15) @@ -179,8 +179,8 @@ #define INCA_IP_PMU_PM_PDEN_EN3 (1 << 3) #define INCA_IP_PMU_PM_PDEN_EN2 (1 << 2) #define INCA_IP_PMU_PM_PDEN_EN0 (1 << 0) - -/***PM Wake-Up from Power Down Register***/ + +/***PM Wake-Up from Power Down Register***/ #define INCA_IP_PMU_PM_WUP ((volatile u32*)(INCA_IP_PMU+ 0x0010)) #define INCA_IP_PMU_PM_WUP_WUP16 (1 << 16) #define INCA_IP_PMU_PM_WUP_WUP15 (1 << 15) @@ -197,31 +197,31 @@ #define INCA_IP_PMU_PM_WUP_WUP3 (1 << 3) #define INCA_IP_PMU_PM_WUP_WUP2 (1 << 2) #define INCA_IP_PMU_PM_WUP_WUP0 (1 << 0) - -/***PM Control Register***/ + +/***PM Control Register***/ #define INCA_IP_PMU_PM_CR ((volatile u32*)(INCA_IP_PMU+ 0x0014)) #define INCA_IP_PMU_PM_CR_AWEN (1 << 31) #define INCA_IP_PMU_PM_CR_SWRST (1 << 30) #define INCA_IP_PMU_PM_CR_SWCR (1 << 2) -#define INCA_IP_PMU_PM_CR_CRD (value) (((( 1 << 2) - 1) & (value)) << 0) - +#define INCA_IP_PMU_PM_CR_CRD (value) (((( 1 << 2) - 1) & (value)) << 0) + /***********************************************************************/ /* Module : BCU register address and bits */ /***********************************************************************/ - + #define INCA_IP_BCU (0xB8000100) -/***********************************************************************/ +/***********************************************************************/ + - -/***BCU Control Register (0010H)***/ +/***BCU Control Register (0010H)***/ #define INCA_IP_BCU_BCU_CON ((volatile u32*)(INCA_IP_BCU+ 0x0010)) #define INCA_IP_BCU_BCU_CON_SPC (value) (((( 1 << 8) - 1) & (value)) << 24) #define INCA_IP_BCU_BCU_CON_SPE (1 << 19) #define INCA_IP_BCU_BCU_CON_PSE (1 << 18) #define INCA_IP_BCU_BCU_CON_DBG (1 << 16) #define INCA_IP_BCU_BCU_CON_TOUT (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***BCU Error Control Capture Register (0020H)***/ + +/***BCU Error Control Capture Register (0020H)***/ #define INCA_IP_BCU_BCU_ECON ((volatile u32*)(INCA_IP_BCU+ 0x0020)) #define INCA_IP_BCU_BCU_ECON_TAG (value) (((( 1 << 4) - 1) & (value)) << 24) #define INCA_IP_BCU_BCU_ECON_RDN (1 << 23) @@ -233,31 +233,31 @@ #define INCA_IP_BCU_BCU_ECON_TOUT (1 << 16) #define INCA_IP_BCU_BCU_ECON_ERRCNT (value) (((( 1 << 16) - 1) & (value)) << 0) #define INCA_IP_BCU_BCU_ECON_OPC (value) (((( 1 << 4) - 1) & (value)) << 28) - -/***BCU Error Address Capture Register (0024 H)***/ + +/***BCU Error Address Capture Register (0024 H)***/ #define INCA_IP_BCU_BCU_EADD ((volatile u32*)(INCA_IP_BCU+ 0x0024)) #define INCA_IP_BCU_BCU_EADD_FPIADR - -/***BCU Error Data Capture Register (0028H)***/ + +/***BCU Error Data Capture Register (0028H)***/ #define INCA_IP_BCU_BCU_EDAT ((volatile u32*)(INCA_IP_BCU+ 0x0028)) -#define INCA_IP_BCU_BCU_EDAT_FPIDAT - +#define INCA_IP_BCU_BCU_EDAT_FPIDAT + /***********************************************************************/ /* Module : MBC register address and bits */ /***********************************************************************/ - + #define INCA_IP_MBC (0xBF103000) -/***********************************************************************/ +/***********************************************************************/ - -/***Mailbox CPU Configuration Register***/ + +/***Mailbox CPU Configuration Register***/ #define INCA_IP_MBC_MBC_CFG ((volatile u32*)(INCA_IP_MBC+ 0x0080)) #define INCA_IP_MBC_MBC_CFG_SWAP (value) (((( 1 << 2) - 1) & (value)) << 6) #define INCA_IP_MBC_MBC_CFG_RES (1 << 5) #define INCA_IP_MBC_MBC_CFG_FWID (value) (((( 1 << 4) - 1) & (value)) << 1) #define INCA_IP_MBC_MBC_CFG_SIZE (1 << 0) - -/***Mailbox CPU Interrupt Status Register***/ + +/***Mailbox CPU Interrupt Status Register***/ #define INCA_IP_MBC_MBC_ISR ((volatile u32*)(INCA_IP_MBC+ 0x0084)) #define INCA_IP_MBC_MBC_ISR_B3DA (1 << 31) #define INCA_IP_MBC_MBC_ISR_B2DA (1 << 30) @@ -265,8 +265,8 @@ #define INCA_IP_MBC_MBC_ISR_B0E (1 << 28) #define INCA_IP_MBC_MBC_ISR_WDT (1 << 27) #define INCA_IP_MBC_MBC_ISR_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) - -/***Mailbox CPU Mask Register***/ + +/***Mailbox CPU Mask Register***/ #define INCA_IP_MBC_MBC_MSK ((volatile u32*)(INCA_IP_MBC+ 0x0088)) #define INCA_IP_MBC_MBC_MSK_B3DA (1 << 31) #define INCA_IP_MBC_MBC_MSK_B2DA (1 << 30) @@ -274,8 +274,8 @@ #define INCA_IP_MBC_MBC_MSK_B0E (1 << 28) #define INCA_IP_MBC_MBC_MSK_WDT (1 << 27) #define INCA_IP_MBC_MBC_MSK_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) - -/***Mailbox CPU Mask 01 Register***/ + +/***Mailbox CPU Mask 01 Register***/ #define INCA_IP_MBC_MBC_MSK01 ((volatile u32*)(INCA_IP_MBC+ 0x008C)) #define INCA_IP_MBC_MBC_MSK01_B3DA (1 << 31) #define INCA_IP_MBC_MBC_MSK01_B2DA (1 << 30) @@ -283,8 +283,8 @@ #define INCA_IP_MBC_MBC_MSK01_B0E (1 << 28) #define INCA_IP_MBC_MBC_MSK01_WDT (1 << 27) #define INCA_IP_MBC_MBC_MSK01_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) - -/***Mailbox CPU Mask 10 Register***/ + +/***Mailbox CPU Mask 10 Register***/ #define INCA_IP_MBC_MBC_MSK10 ((volatile u32*)(INCA_IP_MBC+ 0x0090)) #define INCA_IP_MBC_MBC_MSK10_B3DA (1 << 31) #define INCA_IP_MBC_MBC_MSK10_B2DA (1 << 30) @@ -292,167 +292,167 @@ #define INCA_IP_MBC_MBC_MSK10_B0E (1 << 28) #define INCA_IP_MBC_MBC_MSK10_WDT (1 << 27) #define INCA_IP_MBC_MBC_MSK10_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) - -/***Mailbox CPU Short Command Register***/ + +/***Mailbox CPU Short Command Register***/ #define INCA_IP_MBC_MBC_CMD ((volatile u32*)(INCA_IP_MBC+ 0x0094)) #define INCA_IP_MBC_MBC_CMD_CS270 (value) (((( 1 << 28) - 1) & (value)) << 0) - -/***Mailbox CPU Input Data of Buffer 0***/ + +/***Mailbox CPU Input Data of Buffer 0***/ #define INCA_IP_MBC_MBC_ID0 ((volatile u32*)(INCA_IP_MBC+ 0x0000)) #define INCA_IP_MBC_MBC_ID0_INDATA - -/***Mailbox CPU Input Data of Buffer 1***/ + +/***Mailbox CPU Input Data of Buffer 1***/ #define INCA_IP_MBC_MBC_ID1 ((volatile u32*)(INCA_IP_MBC+ 0x0020)) #define INCA_IP_MBC_MBC_ID1_INDATA - -/***Mailbox CPU Output Data of Buffer 2***/ + +/***Mailbox CPU Output Data of Buffer 2***/ #define INCA_IP_MBC_MBC_OD2 ((volatile u32*)(INCA_IP_MBC+ 0x0040)) #define INCA_IP_MBC_MBC_OD2_OUTDATA - -/***Mailbox CPU Output Data of Buffer 3***/ + +/***Mailbox CPU Output Data of Buffer 3***/ #define INCA_IP_MBC_MBC_OD3 ((volatile u32*)(INCA_IP_MBC+ 0x0060)) #define INCA_IP_MBC_MBC_OD3_OUTDATA - -/***Mailbox CPU Control Register of Buffer 0***/ + +/***Mailbox CPU Control Register of Buffer 0***/ #define INCA_IP_MBC_MBC_CR0 ((volatile u32*)(INCA_IP_MBC+ 0x0004)) #define INCA_IP_MBC_MBC_CR0_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***Mailbox CPU Control Register of Buffer 1***/ + +/***Mailbox CPU Control Register of Buffer 1***/ #define INCA_IP_MBC_MBC_CR1 ((volatile u32*)(INCA_IP_MBC+ 0x0024)) #define INCA_IP_MBC_MBC_CR1_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***Mailbox CPU Control Register of Buffer 2***/ + +/***Mailbox CPU Control Register of Buffer 2***/ #define INCA_IP_MBC_MBC_CR2 ((volatile u32*)(INCA_IP_MBC+ 0x0044)) #define INCA_IP_MBC_MBC_CR2_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***Mailbox CPU Control Register of Buffer 3***/ + +/***Mailbox CPU Control Register of Buffer 3***/ #define INCA_IP_MBC_MBC_CR3 ((volatile u32*)(INCA_IP_MBC+ 0x0064)) #define INCA_IP_MBC_MBC_CR3_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***Mailbox CPU Free Space of Buffer 0***/ + +/***Mailbox CPU Free Space of Buffer 0***/ #define INCA_IP_MBC_MBC_FS0 ((volatile u32*)(INCA_IP_MBC+ 0x0008)) #define INCA_IP_MBC_MBC_FS0_FS - -/***Mailbox CPU Free Space of Buffer 1***/ + +/***Mailbox CPU Free Space of Buffer 1***/ #define INCA_IP_MBC_MBC_FS1 ((volatile u32*)(INCA_IP_MBC+ 0x0028)) #define INCA_IP_MBC_MBC_FS1_FS - -/***Mailbox CPU Free Space of Buffer 2***/ + +/***Mailbox CPU Free Space of Buffer 2***/ #define INCA_IP_MBC_MBC_FS2 ((volatile u32*)(INCA_IP_MBC+ 0x0048)) #define INCA_IP_MBC_MBC_FS2_FS - -/***Mailbox CPU Free Space of Buffer 3***/ + +/***Mailbox CPU Free Space of Buffer 3***/ #define INCA_IP_MBC_MBC_FS3 ((volatile u32*)(INCA_IP_MBC+ 0x0068)) #define INCA_IP_MBC_MBC_FS3_FS - -/***Mailbox CPU Data Available in Buffer 0***/ + +/***Mailbox CPU Data Available in Buffer 0***/ #define INCA_IP_MBC_MBC_DA0 ((volatile u32*)(INCA_IP_MBC+ 0x000C)) #define INCA_IP_MBC_MBC_DA0_DA - -/***Mailbox CPU Data Available in Buffer 1***/ + +/***Mailbox CPU Data Available in Buffer 1***/ #define INCA_IP_MBC_MBC_DA1 ((volatile u32*)(INCA_IP_MBC+ 0x002C)) #define INCA_IP_MBC_MBC_DA1_DA - -/***Mailbox CPU Data Available in Buffer 2***/ + +/***Mailbox CPU Data Available in Buffer 2***/ #define INCA_IP_MBC_MBC_DA2 ((volatile u32*)(INCA_IP_MBC+ 0x004C)) #define INCA_IP_MBC_MBC_DA2_DA - -/***Mailbox CPU Data Available in Buffer 3***/ + +/***Mailbox CPU Data Available in Buffer 3***/ #define INCA_IP_MBC_MBC_DA3 ((volatile u32*)(INCA_IP_MBC+ 0x006C)) #define INCA_IP_MBC_MBC_DA3_DA - -/***Mailbox CPU Input Absolute Pointer of Buffer 0***/ + +/***Mailbox CPU Input Absolute Pointer of Buffer 0***/ #define INCA_IP_MBC_MBC_IABS0 ((volatile u32*)(INCA_IP_MBC+ 0x0010)) #define INCA_IP_MBC_MBC_IABS0_IABS - -/***Mailbox CPU Input Absolute Pointer of Buffer 1***/ + +/***Mailbox CPU Input Absolute Pointer of Buffer 1***/ #define INCA_IP_MBC_MBC_IABS1 ((volatile u32*)(INCA_IP_MBC+ 0x0030)) #define INCA_IP_MBC_MBC_IABS1_IABS - -/***Mailbox CPU Input Absolute Pointer of Buffer 2***/ + +/***Mailbox CPU Input Absolute Pointer of Buffer 2***/ #define INCA_IP_MBC_MBC_IABS2 ((volatile u32*)(INCA_IP_MBC+ 0x0050)) #define INCA_IP_MBC_MBC_IABS2_IABS - -/***Mailbox CPU Input Absolute Pointer of Buffer 3***/ + +/***Mailbox CPU Input Absolute Pointer of Buffer 3***/ #define INCA_IP_MBC_MBC_IABS3 ((volatile u32*)(INCA_IP_MBC+ 0x0070)) #define INCA_IP_MBC_MBC_IABS3_IABS - -/***Mailbox CPU Input Temporary Pointer of Buffer 0***/ + +/***Mailbox CPU Input Temporary Pointer of Buffer 0***/ #define INCA_IP_MBC_MBC_ITMP0 ((volatile u32*)(INCA_IP_MBC+ 0x0014)) #define INCA_IP_MBC_MBC_ITMP0_ITMP - -/***Mailbox CPU Input Temporary Pointer of Buffer 1***/ + +/***Mailbox CPU Input Temporary Pointer of Buffer 1***/ #define INCA_IP_MBC_MBC_ITMP1 ((volatile u32*)(INCA_IP_MBC+ 0x0034)) #define INCA_IP_MBC_MBC_ITMP1_ITMP - -/***Mailbox CPU Input Temporary Pointer of Buffer 2***/ + +/***Mailbox CPU Input Temporary Pointer of Buffer 2***/ #define INCA_IP_MBC_MBC_ITMP2 ((volatile u32*)(INCA_IP_MBC+ 0x0054)) #define INCA_IP_MBC_MBC_ITMP2_ITMP - -/***Mailbox CPU Input Temporary Pointer of Buffer 3***/ + +/***Mailbox CPU Input Temporary Pointer of Buffer 3***/ #define INCA_IP_MBC_MBC_ITMP3 ((volatile u32*)(INCA_IP_MBC+ 0x0074)) #define INCA_IP_MBC_MBC_ITMP3_ITMP - -/***Mailbox CPU Output Absolute Pointer of Buffer 0***/ + +/***Mailbox CPU Output Absolute Pointer of Buffer 0***/ #define INCA_IP_MBC_MBC_OABS0 ((volatile u32*)(INCA_IP_MBC+ 0x0018)) #define INCA_IP_MBC_MBC_OABS0_OABS - -/***Mailbox CPU Output Absolute Pointer of Buffer 1***/ + +/***Mailbox CPU Output Absolute Pointer of Buffer 1***/ #define INCA_IP_MBC_MBC_OABS1 ((volatile u32*)(INCA_IP_MBC+ 0x0038)) #define INCA_IP_MBC_MBC_OABS1_OABS - -/***Mailbox CPU Output Absolute Pointer of Buffer 2***/ + +/***Mailbox CPU Output Absolute Pointer of Buffer 2***/ #define INCA_IP_MBC_MBC_OABS2 ((volatile u32*)(INCA_IP_MBC+ 0x0058)) #define INCA_IP_MBC_MBC_OABS2_OABS - -/***Mailbox CPU Output Absolute Pointer of Buffer 3***/ + +/***Mailbox CPU Output Absolute Pointer of Buffer 3***/ #define INCA_IP_MBC_MBC_OABS3 ((volatile u32*)(INCA_IP_MBC+ 0x0078)) #define INCA_IP_MBC_MBC_OABS3_OABS - -/***Mailbox CPU Output Temporary Pointer of Buffer 0***/ + +/***Mailbox CPU Output Temporary Pointer of Buffer 0***/ #define INCA_IP_MBC_MBC_OTMP0 ((volatile u32*)(INCA_IP_MBC+ 0x001C)) #define INCA_IP_MBC_MBC_OTMP0_OTMP - -/***Mailbox CPU Output Temporary Pointer of Buffer 1***/ + +/***Mailbox CPU Output Temporary Pointer of Buffer 1***/ #define INCA_IP_MBC_MBC_OTMP1 ((volatile u32*)(INCA_IP_MBC+ 0x003C)) #define INCA_IP_MBC_MBC_OTMP1_OTMP - -/***Mailbox CPU Output Temporary Pointer of Buffer 2***/ + +/***Mailbox CPU Output Temporary Pointer of Buffer 2***/ #define INCA_IP_MBC_MBC_OTMP2 ((volatile u32*)(INCA_IP_MBC+ 0x005C)) #define INCA_IP_MBC_MBC_OTMP2_OTMP - -/***Mailbox CPU Output Temporary Pointer of Buffer 3***/ + +/***Mailbox CPU Output Temporary Pointer of Buffer 3***/ #define INCA_IP_MBC_MBC_OTMP3 ((volatile u32*)(INCA_IP_MBC+ 0x007C)) #define INCA_IP_MBC_MBC_OTMP3_OTMP - -/***DSP Control Register***/ + +/***DSP Control Register***/ #define INCA_IP_MBC_DCTRL ((volatile u32*)(INCA_IP_MBC+ 0x00A0)) #define INCA_IP_MBC_DCTRL_BA (1 << 0) #define INCA_IP_MBC_DCTRL_BMOD (value) (((( 1 << 3) - 1) & (value)) << 1) #define INCA_IP_MBC_DCTRL_IDL (1 << 4) #define INCA_IP_MBC_DCTRL_RES (1 << 15) - -/***DSP Status Register***/ + +/***DSP Status Register***/ #define INCA_IP_MBC_DSTA ((volatile u32*)(INCA_IP_MBC+ 0x00A4)) #define INCA_IP_MBC_DSTA_IDLE (1 << 0) #define INCA_IP_MBC_DSTA_PD (1 << 1) - -/***DSP Test 1 Register***/ + +/***DSP Test 1 Register***/ #define INCA_IP_MBC_DTST1 ((volatile u32*)(INCA_IP_MBC+ 0x00A8)) #define INCA_IP_MBC_DTST1_ABORT (1 << 0) #define INCA_IP_MBC_DTST1_HWF32 (1 << 1) #define INCA_IP_MBC_DTST1_HWF4M (1 << 2) -#define INCA_IP_MBC_DTST1_HWFOP (1 << 3) - +#define INCA_IP_MBC_DTST1_HWFOP (1 << 3) + /***********************************************************************/ /* Module : Switch register address and bits */ /***********************************************************************/ - + #define INCA_IP_Switch (0xBF104000) -/***********************************************************************/ +/***********************************************************************/ + - -/***Unknown Destination Register***/ +/***Unknown Destination Register***/ #define INCA_IP_Switch_UN_DEST ((volatile u32*)(INCA_IP_Switch+ 0x0000)) #define INCA_IP_Switch_UN_DEST_CB (1 << 8) #define INCA_IP_Switch_UN_DEST_LB (1 << 7) @@ -463,8 +463,8 @@ #define INCA_IP_Switch_UN_DEST_CU (1 << 2) #define INCA_IP_Switch_UN_DEST_LU (1 << 1) #define INCA_IP_Switch_UN_DEST_PU (1 << 0) - -/***VLAN Control Register***/ + +/***VLAN Control Register***/ #define INCA_IP_Switch_VLAN_CTRL ((volatile u32*)(INCA_IP_Switch+ 0x0004)) #define INCA_IP_Switch_VLAN_CTRL_SC (1 << 6) #define INCA_IP_Switch_VLAN_CTRL_SL (1 << 5) @@ -473,23 +473,23 @@ #define INCA_IP_Switch_VLAN_CTRL_TL (1 << 2) #define INCA_IP_Switch_VLAN_CTRL_TP (1 << 1) #define INCA_IP_Switch_VLAN_CTRL_VA (1 << 0) - -/***PC VLAN Configuration Register***/ + +/***PC VLAN Configuration Register***/ #define INCA_IP_Switch_PC_VLAN ((volatile u32*)(INCA_IP_Switch+ 0x0008)) #define INCA_IP_Switch_PC_VLAN_PRI (value) (((( 1 << 3) - 1) & (value)) << 12) #define INCA_IP_Switch_PC_VLAN_VLAN_ID (value) (((( 1 << 12) - 1) & (value)) << 0) - -/***LAN VLAN Configuration Register***/ + +/***LAN VLAN Configuration Register***/ #define INCA_IP_Switch_LAN_VLAN ((volatile u32*)(INCA_IP_Switch+ 0x000C)) #define INCA_IP_Switch_LAN_VLAN_PRI (value) (((( 1 << 3) - 1) & (value)) << 12) #define INCA_IP_Switch_LAN_VLAN_VLAN_ID (value) (((( 1 << 12) - 1) & (value)) << 0) - -/***CPU VLAN Configuration Register***/ + +/***CPU VLAN Configuration Register***/ #define INCA_IP_Switch_CPU_VLAN ((volatile u32*)(INCA_IP_Switch+ 0x0010)) #define INCA_IP_Switch_CPU_VLAN_PRI (value) (((( 1 << 3) - 1) & (value)) << 12) #define INCA_IP_Switch_CPU_VLAN_VLAN_ID (value) (((( 1 << 12) - 1) & (value)) << 0) - -/***Priority CoS Mapping Register***/ + +/***Priority CoS Mapping Register***/ #define INCA_IP_Switch_PRI_CoS ((volatile u32*)(INCA_IP_Switch+ 0x0014)) #define INCA_IP_Switch_PRI_CoS_P7 (1 << 7) #define INCA_IP_Switch_PRI_CoS_P6 (1 << 6) @@ -499,14 +499,14 @@ #define INCA_IP_Switch_PRI_CoS_P2 (1 << 2) #define INCA_IP_Switch_PRI_CoS_P1 (1 << 1) #define INCA_IP_Switch_PRI_CoS_P0 (1 << 0) - -/***Spanning Tree Port Status Register***/ + +/***Spanning Tree Port Status Register***/ #define INCA_IP_Switch_ST_PT ((volatile u32*)(INCA_IP_Switch+ 0x0018)) #define INCA_IP_Switch_ST_PT_CPS (value) (((( 1 << 2) - 1) & (value)) << 4) #define INCA_IP_Switch_ST_PT_LPS (value) (((( 1 << 2) - 1) & (value)) << 2) #define INCA_IP_Switch_ST_PT_PPS (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***ARL Control Register***/ + +/***ARL Control Register***/ #define INCA_IP_Switch_ARL_CTL ((volatile u32*)(INCA_IP_Switch+ 0x001C)) #define INCA_IP_Switch_ARL_CTL_CHCC (1 << 15) #define INCA_IP_Switch_ARL_CTL_CHCL (1 << 14) @@ -523,24 +523,24 @@ #define INCA_IP_Switch_ARL_CTL_MAF (1 << 1) #define INCA_IP_Switch_ARL_CTL_ENL (1 << 0) #define INCA_IP_Switch_ARL_CTL_Res (value) (((( 1 << 19) - 1) & (value)) << 13) - -/***CPU Access Control Register***/ + +/***CPU Access Control Register***/ #define INCA_IP_Switch_CPU_ACTL ((volatile u32*)(INCA_IP_Switch+ 0x0020)) #define INCA_IP_Switch_CPU_ACTL_RA (1 << 31) #define INCA_IP_Switch_CPU_ACTL_RW (1 << 30) #define INCA_IP_Switch_CPU_ACTL_Res (value) (((( 1 << 21) - 1) & (value)) << 9) #define INCA_IP_Switch_CPU_ACTL_AVA (1 << 8) #define INCA_IP_Switch_CPU_ACTL_IDX (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***CPU Access Data Register 1***/ + +/***CPU Access Data Register 1***/ #define INCA_IP_Switch_DATA1 ((volatile u32*)(INCA_IP_Switch+ 0x0024)) #define INCA_IP_Switch_DATA1_Data (value) (((( 1 << 24) - 1) & (value)) << 0) - -/***CPU Access Data Register 2***/ + +/***CPU Access Data Register 2***/ #define INCA_IP_Switch_DATA2 ((volatile u32*)(INCA_IP_Switch+ 0x0028)) #define INCA_IP_Switch_DATA2_Data - -/***CPU Port Control Register***/ + +/***CPU Port Control Register***/ #define INCA_IP_Switch_CPU_PCTL ((volatile u32*)(INCA_IP_Switch+ 0x002C)) #define INCA_IP_Switch_CPU_PCTL_DA_PORTS (value) (((( 1 << 3) - 1) & (value)) << 11) #define INCA_IP_Switch_CPU_PCTL_DAC (1 << 10) @@ -551,85 +551,85 @@ #define INCA_IP_Switch_CPU_PCTL_EML (1 << 1) #define INCA_IP_Switch_CPU_PCTL_EDL (1 << 0) #define INCA_IP_Switch_CPU_PCTL_Res (value) (((( 1 << 18) - 1) & (value)) << 14) - -/***DSCP CoS Mapping Register 1***/ + +/***DSCP CoS Mapping Register 1***/ #define INCA_IP_Switch_DSCP_COS1 ((volatile u32*)(INCA_IP_Switch+ 0x0030)) #define INCA_IP_Switch_DSCP_COS1_DSCP - -/***DSCP CoS Mapping Register 1***/ + +/***DSCP CoS Mapping Register 1***/ #define INCA_IP_Switch_DSCP_COS2 ((volatile u32*)(INCA_IP_Switch+ 0x0034)) #define INCA_IP_Switch_DSCP_COS2_DSCP - -/***PC WFQ Control Register***/ + +/***PC WFQ Control Register***/ #define INCA_IP_Switch_PC_WFQ_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0080)) #define INCA_IP_Switch_PC_WFQ_CTL_P1 (1 << 9) #define INCA_IP_Switch_PC_WFQ_CTL_P0 (1 << 8) #define INCA_IP_Switch_PC_WFQ_CTL_WT1 (value) (((( 1 << 3) - 1) & (value)) << 5) #define INCA_IP_Switch_PC_WFQ_CTL_WT0 (value) (((( 1 << 3) - 1) & (value)) << 2) #define INCA_IP_Switch_PC_WFQ_CTL_SCH_SEL (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***PC TX Control Register***/ + +/***PC TX Control Register***/ #define INCA_IP_Switch_PC_TX_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0084)) #define INCA_IP_Switch_PC_TX_CTL_ELR (1 << 1) #define INCA_IP_Switch_PC_TX_CTL_EER (1 << 0) - -/***LAN WFQ Control Register***/ + +/***LAN WFQ Control Register***/ #define INCA_IP_Switch_LAN_WFQ_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0100)) #define INCA_IP_Switch_LAN_WFQ_CTL_P1 (1 << 9) #define INCA_IP_Switch_LAN_WFQ_CTL_P0 (1 << 8) #define INCA_IP_Switch_LAN_WFQ_CTL_WT1 (value) (((( 1 << 3) - 1) & (value)) << 5) #define INCA_IP_Switch_LAN_WFQ_CTL_WT0 (value) (((( 1 << 3) - 1) & (value)) << 2) #define INCA_IP_Switch_LAN_WFQ_CTL_SCH_SEL (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***LAN TX Control Register***/ + +/***LAN TX Control Register***/ #define INCA_IP_Switch_LAN_TX_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0104)) #define INCA_IP_Switch_LAN_TX_CTL_ELR (1 << 1) #define INCA_IP_Switch_LAN_TX_CTL_EER (1 << 0) - -/***CPU WFQ Control Register***/ + +/***CPU WFQ Control Register***/ #define INCA_IP_Switch_CPU_WFQ_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0180)) #define INCA_IP_Switch_CPU_WFQ_CTL_P1 (1 << 9) #define INCA_IP_Switch_CPU_WFQ_CTL_P0 (1 << 8) #define INCA_IP_Switch_CPU_WFQ_CTL_WT1 (value) (((( 1 << 3) - 1) & (value)) << 5) #define INCA_IP_Switch_CPU_WFQ_CTL_WT0 (value) (((( 1 << 3) - 1) & (value)) << 2) #define INCA_IP_Switch_CPU_WFQ_CTL_SCH_SEL (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***PM PC RX Watermark Register***/ + +/***PM PC RX Watermark Register***/ #define INCA_IP_Switch_PC_WM ((volatile u32*)(INCA_IP_Switch+ 0x0200)) #define INCA_IP_Switch_PC_WM_RX_WM1 (value) (((( 1 << 8) - 1) & (value)) << 24) #define INCA_IP_Switch_PC_WM_RX_WM2 (value) (((( 1 << 8) - 1) & (value)) << 16) #define INCA_IP_Switch_PC_WM_RX_WM3 (value) (((( 1 << 8) - 1) & (value)) << 8) #define INCA_IP_Switch_PC_WM_RX_WM4 (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***PM LAN RX Watermark Register***/ + +/***PM LAN RX Watermark Register***/ #define INCA_IP_Switch_LAN_WM ((volatile u32*)(INCA_IP_Switch+ 0x0204)) #define INCA_IP_Switch_LAN_WM_RX_WM1 (value) (((( 1 << 8) - 1) & (value)) << 24) #define INCA_IP_Switch_LAN_WM_RX_WM2 (value) (((( 1 << 8) - 1) & (value)) << 16) #define INCA_IP_Switch_LAN_WM_RX_WM3 (value) (((( 1 << 8) - 1) & (value)) << 8) #define INCA_IP_Switch_LAN_WM_RX_WM4 (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***PM CPU RX Watermark Register***/ + +/***PM CPU RX Watermark Register***/ #define INCA_IP_Switch_CPU_WM ((volatile u32*)(INCA_IP_Switch+ 0x0208)) #define INCA_IP_Switch_CPU_WM_RX_WM1 (value) (((( 1 << 8) - 1) & (value)) << 24) #define INCA_IP_Switch_CPU_WM_RX_WM2 (value) (((( 1 << 8) - 1) & (value)) << 16) #define INCA_IP_Switch_CPU_WM_RX_WM3 (value) (((( 1 << 8) - 1) & (value)) << 8) #define INCA_IP_Switch_CPU_WM_RX_WM4 (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***PM CPU RX Watermark Register***/ + +/***PM CPU RX Watermark Register***/ #define INCA_IP_Switch_GBL_WM ((volatile u32*)(INCA_IP_Switch+ 0x020C)) #define INCA_IP_Switch_GBL_WM_GBL_RX_WM1 (value) (((( 1 << 8) - 1) & (value)) << 24) #define INCA_IP_Switch_GBL_WM_GBL_RX_WM2 (value) (((( 1 << 8) - 1) & (value)) << 16) #define INCA_IP_Switch_GBL_WM_GBL_RX_WM3 (value) (((( 1 << 8) - 1) & (value)) << 8) #define INCA_IP_Switch_GBL_WM_GBL_RX_WM4 (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***PM Control Register***/ + +/***PM Control Register***/ #define INCA_IP_Switch_PM_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0210)) #define INCA_IP_Switch_PM_CTL_GDN (1 << 3) #define INCA_IP_Switch_PM_CTL_CDN (1 << 2) #define INCA_IP_Switch_PM_CTL_LDN (1 << 1) #define INCA_IP_Switch_PM_CTL_PDN (1 << 0) - -/***PM Header Control Register***/ + +/***PM Header Control Register***/ #define INCA_IP_Switch_PMAC_HD_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0280)) #define INCA_IP_Switch_PMAC_HD_CTL_RL2 (1 << 21) #define INCA_IP_Switch_PMAC_HD_CTL_RC (1 << 20) @@ -638,38 +638,38 @@ #define INCA_IP_Switch_PMAC_HD_CTL_TYPE_LEN (value) (((( 1 << 16) - 1) & (value)) << 2) #define INCA_IP_Switch_PMAC_HD_CTL_TAG (1 << 1) #define INCA_IP_Switch_PMAC_HD_CTL_ADD (1 << 0) - -/***PM Source Address Register 1***/ + +/***PM Source Address Register 1***/ #define INCA_IP_Switch_PMAC_SA1 ((volatile u32*)(INCA_IP_Switch+ 0x0284)) #define INCA_IP_Switch_PMAC_SA1_SA_47_32 (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***PM Source Address Register 2***/ + +/***PM Source Address Register 2***/ #define INCA_IP_Switch_PMAC_SA2 ((volatile u32*)(INCA_IP_Switch+ 0x0288)) #define INCA_IP_Switch_PMAC_SA2_SA_31_0 - -/***PM Dest Address Register 1***/ + +/***PM Dest Address Register 1***/ #define INCA_IP_Switch_PMAC_DA1 ((volatile u32*)(INCA_IP_Switch+ 0x028C)) #define INCA_IP_Switch_PMAC_DA1_DA_47_32 (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***PM Dest Address Register 2***/ + +/***PM Dest Address Register 2***/ #define INCA_IP_Switch_PMAC_DA2 ((volatile u32*)(INCA_IP_Switch+ 0x0290)) #define INCA_IP_Switch_PMAC_DA2_DA_31_0 - -/***PM VLAN Register***/ + +/***PM VLAN Register***/ #define INCA_IP_Switch_PMAC_VLAN ((volatile u32*)(INCA_IP_Switch+ 0x0294)) #define INCA_IP_Switch_PMAC_VLAN_PRI (value) (((( 1 << 3) - 1) & (value)) << 13) #define INCA_IP_Switch_PMAC_VLAN_CFI (1 << 12) #define INCA_IP_Switch_PMAC_VLAN_VLANID (value) (((( 1 << 12) - 1) & (value)) << 0) - -/***PM TX IPG Counter Register***/ + +/***PM TX IPG Counter Register***/ #define INCA_IP_Switch_PMAC_TX_IPG ((volatile u32*)(INCA_IP_Switch+ 0x0298)) #define INCA_IP_Switch_PMAC_TX_IPG_IPGCNT (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***PM RX IPG Counter Register***/ + +/***PM RX IPG Counter Register***/ #define INCA_IP_Switch_PMAC_RX_IPG ((volatile u32*)(INCA_IP_Switch+ 0x029C)) #define INCA_IP_Switch_PMAC_RX_IPG_IPGCNT (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Mirror Register***/ + +/***Mirror Register***/ #define INCA_IP_Switch_MRR ((volatile u32*)(INCA_IP_Switch+ 0x0300)) #define INCA_IP_Switch_MRR_MRR (value) (((( 1 << 2) - 1) & (value)) << 6) #define INCA_IP_Switch_MRR_EC (1 << 5) @@ -678,21 +678,21 @@ #define INCA_IP_Switch_MRR_IC (1 << 2) #define INCA_IP_Switch_MRR_IL (1 << 1) #define INCA_IP_Switch_MRR_IP (1 << 0) - -/***Packet Length Register***/ + +/***Packet Length Register***/ #define INCA_IP_Switch_PKT_LEN ((volatile u32*)(INCA_IP_Switch+ 0x0304)) #define INCA_IP_Switch_PKT_LEN_ADD (1 << 11) #define INCA_IP_Switch_PKT_LEN_MAX_PKT_LEN (value) (((( 1 << 11) - 1) & (value)) << 0) - -/***MDIO Access Register***/ + +/***MDIO Access Register***/ #define INCA_IP_Switch_MDIO_ACC ((volatile u32*)(INCA_IP_Switch+ 0x0480)) #define INCA_IP_Switch_MDIO_ACC_RA (1 << 31) #define INCA_IP_Switch_MDIO_ACC_RW (1 << 30) #define INCA_IP_Switch_MDIO_ACC_PHY_ADDR (value) (((( 1 << 5) - 1) & (value)) << 21) #define INCA_IP_Switch_MDIO_ACC_REG_ADDR (value) (((( 1 << 5) - 1) & (value)) << 16) #define INCA_IP_Switch_MDIO_ACC_PHY_DATA (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***Ethernet PHY Register***/ + +/***Ethernet PHY Register***/ #define INCA_IP_Switch_EPHY ((volatile u32*)(INCA_IP_Switch+ 0x0484)) #define INCA_IP_Switch_EPHY_SL (1 << 7) #define INCA_IP_Switch_EPHY_SP (1 << 6) @@ -702,13 +702,13 @@ #define INCA_IP_Switch_EPHY_DP (1 << 2) #define INCA_IP_Switch_EPHY_PL (1 << 1) #define INCA_IP_Switch_EPHY_PP (1 << 0) - -/***Pause Write Enable Register***/ + +/***Pause Write Enable Register***/ #define INCA_IP_Switch_PWR_EN ((volatile u32*)(INCA_IP_Switch+ 0x0488)) #define INCA_IP_Switch_PWR_EN_PL (1 << 1) #define INCA_IP_Switch_PWR_EN_PP (1 << 0) - -/***MDIO Configuration Register***/ + +/***MDIO Configuration Register***/ #define INCA_IP_Switch_MDIO_CFG ((volatile u32*)(INCA_IP_Switch+ 0x048C)) #define INCA_IP_Switch_MDIO_CFG_MDS (value) (((( 1 << 2) - 1) & (value)) << 14) #define INCA_IP_Switch_MDIO_CFG_PHY_LAN_ADDR (value) (((( 1 << 5) - 1) & (value)) << 9) @@ -717,24 +717,24 @@ #define INCA_IP_Switch_MDIO_CFG_PS (1 << 2) #define INCA_IP_Switch_MDIO_CFG_PT (1 << 1) #define INCA_IP_Switch_MDIO_CFG_UMM (1 << 0) - -/***Clock Configuration Register***/ + +/***Clock Configuration Register***/ #define INCA_IP_Switch_CLK_CFG ((volatile u32*)(INCA_IP_Switch+ 0x0500)) #define INCA_IP_Switch_CLK_CFG_ARL_ID (1 << 9) #define INCA_IP_Switch_CLK_CFG_CPU_ID (1 << 8) #define INCA_IP_Switch_CLK_CFG_LAN_ID (1 << 7) #define INCA_IP_Switch_CLK_CFG_PC_ID (1 << 6) -#define INCA_IP_Switch_CLK_CFG_SE_ID (1 << 5) - +#define INCA_IP_Switch_CLK_CFG_SE_ID (1 << 5) + /***********************************************************************/ /* Module : SSC1 register address and bits */ /***********************************************************************/ - + #define INCA_IP_SSC1 (0xB8000500) -/***********************************************************************/ +/***********************************************************************/ - -/***Control Register (Programming Mode)***/ + +/***Control Register (Programming Mode)***/ #define INCA_IP_SSC1_SCC_CON_PRG ((volatile u32*)(INCA_IP_SSC1+ 0x0010)) #define INCA_IP_SSC1_SCC_CON_PRG_EN (1 << 15) #define INCA_IP_SSC1_SCC_CON_PRG_MS (1 << 14) @@ -748,8 +748,8 @@ #define INCA_IP_SSC1_SCC_CON_PRG_PH (1 << 5) #define INCA_IP_SSC1_SCC_CON_PRG_HB (1 << 4) #define INCA_IP_SSC1_SCC_CON_PRG_BM (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***SCC Control Register (Operating Mode)***/ + +/***SCC Control Register (Operating Mode)***/ #define INCA_IP_SSC1_SCC_CON_OPR ((volatile u32*)(INCA_IP_SSC1+ 0x0010)) #define INCA_IP_SSC1_SCC_CON_OPR_EN (1 << 15) #define INCA_IP_SSC1_SCC_CON_OPR_MS (1 << 14) @@ -759,8 +759,8 @@ #define INCA_IP_SSC1_SCC_CON_OPR_RE (1 << 9) #define INCA_IP_SSC1_SCC_CON_OPR_TE (1 << 8) #define INCA_IP_SSC1_SCC_CON_OPR_BC (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***SSC Write Hardware Modified Control Register***/ + +/***SSC Write Hardware Modified Control Register***/ #define INCA_IP_SSC1_SSC_WHBCON ((volatile u32*)(INCA_IP_SSC1+ 0x0040)) #define INCA_IP_SSC1_SSC_WHBCON_SETBE (1 << 15) #define INCA_IP_SSC1_SSC_WHBCON_SETPE (1 << 14) @@ -770,53 +770,53 @@ #define INCA_IP_SSC1_SSC_WHBCON_CLRPE (1 << 10) #define INCA_IP_SSC1_SSC_WHBCON_CLRRE (1 << 9) #define INCA_IP_SSC1_SSC_WHBCON_CLRTE (1 << 8) - -/***SSC Baudrate Timer Reload Register***/ + +/***SSC Baudrate Timer Reload Register***/ #define INCA_IP_SSC1_SSC_BR ((volatile u32*)(INCA_IP_SSC1+ 0x0014)) #define INCA_IP_SSC1_SSC_BR_BR_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***SSC Transmitter Buffer Register***/ + +/***SSC Transmitter Buffer Register***/ #define INCA_IP_SSC1_SSC_TB ((volatile u32*)(INCA_IP_SSC1+ 0x0020)) #define INCA_IP_SSC1_SSC_TB_TB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***SSC Receiver Buffer Register***/ + +/***SSC Receiver Buffer Register***/ #define INCA_IP_SSC1_SSC_RB ((volatile u32*)(INCA_IP_SSC1+ 0x0024)) #define INCA_IP_SSC1_SSC_RB_RB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***SSC Receive FIFO Control Register***/ + +/***SSC Receive FIFO Control Register***/ #define INCA_IP_SSC1_SSC_RXFCON ((volatile u32*)(INCA_IP_SSC1+ 0x0030)) #define INCA_IP_SSC1_SSC_RXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) #define INCA_IP_SSC1_SSC_RXFCON_RXTMEN (1 << 2) #define INCA_IP_SSC1_SSC_RXFCON_RXFLU (1 << 1) #define INCA_IP_SSC1_SSC_RXFCON_RXFEN (1 << 0) - -/***SSC Transmit FIFO Control Register***/ + +/***SSC Transmit FIFO Control Register***/ #define INCA_IP_SSC1_SSC_TXFCON ((volatile u32*)(INCA_IP_SSC1+ 0x0034)) #define INCA_IP_SSC1_SSC_TXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) #define INCA_IP_SSC1_SSC_TXFCON_TXTMEN (1 << 2) #define INCA_IP_SSC1_SSC_TXFCON_TXFLU (1 << 1) #define INCA_IP_SSC1_SSC_TXFCON_TXFEN (1 << 0) - -/***SSC FIFO Status Register***/ + +/***SSC FIFO Status Register***/ #define INCA_IP_SSC1_SSC_FSTAT ((volatile u32*)(INCA_IP_SSC1+ 0x0038)) #define INCA_IP_SSC1_SSC_FSTAT_TXFFL (value) (((( 1 << 6) - 1) & (value)) << 8) #define INCA_IP_SSC1_SSC_FSTAT_RXFFL (value) (((( 1 << 6) - 1) & (value)) << 0) - -/***SSC Clock Control Register***/ + +/***SSC Clock Control Register***/ #define INCA_IP_SSC1_SSC_CLC ((volatile u32*)(INCA_IP_SSC1+ 0x0000)) #define INCA_IP_SSC1_SSC_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) #define INCA_IP_SSC1_SSC_CLC_DISS (1 << 1) -#define INCA_IP_SSC1_SSC_CLC_DISR (1 << 0) - +#define INCA_IP_SSC1_SSC_CLC_DISR (1 << 0) + /***********************************************************************/ /* Module : SSC2 register address and bits */ /***********************************************************************/ - + #define INCA_IP_SSC2 (0xB8000600) -/***********************************************************************/ +/***********************************************************************/ - -/***Control Register (Programming Mode)***/ + +/***Control Register (Programming Mode)***/ #define INCA_IP_SSC2_SCC_CON_PRG ((volatile u32*)(INCA_IP_SSC2+ 0x0010)) #define INCA_IP_SSC2_SCC_CON_PRG_EN (1 << 15) #define INCA_IP_SSC2_SCC_CON_PRG_MS (1 << 14) @@ -830,8 +830,8 @@ #define INCA_IP_SSC2_SCC_CON_PRG_PH (1 << 5) #define INCA_IP_SSC2_SCC_CON_PRG_HB (1 << 4) #define INCA_IP_SSC2_SCC_CON_PRG_BM (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***SCC Control Register (Operating Mode)***/ + +/***SCC Control Register (Operating Mode)***/ #define INCA_IP_SSC2_SCC_CON_OPR ((volatile u32*)(INCA_IP_SSC2+ 0x0010)) #define INCA_IP_SSC2_SCC_CON_OPR_EN (1 << 15) #define INCA_IP_SSC2_SCC_CON_OPR_MS (1 << 14) @@ -841,8 +841,8 @@ #define INCA_IP_SSC2_SCC_CON_OPR_RE (1 << 9) #define INCA_IP_SSC2_SCC_CON_OPR_TE (1 << 8) #define INCA_IP_SSC2_SCC_CON_OPR_BC (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***SSC Write Hardware Modified Control Register***/ + +/***SSC Write Hardware Modified Control Register***/ #define INCA_IP_SSC2_SSC_WHBCON ((volatile u32*)(INCA_IP_SSC2+ 0x0040)) #define INCA_IP_SSC2_SSC_WHBCON_SETBE (1 << 15) #define INCA_IP_SSC2_SSC_WHBCON_SETPE (1 << 14) @@ -852,63 +852,63 @@ #define INCA_IP_SSC2_SSC_WHBCON_CLRPE (1 << 10) #define INCA_IP_SSC2_SSC_WHBCON_CLRRE (1 << 9) #define INCA_IP_SSC2_SSC_WHBCON_CLRTE (1 << 8) - -/***SSC Baudrate Timer Reload Register***/ + +/***SSC Baudrate Timer Reload Register***/ #define INCA_IP_SSC2_SSC_BR ((volatile u32*)(INCA_IP_SSC2+ 0x0014)) #define INCA_IP_SSC2_SSC_BR_BR_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***SSC Transmitter Buffer Register***/ + +/***SSC Transmitter Buffer Register***/ #define INCA_IP_SSC2_SSC_TB ((volatile u32*)(INCA_IP_SSC2+ 0x0020)) #define INCA_IP_SSC2_SSC_TB_TB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***SSC Receiver Buffer Register***/ + +/***SSC Receiver Buffer Register***/ #define INCA_IP_SSC2_SSC_RB ((volatile u32*)(INCA_IP_SSC2+ 0x0024)) #define INCA_IP_SSC2_SSC_RB_RB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***SSC Receive FIFO Control Register***/ + +/***SSC Receive FIFO Control Register***/ #define INCA_IP_SSC2_SSC_RXFCON ((volatile u32*)(INCA_IP_SSC2+ 0x0030)) #define INCA_IP_SSC2_SSC_RXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) #define INCA_IP_SSC2_SSC_RXFCON_RXTMEN (1 << 2) #define INCA_IP_SSC2_SSC_RXFCON_RXFLU (1 << 1) #define INCA_IP_SSC2_SSC_RXFCON_RXFEN (1 << 0) - -/***SSC Transmit FIFO Control Register***/ + +/***SSC Transmit FIFO Control Register***/ #define INCA_IP_SSC2_SSC_TXFCON ((volatile u32*)(INCA_IP_SSC2+ 0x0034)) #define INCA_IP_SSC2_SSC_TXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) #define INCA_IP_SSC2_SSC_TXFCON_TXTMEN (1 << 2) #define INCA_IP_SSC2_SSC_TXFCON_TXFLU (1 << 1) #define INCA_IP_SSC2_SSC_TXFCON_TXFEN (1 << 0) - -/***SSC FIFO Status Register***/ + +/***SSC FIFO Status Register***/ #define INCA_IP_SSC2_SSC_FSTAT ((volatile u32*)(INCA_IP_SSC2+ 0x0038)) #define INCA_IP_SSC2_SSC_FSTAT_TXFFL (value) (((( 1 << 6) - 1) & (value)) << 8) #define INCA_IP_SSC2_SSC_FSTAT_RXFFL (value) (((( 1 << 6) - 1) & (value)) << 0) - -/***SSC Clock Control Register***/ + +/***SSC Clock Control Register***/ #define INCA_IP_SSC2_SSC_CLC ((volatile u32*)(INCA_IP_SSC2+ 0x0000)) #define INCA_IP_SSC2_SSC_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) #define INCA_IP_SSC2_SSC_CLC_DISS (1 << 1) -#define INCA_IP_SSC2_SSC_CLC_DISR (1 << 0) - +#define INCA_IP_SSC2_SSC_CLC_DISR (1 << 0) + /***********************************************************************/ /* Module : EBU register address and bits */ /***********************************************************************/ - + #if defined(CONFIG_INCA_IP) #define INCA_IP_EBU (0xB8000200) #elif defined(CONFIG_PURPLE) #define INCA_IP_EBU (0xB800D800) #endif -/***********************************************************************/ +/***********************************************************************/ + - -/***EBU Clock Control Register***/ +/***EBU Clock Control Register***/ #define INCA_IP_EBU_EBU_CLC ((volatile u32*)(INCA_IP_EBU+ 0x0000)) #define INCA_IP_EBU_EBU_CLC_DISS (1 << 1) #define INCA_IP_EBU_EBU_CLC_DISR (1 << 0) - -/***EBU Global Control Register***/ + +/***EBU Global Control Register***/ #define INCA_IP_EBU_EBU_CON ((volatile u32*)(INCA_IP_EBU+ 0x0010)) #define INCA_IP_EBU_EBU_CON_DTACS (value) (((( 1 << 3) - 1) & (value)) << 20) #define INCA_IP_EBU_EBU_CON_DTARW (value) (((( 1 << 3) - 1) & (value)) << 16) @@ -916,29 +916,29 @@ #define INCA_IP_EBU_EBU_CON_ARBMODE (value) (((( 1 << 2) - 1) & (value)) << 6) #define INCA_IP_EBU_EBU_CON_ARBSYNC (1 << 5) #define INCA_IP_EBU_EBU_CON_1 (1 << 3) - -/***EBU Address Select Register 0***/ + +/***EBU Address Select Register 0***/ #define INCA_IP_EBU_EBU_ADDSEL0 ((volatile u32*)(INCA_IP_EBU+ 0x0020)) #define INCA_IP_EBU_EBU_ADDSEL0_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) #define INCA_IP_EBU_EBU_ADDSEL0_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) #define INCA_IP_EBU_EBU_ADDSEL0_MIRRORE (1 << 1) #define INCA_IP_EBU_EBU_ADDSEL0_REGEN (1 << 0) - -/***EBU Address Select Register 1***/ + +/***EBU Address Select Register 1***/ #define INCA_IP_EBU_EBU_ADDSEL1 ((volatile u32*)(INCA_IP_EBU+ 0x0024)) #define INCA_IP_EBU_EBU_ADDSEL1_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) #define INCA_IP_EBU_EBU_ADDSEL1_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) #define INCA_IP_EBU_EBU_ADDSEL1_MIRRORE (1 << 1) #define INCA_IP_EBU_EBU_ADDSEL1_REGEN (1 << 0) - -/***EBU Address Select Register 2***/ + +/***EBU Address Select Register 2***/ #define INCA_IP_EBU_EBU_ADDSEL2 ((volatile u32*)(INCA_IP_EBU+ 0x0028)) #define INCA_IP_EBU_EBU_ADDSEL2_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) #define INCA_IP_EBU_EBU_ADDSEL2_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) #define INCA_IP_EBU_EBU_ADDSEL2_MIRRORE (1 << 1) #define INCA_IP_EBU_EBU_ADDSEL2_REGEN (1 << 0) - -/***EBU Bus Configuration Register 0***/ + +/***EBU Bus Configuration Register 0***/ #define INCA_IP_EBU_EBU_BUSCON0 ((volatile u32*)(INCA_IP_EBU+ 0x0060)) #define INCA_IP_EBU_EBU_BUSCON0_WRDIS (1 << 31) #define INCA_IP_EBU_EBU_BUSCON0_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29) @@ -954,8 +954,8 @@ #define INCA_IP_EBU_EBU_BUSCON0_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) #define INCA_IP_EBU_EBU_BUSCON0_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) #define INCA_IP_EBU_EBU_BUSCON0_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***EBU Bus Configuration Register 1***/ + +/***EBU Bus Configuration Register 1***/ #define INCA_IP_EBU_EBU_BUSCON1 ((volatile u32*)(INCA_IP_EBU+ 0x0064)) #define INCA_IP_EBU_EBU_BUSCON1_WRDIS (1 << 31) #define INCA_IP_EBU_EBU_BUSCON1_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29) @@ -971,8 +971,8 @@ #define INCA_IP_EBU_EBU_BUSCON1_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) #define INCA_IP_EBU_EBU_BUSCON1_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) #define INCA_IP_EBU_EBU_BUSCON1_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***EBU Bus Configuration Register 2***/ + +/***EBU Bus Configuration Register 2***/ #define INCA_IP_EBU_EBU_BUSCON2 ((volatile u32*)(INCA_IP_EBU+ 0x0068)) #define INCA_IP_EBU_EBU_BUSCON2_WRDIS (1 << 31) #define INCA_IP_EBU_EBU_BUSCON2_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29) @@ -987,28 +987,28 @@ #define INCA_IP_EBU_EBU_BUSCON2_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6) #define INCA_IP_EBU_EBU_BUSCON2_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) #define INCA_IP_EBU_EBU_BUSCON2_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) -#define INCA_IP_EBU_EBU_BUSCON2_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) - +#define INCA_IP_EBU_EBU_BUSCON2_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) + /***********************************************************************/ /* Module : SDRAM register address and bits */ /***********************************************************************/ - + #define INCA_IP_SDRAM (0xBF800000) -/***********************************************************************/ +/***********************************************************************/ + - -/***MC Access Error Cause Register***/ +/***MC Access Error Cause Register***/ #define INCA_IP_SDRAM_MC_ERRCAUSE ((volatile u32*)(INCA_IP_SDRAM+ 0x0100)) #define INCA_IP_SDRAM_MC_ERRCAUSE_ERR (1 << 31) #define INCA_IP_SDRAM_MC_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16) #define INCA_IP_SDRAM_MC_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0) #define INCA_IP_SDRAM_MC_ERRCAUSE_Res (value) (((( 1 << NaN) - 1) & (value)) << NaN) - -/***MC Access Error Address Register***/ + +/***MC Access Error Address Register***/ #define INCA_IP_SDRAM_MC_ERRADDR ((volatile u32*)(INCA_IP_SDRAM+ 0x0108)) #define INCA_IP_SDRAM_MC_ERRADDR_ADDR - -/***MC I/O General Purpose Register***/ + +/***MC I/O General Purpose Register***/ #define INCA_IP_SDRAM_MC_IOGP ((volatile u32*)(INCA_IP_SDRAM+ 0x0800)) #define INCA_IP_SDRAM_MC_IOGP_GPR6 (value) (((( 1 << 4) - 1) & (value)) << 28) #define INCA_IP_SDRAM_MC_IOGP_GPR5 (value) (((( 1 << 4) - 1) & (value)) << 24) @@ -1019,39 +1019,39 @@ #define INCA_IP_SDRAM_MC_IOGP_CLKDELAY (value) (((( 1 << 3) - 1) & (value)) << 8) #define INCA_IP_SDRAM_MC_IOGP_CLKRAT (value) (((( 1 << 4) - 1) & (value)) << 4) #define INCA_IP_SDRAM_MC_IOGP_RDDEL (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***MC Self Refresh Register***/ + +/***MC Self Refresh Register***/ #define INCA_IP_SDRAM_MC_SELFRFSH ((volatile u32*)(INCA_IP_SDRAM+ 0x0A00)) #define INCA_IP_SDRAM_MC_SELFRFSH_PWDS (1 << 1) #define INCA_IP_SDRAM_MC_SELFRFSH_PWD (1 << 0) #define INCA_IP_SDRAM_MC_SELFRFSH_Res (value) (((( 1 << 30) - 1) & (value)) << 2) - -/***MC Enable Register***/ + +/***MC Enable Register***/ #define INCA_IP_SDRAM_MC_CTRLENA ((volatile u32*)(INCA_IP_SDRAM+ 0x1000)) #define INCA_IP_SDRAM_MC_CTRLENA_ENA (1 << 0) #define INCA_IP_SDRAM_MC_CTRLENA_Res (value) (((( 1 << 31) - 1) & (value)) << 1) - -/***MC Mode Register Setup Code***/ + +/***MC Mode Register Setup Code***/ #define INCA_IP_SDRAM_MC_MRSCODE ((volatile u32*)(INCA_IP_SDRAM+ 0x1008)) #define INCA_IP_SDRAM_MC_MRSCODE_UMC (value) (((( 1 << 5) - 1) & (value)) << 7) #define INCA_IP_SDRAM_MC_MRSCODE_CL (value) (((( 1 << 3) - 1) & (value)) << 4) #define INCA_IP_SDRAM_MC_MRSCODE_WT (1 << 3) #define INCA_IP_SDRAM_MC_MRSCODE_BL (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***MC Configuration Data-word Width Register***/ + +/***MC Configuration Data-word Width Register***/ #define INCA_IP_SDRAM_MC_CFGDW ((volatile u32*)(INCA_IP_SDRAM+ 0x1010)) #define INCA_IP_SDRAM_MC_CFGDW_DW (value) (((( 1 << 4) - 1) & (value)) << 0) #define INCA_IP_SDRAM_MC_CFGDW_Res (value) (((( 1 << 28) - 1) & (value)) << 4) - -/***MC Configuration Physical Bank 0 Register***/ + +/***MC Configuration Physical Bank 0 Register***/ #define INCA_IP_SDRAM_MC_CFGPB0 ((volatile u32*)(INCA_IP_SDRAM+ 0x1018)) #define INCA_IP_SDRAM_MC_CFGPB0_MCSEN0 (value) (((( 1 << 4) - 1) & (value)) << 12) #define INCA_IP_SDRAM_MC_CFGPB0_BANKN0 (value) (((( 1 << 4) - 1) & (value)) << 8) #define INCA_IP_SDRAM_MC_CFGPB0_ROWW0 (value) (((( 1 << 4) - 1) & (value)) << 4) #define INCA_IP_SDRAM_MC_CFGPB0_COLW0 (value) (((( 1 << 4) - 1) & (value)) << 0) #define INCA_IP_SDRAM_MC_CFGPB0_Res (value) (((( 1 << 16) - 1) & (value)) << 16) - -/***MC Latency Register***/ + +/***MC Latency Register***/ #define INCA_IP_SDRAM_MC_LATENCY ((volatile u32*)(INCA_IP_SDRAM+ 0x1038)) #define INCA_IP_SDRAM_MC_LATENCY_TRP (value) (((( 1 << 4) - 1) & (value)) << 16) #define INCA_IP_SDRAM_MC_LATENCY_TRAS (value) (((( 1 << 4) - 1) & (value)) << 12) @@ -1059,27 +1059,27 @@ #define INCA_IP_SDRAM_MC_LATENCY_TDPL (value) (((( 1 << 4) - 1) & (value)) << 4) #define INCA_IP_SDRAM_MC_LATENCY_TDAL (value) (((( 1 << 4) - 1) & (value)) << 0) #define INCA_IP_SDRAM_MC_LATENCY_Res (value) (((( 1 << 12) - 1) & (value)) << 20) - -/***MC Refresh Cycle Time Register***/ + +/***MC Refresh Cycle Time Register***/ #define INCA_IP_SDRAM_MC_TREFRESH ((volatile u32*)(INCA_IP_SDRAM+ 0x1040)) #define INCA_IP_SDRAM_MC_TREFRESH_TREF (value) (((( 1 << 13) - 1) & (value)) << 0) -#define INCA_IP_SDRAM_MC_TREFRESH_Res (value) (((( 1 << 19) - 1) & (value)) << 13) - +#define INCA_IP_SDRAM_MC_TREFRESH_Res (value) (((( 1 << 19) - 1) & (value)) << 13) + /***********************************************************************/ /* Module : GPTU register address and bits */ /***********************************************************************/ - + #define INCA_IP_GPTU (0xB8000300) -/***********************************************************************/ +/***********************************************************************/ + - -/***GPT Clock Control Register***/ +/***GPT Clock Control Register***/ #define INCA_IP_GPTU_GPT_CLC ((volatile u32*)(INCA_IP_GPTU+ 0x0000)) #define INCA_IP_GPTU_GPT_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) #define INCA_IP_GPTU_GPT_CLC_DISS (1 << 1) #define INCA_IP_GPTU_GPT_CLC_DISR (1 << 0) - -/***GPT Timer 3 Control Register***/ + +/***GPT Timer 3 Control Register***/ #define INCA_IP_GPTU_GPT_T3CON ((volatile u32*)(INCA_IP_GPTU+ 0x0014)) #define INCA_IP_GPTU_GPT_T3CON_T3RDIR (1 << 15) #define INCA_IP_GPTU_GPT_T3CON_T3CHDIR (1 << 14) @@ -1090,8 +1090,8 @@ #define INCA_IP_GPTU_GPT_T3CON_T3R (1 << 6) #define INCA_IP_GPTU_GPT_T3CON_T3M (value) (((( 1 << 3) - 1) & (value)) << 3) #define INCA_IP_GPTU_GPT_T3CON_T3I (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Write Hardware Modified Timer 3 Control Register + +/***GPT Write Hardware Modified Timer 3 Control Register If set and clear bit are written concurrently with 1, the associated bit is not changed.***/ #define INCA_IP_GPTU_GPT_WHBT3CON ((volatile u32*)(INCA_IP_GPTU+ 0x004C)) #define INCA_IP_GPTU_GPT_WHBT3CON_SETT3CHDIR (1 << 15) @@ -1100,8 +1100,8 @@ If set and clear bit are written concurrently with 1, the associated bit is not #define INCA_IP_GPTU_GPT_WHBT3CON_CLRT3EDGE (1 << 12) #define INCA_IP_GPTU_GPT_WHBT3CON_SETT3OTL (1 << 11) #define INCA_IP_GPTU_GPT_WHBT3CON_CLRT3OTL (1 << 10) - -/***GPT Timer 2 Control Register***/ + +/***GPT Timer 2 Control Register***/ #define INCA_IP_GPTU_GPT_T2CON ((volatile u32*)(INCA_IP_GPTU+ 0x0010)) #define INCA_IP_GPTU_GPT_T2CON_TxRDIR (1 << 15) #define INCA_IP_GPTU_GPT_T2CON_TxCHDIR (1 << 14) @@ -1112,8 +1112,8 @@ If set and clear bit are written concurrently with 1, the associated bit is not #define INCA_IP_GPTU_GPT_T2CON_TxR (1 << 6) #define INCA_IP_GPTU_GPT_T2CON_TxM (value) (((( 1 << 3) - 1) & (value)) << 3) #define INCA_IP_GPTU_GPT_T2CON_TxI (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Timer 4 Control Register***/ + +/***GPT Timer 4 Control Register***/ #define INCA_IP_GPTU_GPT_T4CON ((volatile u32*)(INCA_IP_GPTU+ 0x0018)) #define INCA_IP_GPTU_GPT_T4CON_TxRDIR (1 << 15) #define INCA_IP_GPTU_GPT_T4CON_TxCHDIR (1 << 14) @@ -1124,7 +1124,7 @@ If set and clear bit are written concurrently with 1, the associated bit is not #define INCA_IP_GPTU_GPT_T4CON_TxR (1 << 6) #define INCA_IP_GPTU_GPT_T4CON_TxM (value) (((( 1 << 3) - 1) & (value)) << 3) #define INCA_IP_GPTU_GPT_T4CON_TxI (value) (((( 1 << 3) - 1) & (value)) << 0) - + /***GPT Write HW Modified Timer 2 Control Register If set and clear bit are written concurrently with 1, the associated bit is not changed.***/ #define INCA_IP_GPTU_GPT_WHBT2CON ((volatile u32*)(INCA_IP_GPTU+ 0x0048)) @@ -1132,7 +1132,7 @@ If set and clear bit are written concurrently with 1, the associated bit is not #define INCA_IP_GPTU_GPT_WHBT2CON_CLRTxCHDIR (1 << 14) #define INCA_IP_GPTU_GPT_WHBT2CON_SETTxEDGE (1 << 13) #define INCA_IP_GPTU_GPT_WHBT2CON_CLRTxEDGE (1 << 12) - + /***GPT Write HW Modified Timer 4 Control Register If set and clear bit are written concurrently with 1, the associated bit is not changed.***/ #define INCA_IP_GPTU_GPT_WHBT4CON ((volatile u32*)(INCA_IP_GPTU+ 0x0050)) @@ -1140,32 +1140,32 @@ If set and clear bit are written concurrently with 1, the associated bit is not #define INCA_IP_GPTU_GPT_WHBT4CON_CLRTxCHDIR (1 << 14) #define INCA_IP_GPTU_GPT_WHBT4CON_SETTxEDGE (1 << 13) #define INCA_IP_GPTU_GPT_WHBT4CON_CLRTxEDGE (1 << 12) - -/***GPT Capture Reload Register***/ + +/***GPT Capture Reload Register***/ #define INCA_IP_GPTU_GPT_CAPREL ((volatile u32*)(INCA_IP_GPTU+ 0x0030)) #define INCA_IP_GPTU_GPT_CAPREL_CAPREL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 2 Register***/ + +/***GPT Timer 2 Register***/ #define INCA_IP_GPTU_GPT_T2 ((volatile u32*)(INCA_IP_GPTU+ 0x0034)) #define INCA_IP_GPTU_GPT_T2_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 3 Register***/ + +/***GPT Timer 3 Register***/ #define INCA_IP_GPTU_GPT_T3 ((volatile u32*)(INCA_IP_GPTU+ 0x0038)) #define INCA_IP_GPTU_GPT_T3_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 4 Register***/ + +/***GPT Timer 4 Register***/ #define INCA_IP_GPTU_GPT_T4 ((volatile u32*)(INCA_IP_GPTU+ 0x003C)) #define INCA_IP_GPTU_GPT_T4_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 5 Register***/ + +/***GPT Timer 5 Register***/ #define INCA_IP_GPTU_GPT_T5 ((volatile u32*)(INCA_IP_GPTU+ 0x0040)) #define INCA_IP_GPTU_GPT_T5_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 6 Register***/ + +/***GPT Timer 6 Register***/ #define INCA_IP_GPTU_GPT_T6 ((volatile u32*)(INCA_IP_GPTU+ 0x0044)) #define INCA_IP_GPTU_GPT_T6_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 6 Control Register***/ + +/***GPT Timer 6 Control Register***/ #define INCA_IP_GPTU_GPT_T6CON ((volatile u32*)(INCA_IP_GPTU+ 0x0020)) #define INCA_IP_GPTU_GPT_T6CON_T6SR (1 << 15) #define INCA_IP_GPTU_GPT_T6CON_T6CLR (1 << 14) @@ -1175,14 +1175,14 @@ If set and clear bit are written concurrently with 1, the associated bit is not #define INCA_IP_GPTU_GPT_T6CON_T6R (1 << 6) #define INCA_IP_GPTU_GPT_T6CON_T6M (value) (((( 1 << 3) - 1) & (value)) << 3) #define INCA_IP_GPTU_GPT_T6CON_T6I (value) (((( 1 << 3) - 1) & (value)) << 0) - + /***GPT Write HW Modified Timer 6 Control Register If set and clear bit are written concurrently with 1, the associated bit is not changed.***/ #define INCA_IP_GPTU_GPT_WHBT6CON ((volatile u32*)(INCA_IP_GPTU+ 0x0054)) #define INCA_IP_GPTU_GPT_WHBT6CON_SETT6OTL (1 << 11) #define INCA_IP_GPTU_GPT_WHBT6CON_CLRT6OTL (1 << 10) - -/***GPT Timer 5 Control Register***/ + +/***GPT Timer 5 Control Register***/ #define INCA_IP_GPTU_GPT_T5CON ((volatile u32*)(INCA_IP_GPTU+ 0x001C)) #define INCA_IP_GPTU_GPT_T5CON_T5SC (1 << 15) #define INCA_IP_GPTU_GPT_T5CON_T5CLR (1 << 14) @@ -1194,25 +1194,25 @@ If set and clear bit are written concurrently with 1, the associated bit is not #define INCA_IP_GPTU_GPT_T5CON_T5UD (1 << 7) #define INCA_IP_GPTU_GPT_T5CON_T5R (1 << 6) #define INCA_IP_GPTU_GPT_T5CON_T5M (value) (((( 1 << 3) - 1) & (value)) << 3) -#define INCA_IP_GPTU_GPT_T5CON_T5I (value) (((( 1 << 3) - 1) & (value)) << 0) - +#define INCA_IP_GPTU_GPT_T5CON_T5I (value) (((( 1 << 3) - 1) & (value)) << 0) + /***********************************************************************/ /* Module : IOM register address and bits */ /***********************************************************************/ - + #define INCA_IP_IOM (0xBF105000) -/***********************************************************************/ +/***********************************************************************/ - -/***Receive FIFO***/ + +/***Receive FIFO***/ #define INCA_IP_IOM_RFIFO ((volatile u32*)(INCA_IP_IOM+ 0x0000)) #define INCA_IP_IOM_RFIFO_RXD (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Transmit FIFO***/ + +/***Transmit FIFO***/ #define INCA_IP_IOM_XFIFO ((volatile u32*)(INCA_IP_IOM+ 0x0000)) #define INCA_IP_IOM_XFIFO_TXD (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Interrupt Status Register HDLC***/ + +/***Interrupt Status Register HDLC***/ #define INCA_IP_IOM_ISTAH ((volatile u32*)(INCA_IP_IOM+ 0x0080)) #define INCA_IP_IOM_ISTAH_RME (1 << 7) #define INCA_IP_IOM_ISTAH_RPF (1 << 6) @@ -1220,8 +1220,8 @@ If set and clear bit are written concurrently with 1, the associated bit is not #define INCA_IP_IOM_ISTAH_XPR (1 << 4) #define INCA_IP_IOM_ISTAH_XMR (1 << 3) #define INCA_IP_IOM_ISTAH_XDU (1 << 2) - -/***Interrupt Mask Register HDLC***/ + +/***Interrupt Mask Register HDLC***/ #define INCA_IP_IOM_MASKH ((volatile u32*)(INCA_IP_IOM+ 0x0080)) #define INCA_IP_IOM_MASKH_RME (1 << 7) #define INCA_IP_IOM_MASKH_RPF (1 << 6) @@ -1229,23 +1229,23 @@ If set and clear bit are written concurrently with 1, the associated bit is not #define INCA_IP_IOM_MASKH_XPR (1 << 4) #define INCA_IP_IOM_MASKH_XMR (1 << 3) #define INCA_IP_IOM_MASKH_XDU (1 << 2) - -/***Status Register***/ + +/***Status Register***/ #define INCA_IP_IOM_STAR ((volatile u32*)(INCA_IP_IOM+ 0x0084)) #define INCA_IP_IOM_STAR_XDOV (1 << 7) #define INCA_IP_IOM_STAR_XFW (1 << 6) #define INCA_IP_IOM_STAR_RACI (1 << 3) #define INCA_IP_IOM_STAR_XACI (1 << 1) - -/***Command Register***/ + +/***Command Register***/ #define INCA_IP_IOM_CMDR ((volatile u32*)(INCA_IP_IOM+ 0x0084)) #define INCA_IP_IOM_CMDR_RMC (1 << 7) #define INCA_IP_IOM_CMDR_RRES (1 << 6) #define INCA_IP_IOM_CMDR_XTF (1 << 3) #define INCA_IP_IOM_CMDR_XME (1 << 1) #define INCA_IP_IOM_CMDR_XRES (1 << 0) - -/***Mode Register***/ + +/***Mode Register***/ #define INCA_IP_IOM_MODEH ((volatile u32*)(INCA_IP_IOM+ 0x0088)) #define INCA_IP_IOM_MODEH_MDS2 (1 << 7) #define INCA_IP_IOM_MODEH_MDS1 (1 << 6) @@ -1254,8 +1254,8 @@ If set and clear bit are written concurrently with 1, the associated bit is not #define INCA_IP_IOM_MODEH_DIM2 (1 << 2) #define INCA_IP_IOM_MODEH_DIM1 (1 << 1) #define INCA_IP_IOM_MODEH_DIM0 (1 << 0) - -/***Extended Mode Register***/ + +/***Extended Mode Register***/ #define INCA_IP_IOM_EXMR ((volatile u32*)(INCA_IP_IOM+ 0x008C)) #define INCA_IP_IOM_EXMR_XFBS (1 << 7) #define INCA_IP_IOM_EXMR_RFBS (value) (((( 1 << 2) - 1) & (value)) << 5) @@ -1263,36 +1263,36 @@ If set and clear bit are written concurrently with 1, the associated bit is not #define INCA_IP_IOM_EXMR_XCRC (1 << 3) #define INCA_IP_IOM_EXMR_RCRC (1 << 2) #define INCA_IP_IOM_EXMR_ITF (1 << 0) - -/***SAPI1 Register***/ + +/***SAPI1 Register***/ #define INCA_IP_IOM_SAP1 ((volatile u32*)(INCA_IP_IOM+ 0x0094)) #define INCA_IP_IOM_SAP1_SAPI1 (value) (((( 1 << 6) - 1) & (value)) << 2) #define INCA_IP_IOM_SAP1_MHA (1 << 0) - -/***Receive Frame Byte Count Low***/ + +/***Receive Frame Byte Count Low***/ #define INCA_IP_IOM_RBCL ((volatile u32*)(INCA_IP_IOM+ 0x0098)) #define INCA_IP_IOM_RBCL_RBC(value) (1 << value) - - -/***SAPI2 Register***/ + + +/***SAPI2 Register***/ #define INCA_IP_IOM_SAP2 ((volatile u32*)(INCA_IP_IOM+ 0x0098)) #define INCA_IP_IOM_SAP2_SAPI2 (value) (((( 1 << 6) - 1) & (value)) << 2) #define INCA_IP_IOM_SAP2_MLA (1 << 0) - -/***Receive Frame Byte Count High***/ + +/***Receive Frame Byte Count High***/ #define INCA_IP_IOM_RBCH ((volatile u32*)(INCA_IP_IOM+ 0x009C)) #define INCA_IP_IOM_RBCH_OV (1 << 4) #define INCA_IP_IOM_RBCH_RBC11 (1 << 3) #define INCA_IP_IOM_RBCH_RBC10 (1 << 2) #define INCA_IP_IOM_RBCH_RBC9 (1 << 1) #define INCA_IP_IOM_RBCH_RBC8 (1 << 0) - -/***TEI1 Register 1***/ + +/***TEI1 Register 1***/ #define INCA_IP_IOM_TEI1 ((volatile u32*)(INCA_IP_IOM+ 0x009C)) #define INCA_IP_IOM_TEI1_TEI1 (value) (((( 1 << 7) - 1) & (value)) << 1) #define INCA_IP_IOM_TEI1_EA (1 << 0) - -/***Receive Status Register***/ + +/***Receive Status Register***/ #define INCA_IP_IOM_RSTA ((volatile u32*)(INCA_IP_IOM+ 0x00A0)) #define INCA_IP_IOM_RSTA_VFR (1 << 7) #define INCA_IP_IOM_RSTA_RDO (1 << 6) @@ -1302,99 +1302,99 @@ If set and clear bit are written concurrently with 1, the associated bit is not #define INCA_IP_IOM_RSTA_SA0 (1 << 2) #define INCA_IP_IOM_RSTA_TA (1 << 0) #define INCA_IP_IOM_RSTA_CR (1 << 1) - -/***TEI2 Register***/ + +/***TEI2 Register***/ #define INCA_IP_IOM_TEI2 ((volatile u32*)(INCA_IP_IOM+ 0x00A0)) #define INCA_IP_IOM_TEI2_TEI2 (value) (((( 1 << 7) - 1) & (value)) << 1) #define INCA_IP_IOM_TEI2_EA (1 << 0) - -/***Test Mode Register HDLC***/ + +/***Test Mode Register HDLC***/ #define INCA_IP_IOM_TMH ((volatile u32*)(INCA_IP_IOM+ 0x00A4)) #define INCA_IP_IOM_TMH_TLP (1 << 0) - -/***Command/Indication Receive 0***/ + +/***Command/Indication Receive 0***/ #define INCA_IP_IOM_CIR0 ((volatile u32*)(INCA_IP_IOM+ 0x00B8)) #define INCA_IP_IOM_CIR0_CODR0 (value) (((( 1 << 4) - 1) & (value)) << 4) #define INCA_IP_IOM_CIR0_CIC0 (1 << 3) #define INCA_IP_IOM_CIR0_CIC1 (1 << 2) #define INCA_IP_IOM_CIR0_SG (1 << 1) #define INCA_IP_IOM_CIR0_BAS (1 << 0) - -/***Command/Indication Transmit 0***/ + +/***Command/Indication Transmit 0***/ #define INCA_IP_IOM_CIX0 ((volatile u32*)(INCA_IP_IOM+ 0x00B8)) #define INCA_IP_IOM_CIX0_CODX0 (value) (((( 1 << 4) - 1) & (value)) << 4) #define INCA_IP_IOM_CIX0_TBA2 (1 << 3) #define INCA_IP_IOM_CIX0_TBA1 (1 << 2) #define INCA_IP_IOM_CIX0_TBA0 (1 << 1) #define INCA_IP_IOM_CIX0_BAC (1 << 0) - -/***Command/Indication Receive 1***/ + +/***Command/Indication Receive 1***/ #define INCA_IP_IOM_CIR1 ((volatile u32*)(INCA_IP_IOM+ 0x00BC)) #define INCA_IP_IOM_CIR1_CODR1 (value) (((( 1 << 6) - 1) & (value)) << 2) - -/***Command/Indication Transmit 1***/ + +/***Command/Indication Transmit 1***/ #define INCA_IP_IOM_CIX1 ((volatile u32*)(INCA_IP_IOM+ 0x00BC)) #define INCA_IP_IOM_CIX1_CODX1 (value) (((( 1 << 6) - 1) & (value)) << 2) #define INCA_IP_IOM_CIX1_CICW (1 << 1) #define INCA_IP_IOM_CIX1_CI1E (1 << 0) - -/***Controller Data Access Reg. (CH10)***/ + +/***Controller Data Access Reg. (CH10)***/ #define INCA_IP_IOM_CDA10 ((volatile u32*)(INCA_IP_IOM+ 0x0100)) #define INCA_IP_IOM_CDA10_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Controller Data Access Reg. (CH11)***/ + +/***Controller Data Access Reg. (CH11)***/ #define INCA_IP_IOM_CDA11 ((volatile u32*)(INCA_IP_IOM+ 0x0104)) #define INCA_IP_IOM_CDA11_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Controller Data Access Reg. (CH20)***/ + +/***Controller Data Access Reg. (CH20)***/ #define INCA_IP_IOM_CDA20 ((volatile u32*)(INCA_IP_IOM+ 0x0108)) #define INCA_IP_IOM_CDA20_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Controller Data Access Reg. (CH21)***/ + +/***Controller Data Access Reg. (CH21)***/ #define INCA_IP_IOM_CDA21 ((volatile u32*)(INCA_IP_IOM+ 0x010C)) #define INCA_IP_IOM_CDA21_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH10)***/ + +/***Time Slot and Data Port Sel. (CH10)***/ #define INCA_IP_IOM_CDA_TSDP10 ((volatile u32*)(INCA_IP_IOM+ 0x0110)) #define INCA_IP_IOM_CDA_TSDP10_DPS (1 << 7) #define INCA_IP_IOM_CDA_TSDP10_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH11)***/ + +/***Time Slot and Data Port Sel. (CH11)***/ #define INCA_IP_IOM_CDA_TSDP11 ((volatile u32*)(INCA_IP_IOM+ 0x0114)) #define INCA_IP_IOM_CDA_TSDP11_DPS (1 << 7) #define INCA_IP_IOM_CDA_TSDP11_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH20)***/ + +/***Time Slot and Data Port Sel. (CH20)***/ #define INCA_IP_IOM_CDA_TSDP20 ((volatile u32*)(INCA_IP_IOM+ 0x0118)) #define INCA_IP_IOM_CDA_TSDP20_DPS (1 << 7) #define INCA_IP_IOM_CDA_TSDP20_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH21)***/ + +/***Time Slot and Data Port Sel. (CH21)***/ #define INCA_IP_IOM_CDA_TSDP21 ((volatile u32*)(INCA_IP_IOM+ 0x011C)) #define INCA_IP_IOM_CDA_TSDP21_DPS (1 << 7) #define INCA_IP_IOM_CDA_TSDP21_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH10)***/ + +/***Time Slot and Data Port Sel. (CH10)***/ #define INCA_IP_IOM_CO_TSDP10 ((volatile u32*)(INCA_IP_IOM+ 0x0120)) #define INCA_IP_IOM_CO_TSDP10_DPS (1 << 7) #define INCA_IP_IOM_CO_TSDP10_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH11)***/ + +/***Time Slot and Data Port Sel. (CH11)***/ #define INCA_IP_IOM_CO_TSDP11 ((volatile u32*)(INCA_IP_IOM+ 0x0124)) #define INCA_IP_IOM_CO_TSDP11_DPS (1 << 7) #define INCA_IP_IOM_CO_TSDP11_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH20)***/ + +/***Time Slot and Data Port Sel. (CH20)***/ #define INCA_IP_IOM_CO_TSDP20 ((volatile u32*)(INCA_IP_IOM+ 0x0128)) #define INCA_IP_IOM_CO_TSDP20_DPS (1 << 7) #define INCA_IP_IOM_CO_TSDP20_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH21)***/ + +/***Time Slot and Data Port Sel. (CH21)***/ #define INCA_IP_IOM_CO_TSDP21 ((volatile u32*)(INCA_IP_IOM+ 0x012C)) #define INCA_IP_IOM_CO_TSDP21_DPS (1 << 7) #define INCA_IP_IOM_CO_TSDP21_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Ctrl. Reg. Contr. Data Access CH1x***/ + +/***Ctrl. Reg. Contr. Data Access CH1x***/ #define INCA_IP_IOM_CDA1_CR ((volatile u32*)(INCA_IP_IOM+ 0x0138)) #define INCA_IP_IOM_CDA1_CR_EN_TBM (1 << 5) #define INCA_IP_IOM_CDA1_CR_EN_I1 (1 << 4) @@ -1402,8 +1402,8 @@ If set and clear bit are written concurrently with 1, the associated bit is not #define INCA_IP_IOM_CDA1_CR_EN_O1 (1 << 2) #define INCA_IP_IOM_CDA1_CR_EN_O0 (1 << 1) #define INCA_IP_IOM_CDA1_CR_SWAP (1 << 0) - -/***Ctrl. Reg. Contr. Data Access CH1x***/ + +/***Ctrl. Reg. Contr. Data Access CH1x***/ #define INCA_IP_IOM_CDA2_CR ((volatile u32*)(INCA_IP_IOM+ 0x013C)) #define INCA_IP_IOM_CDA2_CR_EN_TBM (1 << 5) #define INCA_IP_IOM_CDA2_CR_EN_I1 (1 << 4) @@ -1411,37 +1411,37 @@ If set and clear bit are written concurrently with 1, the associated bit is not #define INCA_IP_IOM_CDA2_CR_EN_O1 (1 << 2) #define INCA_IP_IOM_CDA2_CR_EN_O0 (1 << 1) #define INCA_IP_IOM_CDA2_CR_SWAP (1 << 0) - -/***Control Register B-Channel Data***/ + +/***Control Register B-Channel Data***/ #define INCA_IP_IOM_BCHA_CR ((volatile u32*)(INCA_IP_IOM+ 0x0144)) #define INCA_IP_IOM_BCHA_CR_EN_BC2 (1 << 4) #define INCA_IP_IOM_BCHA_CR_EN_BC1 (1 << 3) - -/***Control Register B-Channel Data***/ + +/***Control Register B-Channel Data***/ #define INCA_IP_IOM_BCHB_CR ((volatile u32*)(INCA_IP_IOM+ 0x0148)) #define INCA_IP_IOM_BCHB_CR_EN_BC2 (1 << 4) #define INCA_IP_IOM_BCHB_CR_EN_BC1 (1 << 3) - -/***Control Reg. for HDLC and CI1 Data***/ + +/***Control Reg. for HDLC and CI1 Data***/ #define INCA_IP_IOM_DCI_CR ((volatile u32*)(INCA_IP_IOM+ 0x014C)) #define INCA_IP_IOM_DCI_CR_DPS_CI1 (1 << 7) #define INCA_IP_IOM_DCI_CR_EN_CI1 (1 << 6) #define INCA_IP_IOM_DCI_CR_EN_D (1 << 5) - -/***Control Reg. for HDLC and CI1 Data***/ + +/***Control Reg. for HDLC and CI1 Data***/ #define INCA_IP_IOM_DCIC_CR ((volatile u32*)(INCA_IP_IOM+ 0x014C)) #define INCA_IP_IOM_DCIC_CR_DPS_CI0 (1 << 7) #define INCA_IP_IOM_DCIC_CR_EN_CI0 (1 << 6) #define INCA_IP_IOM_DCIC_CR_DPS_D (1 << 5) - -/***Control Reg. Serial Data Strobe x***/ + +/***Control Reg. Serial Data Strobe x***/ #define INCA_IP_IOM_SDS_CR ((volatile u32*)(INCA_IP_IOM+ 0x0154)) #define INCA_IP_IOM_SDS_CR_ENS_TSS (1 << 7) #define INCA_IP_IOM_SDS_CR_ENS_TSS_1 (1 << 6) #define INCA_IP_IOM_SDS_CR_ENS_TSS_3 (1 << 5) #define INCA_IP_IOM_SDS_CR_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Control Register IOM Data***/ + +/***Control Register IOM Data***/ #define INCA_IP_IOM_IOM_CR ((volatile u32*)(INCA_IP_IOM+ 0x015C)) #define INCA_IP_IOM_IOM_CR_SPU (1 << 7) #define INCA_IP_IOM_IOM_CR_CI_CS (1 << 5) @@ -1450,8 +1450,8 @@ If set and clear bit are written concurrently with 1, the associated bit is not #define INCA_IP_IOM_IOM_CR_CLKM (1 << 2) #define INCA_IP_IOM_IOM_CR_Res (1 << 1) #define INCA_IP_IOM_IOM_CR_DIS_IOM (1 << 0) - -/***Synchronous Transfer Interrupt***/ + +/***Synchronous Transfer Interrupt***/ #define INCA_IP_IOM_STI ((volatile u32*)(INCA_IP_IOM+ 0x0160)) #define INCA_IP_IOM_STI_STOV21 (1 << 7) #define INCA_IP_IOM_STI_STOV20 (1 << 6) @@ -1461,15 +1461,15 @@ If set and clear bit are written concurrently with 1, the associated bit is not #define INCA_IP_IOM_STI_STI20 (1 << 2) #define INCA_IP_IOM_STI_STI11 (1 << 1) #define INCA_IP_IOM_STI_STI10 (1 << 0) - -/***Acknowledge Synchronous Transfer Interrupt***/ + +/***Acknowledge Synchronous Transfer Interrupt***/ #define INCA_IP_IOM_ASTI ((volatile u32*)(INCA_IP_IOM+ 0x0160)) #define INCA_IP_IOM_ASTI_ACK21 (1 << 3) #define INCA_IP_IOM_ASTI_ACK20 (1 << 2) #define INCA_IP_IOM_ASTI_ACK11 (1 << 1) #define INCA_IP_IOM_ASTI_ACK10 (1 << 0) - -/***Mask Synchronous Transfer Interrupt***/ + +/***Mask Synchronous Transfer Interrupt***/ #define INCA_IP_IOM_MSTI ((volatile u32*)(INCA_IP_IOM+ 0x0164)) #define INCA_IP_IOM_MSTI_STOV21 (1 << 7) #define INCA_IP_IOM_MSTI_STOV20 (1 << 6) @@ -1479,36 +1479,36 @@ If set and clear bit are written concurrently with 1, the associated bit is not #define INCA_IP_IOM_MSTI_STI20 (1 << 2) #define INCA_IP_IOM_MSTI_STI11 (1 << 1) #define INCA_IP_IOM_MSTI_STI10 (1 << 0) - -/***Configuration Register for Serial Data Strobes***/ + +/***Configuration Register for Serial Data Strobes***/ #define INCA_IP_IOM_SDS_CONF ((volatile u32*)(INCA_IP_IOM+ 0x0168)) #define INCA_IP_IOM_SDS_CONF_SDS_BCL (1 << 0) - -/***Monitoring CDA Bits***/ + +/***Monitoring CDA Bits***/ #define INCA_IP_IOM_MCDA ((volatile u32*)(INCA_IP_IOM+ 0x016C)) #define INCA_IP_IOM_MCDA_MCDA21 (value) (((( 1 << 2) - 1) & (value)) << 6) #define INCA_IP_IOM_MCDA_MCDA20 (value) (((( 1 << 2) - 1) & (value)) << 4) #define INCA_IP_IOM_MCDA_MCDA11 (value) (((( 1 << 2) - 1) & (value)) << 2) -#define INCA_IP_IOM_MCDA_MCDA10 (value) (((( 1 << 2) - 1) & (value)) << 0) - +#define INCA_IP_IOM_MCDA_MCDA10 (value) (((( 1 << 2) - 1) & (value)) << 0) + /***********************************************************************/ /* Module : ASC register address and bits */ /***********************************************************************/ - + #if defined(CONFIG_INCA_IP) #define INCA_IP_ASC (0xB8000400) #elif defined(CONFIG_PURPLE) #define INCA_IP_ASC (0xBE500000) #endif -/***********************************************************************/ +/***********************************************************************/ + - -/***ASC Port Input Select Register***/ +/***ASC Port Input Select Register***/ #define INCA_IP_ASC_ASC_PISEL ((volatile u32*)(INCA_IP_ASC+ 0x0004)) #define INCA_IP_ASC_ASC_PISEL_RIS (1 << 0) - -/***ASC Control Register***/ + +/***ASC Control Register***/ #define INCA_IP_ASC_ASC_CON ((volatile u32*)(INCA_IP_ASC+ 0x0010)) #define INCA_IP_ASC_ASC_CON_R (1 << 15) #define INCA_IP_ASC_ASC_CON_LB (1 << 14) @@ -1524,8 +1524,8 @@ If set and clear bit are written concurrently with 1, the associated bit is not #define INCA_IP_ASC_ASC_CON_REN (1 << 4) #define INCA_IP_ASC_ASC_CON_STP (1 << 3) #define INCA_IP_ASC_ASC_CON_M (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***ASC Write Hardware Modified Control Register***/ + +/***ASC Write Hardware Modified Control Register***/ #define INCA_IP_ASC_ASC_WHBCON ((volatile u32*)(INCA_IP_ASC+ 0x0050)) #define INCA_IP_ASC_ASC_WHBCON_SETOE (1 << 13) #define INCA_IP_ASC_ASC_WHBCON_SETFE (1 << 12) @@ -1535,29 +1535,29 @@ If set and clear bit are written concurrently with 1, the associated bit is not #define INCA_IP_ASC_ASC_WHBCON_CLRPE (1 << 8) #define INCA_IP_ASC_ASC_WHBCON_SETREN (1 << 5) #define INCA_IP_ASC_ASC_WHBCON_CLRREN (1 << 4) - -/***ASC Baudrate Timer/Reload Register***/ + +/***ASC Baudrate Timer/Reload Register***/ #define INCA_IP_ASC_ASC_BTR ((volatile u32*)(INCA_IP_ASC+ 0x0014)) #define INCA_IP_ASC_ASC_BTR_BR_VALUE (value) (((( 1 << 13) - 1) & (value)) << 0) - -/***ASC Fractional Divider Register***/ + +/***ASC Fractional Divider Register***/ #define INCA_IP_ASC_ASC_FDV ((volatile u32*)(INCA_IP_ASC+ 0x0018)) #define INCA_IP_ASC_ASC_FDV_FD_VALUE (value) (((( 1 << 9) - 1) & (value)) << 0) - -/***ASC IrDA Pulse Mode/Width Register***/ + +/***ASC IrDA Pulse Mode/Width Register***/ #define INCA_IP_ASC_ASC_PMW ((volatile u32*)(INCA_IP_ASC+ 0x001C)) #define INCA_IP_ASC_ASC_PMW_IRPW (1 << 8) #define INCA_IP_ASC_ASC_PMW_PW_VALUE (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***ASC Transmit Buffer Register***/ + +/***ASC Transmit Buffer Register***/ #define INCA_IP_ASC_ASC_TBUF ((volatile u32*)(INCA_IP_ASC+ 0x0020)) #define INCA_IP_ASC_ASC_TBUF_TD_VALUE (value) (((( 1 << 9) - 1) & (value)) << 0) - -/***ASC Receive Buffer Register***/ + +/***ASC Receive Buffer Register***/ #define INCA_IP_ASC_ASC_RBUF ((volatile u32*)(INCA_IP_ASC+ 0x0024)) #define INCA_IP_ASC_ASC_RBUF_RD_VALUE (value) (((( 1 << 9) - 1) & (value)) << 0) - -/***ASC Autobaud Control Register***/ + +/***ASC Autobaud Control Register***/ #define INCA_IP_ASC_ASC_ABCON ((volatile u32*)(INCA_IP_ASC+ 0x0030)) #define INCA_IP_ASC_ASC_ABCON_RXINV (1 << 11) #define INCA_IP_ASC_ASC_ABCON_TXINV (1 << 10) @@ -1567,40 +1567,40 @@ If set and clear bit are written concurrently with 1, the associated bit is not #define INCA_IP_ASC_ASC_ABCON_ABSTEN (1 << 2) #define INCA_IP_ASC_ASC_ABCON_AUREN (1 << 1) #define INCA_IP_ASC_ASC_ABCON_ABEN (1 << 0) - -/***Receive FIFO Control Register***/ + +/***Receive FIFO Control Register***/ #define INCA_IP_ASC_RXFCON ((volatile u32*)(INCA_IP_ASC+ 0x0040)) #define INCA_IP_ASC_RXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) #define INCA_IP_ASC_RXFCON_RXTMEN (1 << 2) #define INCA_IP_ASC_RXFCON_RXFFLU (1 << 1) #define INCA_IP_ASC_RXFCON_RXFEN (1 << 0) - -/***Transmit FIFO Control Register***/ + +/***Transmit FIFO Control Register***/ #define INCA_IP_ASC_TXFCON ((volatile u32*)(INCA_IP_ASC+ 0x0044)) #define INCA_IP_ASC_TXFCON_TXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) #define INCA_IP_ASC_TXFCON_TXTMEN (1 << 2) #define INCA_IP_ASC_TXFCON_TXFFLU (1 << 1) #define INCA_IP_ASC_TXFCON_TXFEN (1 << 0) - -/***FIFO Status Register***/ + +/***FIFO Status Register***/ #define INCA_IP_ASC_FSTAT ((volatile u32*)(INCA_IP_ASC+ 0x0048)) #define INCA_IP_ASC_FSTAT_TXFFL (value) (((( 1 << 6) - 1) & (value)) << 8) #define INCA_IP_ASC_FSTAT_RXFFL (value) (((( 1 << 6) - 1) & (value)) << 0) - -/***ASC Write HW Modified Autobaud Control Register***/ + +/***ASC Write HW Modified Autobaud Control Register***/ #define INCA_IP_ASC_ASC_WHBABCON ((volatile u32*)(INCA_IP_ASC+ 0x0054)) #define INCA_IP_ASC_ASC_WHBABCON_SETABEN (1 << 1) #define INCA_IP_ASC_ASC_WHBABCON_CLRABEN (1 << 0) - -/***ASC Autobaud Status Register***/ + +/***ASC Autobaud Status Register***/ #define INCA_IP_ASC_ASC_ABSTAT ((volatile u32*)(INCA_IP_ASC+ 0x0034)) #define INCA_IP_ASC_ASC_ABSTAT_DETWAIT (1 << 4) #define INCA_IP_ASC_ASC_ABSTAT_SCCDET (1 << 3) #define INCA_IP_ASC_ASC_ABSTAT_SCSDET (1 << 2) #define INCA_IP_ASC_ASC_ABSTAT_FCCDET (1 << 1) #define INCA_IP_ASC_ASC_ABSTAT_FCSDET (1 << 0) - -/***ASC Write HW Modified Autobaud Status Register***/ + +/***ASC Write HW Modified Autobaud Status Register***/ #define INCA_IP_ASC_ASC_WHBABSTAT ((volatile u32*)(INCA_IP_ASC+ 0x0058)) #define INCA_IP_ASC_ASC_WHBABSTAT_SETDETWAIT (1 << 9) #define INCA_IP_ASC_ASC_WHBABSTAT_CLRDETWAIT (1 << 8) @@ -1612,86 +1612,86 @@ If set and clear bit are written concurrently with 1, the associated bit is not #define INCA_IP_ASC_ASC_WHBABSTAT_CLRFCCDET (1 << 2) #define INCA_IP_ASC_ASC_WHBABSTAT_SETFCSDET (1 << 1) #define INCA_IP_ASC_ASC_WHBABSTAT_CLRFCSDET (1 << 0) - -/***ASC Clock Control Register***/ + +/***ASC Clock Control Register***/ #define INCA_IP_ASC_ASC_CLC ((volatile u32*)(INCA_IP_ASC+ 0x0000)) #define INCA_IP_ASC_ASC_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) #define INCA_IP_ASC_ASC_CLC_DISS (1 << 1) -#define INCA_IP_ASC_ASC_CLC_DISR (1 << 0) - +#define INCA_IP_ASC_ASC_CLC_DISR (1 << 0) + /***********************************************************************/ /* Module : DMA register address and bits */ /***********************************************************************/ - + #define INCA_IP_DMA (0xBF108000) -/***********************************************************************/ +/***********************************************************************/ - -/***DMA RX Channel 0 Command Register***/ + +/***DMA RX Channel 0 Command Register***/ #define INCA_IP_DMA_DMA_RXCCR0 ((volatile u32*)(INCA_IP_DMA+ 0x0800)) #define INCA_IP_DMA_DMA_RXCCR0_LBE (1 << 31) #define INCA_IP_DMA_DMA_RXCCR0_HPEN (1 << 30) #define INCA_IP_DMA_DMA_RXCCR0_INIT (1 << 2) #define INCA_IP_DMA_DMA_RXCCR0_OFF (1 << 1) #define INCA_IP_DMA_DMA_RXCCR0_HR (1 << 0) - -/***DMA RX Channel 1 Command Register***/ + +/***DMA RX Channel 1 Command Register***/ #define INCA_IP_DMA_DMA_RXCCR1 ((volatile u32*)(INCA_IP_DMA+ 0x0804)) #define INCA_IP_DMA_DMA_RXCCR1_LBE (1 << 31) #define INCA_IP_DMA_DMA_RXCCR1_HPEN (1 << 30) #define INCA_IP_DMA_DMA_RXCCR1_INIT (1 << 2) #define INCA_IP_DMA_DMA_RXCCR1_OFF (1 << 1) #define INCA_IP_DMA_DMA_RXCCR1_HR (1 << 0) - -/***DMA Receive Interrupt Status Register***/ + +/***DMA Receive Interrupt Status Register***/ #define INCA_IP_DMA_DMA_RXISR ((volatile u32*)(INCA_IP_DMA+ 0x0808)) #define INCA_IP_DMA_DMA_RXISR_RDERRx (value) (((( 1 << 2) - 1) & (value)) << 8) #define INCA_IP_DMA_DMA_RXISR_CMDCPTx (value) (((( 1 << 2) - 1) & (value)) << 6) #define INCA_IP_DMA_DMA_RXISR_EOPx (value) (((( 1 << 2) - 1) & (value)) << 4) #define INCA_IP_DMA_DMA_RXISR_CPTx (value) (((( 1 << 2) - 1) & (value)) << 2) #define INCA_IP_DMA_DMA_RXISR_HLDx (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***DMA Receive Interrupt Mask Register***/ + +/***DMA Receive Interrupt Mask Register***/ #define INCA_IP_DMA_DMA_RXIMR ((volatile u32*)(INCA_IP_DMA+ 0x080C)) #define INCA_IP_DMA_DMA_RXIMR_RDERRx (value) (((( 1 << 2) - 1) & (value)) << 8) #define INCA_IP_DMA_DMA_RXIMR_CMDCPTx (value) (((( 1 << 2) - 1) & (value)) << 6) #define INCA_IP_DMA_DMA_RXIMR_EOPx (value) (((( 1 << 2) - 1) & (value)) << 4) #define INCA_IP_DMA_DMA_RXIMR_CPTx (value) (((( 1 << 2) - 1) & (value)) << 2) #define INCA_IP_DMA_DMA_RXIMR_HLDx (value) (((( 1 << 2) - 1) & (value)) << 0) - + /***DMA First Receive Descriptor Addr. for Rx Channel 0 ***/ #define INCA_IP_DMA_DMA_RXFRDA0 ((volatile u32*)(INCA_IP_DMA+ 0x0810)) #define INCA_IP_DMA_DMA_RXFRDA0_RXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0) - + /***DMA First Receive Descriptor Addr. for Rx Channel 1 ***/ #define INCA_IP_DMA_DMA_RXFRDA1 ((volatile u32*)(INCA_IP_DMA+ 0x0814)) #define INCA_IP_DMA_DMA_RXFRDA1_RXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0) - -/***DMA Receive Channel Polling Time***/ + +/***DMA Receive Channel Polling Time***/ #define INCA_IP_DMA_DMA_RXPOLL ((volatile u32*)(INCA_IP_DMA+ 0x0818)) #define INCA_IP_DMA_DMA_RXPOLL_BSZ1 (value) (((( 1 << 2) - 1) & (value)) << 30) #define INCA_IP_DMA_DMA_RXPOLL_BSZ0 (value) (((( 1 << 2) - 1) & (value)) << 28) #define INCA_IP_DMA_DMA_RXPOLL_RXPOLLTIME (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***DMA TX Channel 0 Command Register (Voice Port)***/ + +/***DMA TX Channel 0 Command Register (Voice Port)***/ #define INCA_IP_DMA_DMA_TXCCR0 ((volatile u32*)(INCA_IP_DMA+ 0x0880)) #define INCA_IP_DMA_DMA_TXCCR0_LBE (1 << 31) #define INCA_IP_DMA_DMA_TXCCR0_HPEN (1 << 30) #define INCA_IP_DMA_DMA_TXCCR0_HR (1 << 2) #define INCA_IP_DMA_DMA_TXCCR0_OFF (1 << 1) #define INCA_IP_DMA_DMA_TXCCR0_INIT (1 << 0) - -/***DMA TX Channel 1 Command Register (Mangmt Port)***/ + +/***DMA TX Channel 1 Command Register (Mangmt Port)***/ #define INCA_IP_DMA_DMA_TXCCR1 ((volatile u32*)(INCA_IP_DMA+ 0x0884)) #define INCA_IP_DMA_DMA_TXCCR1_LBE (1 << 31) #define INCA_IP_DMA_DMA_TXCCR1_HPEN (1 << 30) #define INCA_IP_DMA_DMA_TXCCR1_HR (1 << 2) #define INCA_IP_DMA_DMA_TXCCR1_OFF (1 << 1) #define INCA_IP_DMA_DMA_TXCCR1_INIT (1 << 0) - -/***DMA TX Channel 2 Command Register (SSC Port)***/ + +/***DMA TX Channel 2 Command Register (SSC Port)***/ #define INCA_IP_DMA_DMA_TXCCR2 ((volatile u32*)(INCA_IP_DMA+ 0x0888)) #define INCA_IP_DMA_DMA_TXCCR2_LBE (1 << 31) #define INCA_IP_DMA_DMA_TXCCR2_HPEN (1 << 30) @@ -1699,60 +1699,60 @@ If set and clear bit are written concurrently with 1, the associated bit is not #define INCA_IP_DMA_DMA_TXCCR2_HR (1 << 2) #define INCA_IP_DMA_DMA_TXCCR2_OFF (1 << 1) #define INCA_IP_DMA_DMA_TXCCR2_INIT (1 << 0) - + /***DMA First Receive Descriptor Addr. for Tx Channel 0 ***/ #define INCA_IP_DMA_DMA_TXFRDA0 ((volatile u32*)(INCA_IP_DMA+ 0x08A0)) #define INCA_IP_DMA_DMA_TXFRDA0_TXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0) - + /***DMA First Receive Descriptor Addr. for Tx Channel 1 ***/ #define INCA_IP_DMA_DMA_TXFRDA1 ((volatile u32*)(INCA_IP_DMA+ 0x08A4)) #define INCA_IP_DMA_DMA_TXFRDA1_TXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0) - + /***DMA First Receive Descriptor Addr. for Tx Channel 2 ***/ #define INCA_IP_DMA_DMA_TXFRDA2 ((volatile u32*)(INCA_IP_DMA+ 0x08A8)) #define INCA_IP_DMA_DMA_TXFRDA2_TXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0) - -/***DMA Transmit Channel Arbitration Register***/ + +/***DMA Transmit Channel Arbitration Register***/ #define INCA_IP_DMA_DMA_TXWGT ((volatile u32*)(INCA_IP_DMA+ 0x08C0)) #define INCA_IP_DMA_DMA_TXWGT_TX2PR (value) (((( 1 << 2) - 1) & (value)) << 4) #define INCA_IP_DMA_DMA_TXWGT_TX1PRI (value) (((( 1 << 2) - 1) & (value)) << 2) #define INCA_IP_DMA_DMA_TXWGT_TX0PRI (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***DMA Transmit Channel Polling Time***/ + +/***DMA Transmit Channel Polling Time***/ #define INCA_IP_DMA_DMA_TXPOLL ((volatile u32*)(INCA_IP_DMA+ 0x08C4)) #define INCA_IP_DMA_DMA_TXPOLL_BSZ2 (value) (((( 1 << 2) - 1) & (value)) << 30) #define INCA_IP_DMA_DMA_TXPOLL_BSZ1 (value) (((( 1 << 2) - 1) & (value)) << 28) #define INCA_IP_DMA_DMA_TXPOLL_BSZ0 (value) (((( 1 << 2) - 1) & (value)) << 26) #define INCA_IP_DMA_DMA_TXPOLL_TXPOLLTIME (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***DMA Transmit Interrupt Status Register***/ + +/***DMA Transmit Interrupt Status Register***/ #define INCA_IP_DMA_DMA_TXISR ((volatile u32*)(INCA_IP_DMA+ 0x08C8)) #define INCA_IP_DMA_DMA_TXISR_RDERRx (value) (((( 1 << 3) - 1) & (value)) << 12) #define INCA_IP_DMA_DMA_TXISR_HLDx (value) (((( 1 << 3) - 1) & (value)) << 9) #define INCA_IP_DMA_DMA_TXISR_CPTx (value) (((( 1 << 3) - 1) & (value)) << 6) #define INCA_IP_DMA_DMA_TXISR_EOPx (value) (((( 1 << 3) - 1) & (value)) << 3) #define INCA_IP_DMA_DMA_TXISR_CMDCPTx (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***DMA Transmit Interrupt Mask Register***/ + +/***DMA Transmit Interrupt Mask Register***/ #define INCA_IP_DMA_DMA_TXIMR ((volatile u32*)(INCA_IP_DMA+ 0x08CC)) #define INCA_IP_DMA_DMA_TXIMR_RDERRx (value) (((( 1 << 3) - 1) & (value)) << 12) #define INCA_IP_DMA_DMA_TXIMR_HLDx (value) (((( 1 << 3) - 1) & (value)) << 9) #define INCA_IP_DMA_DMA_TXIMR_CPTx (value) (((( 1 << 3) - 1) & (value)) << 6) #define INCA_IP_DMA_DMA_TXIMR_EOPx (value) (((( 1 << 3) - 1) & (value)) << 3) -#define INCA_IP_DMA_DMA_TXIMR_CMDCPTx (value) (((( 1 << 3) - 1) & (value)) << 0) - +#define INCA_IP_DMA_DMA_TXIMR_CMDCPTx (value) (((( 1 << 3) - 1) & (value)) << 0) + /***********************************************************************/ /* Module : Debug register address and bits */ /***********************************************************************/ - + #define INCA_IP_Debug (0xBF106000) -/***********************************************************************/ +/***********************************************************************/ + - -/***MCD Break Bus Switch Register***/ +/***MCD Break Bus Switch Register***/ #define INCA_IP_Debug_MCD_BBS ((volatile u32*)(INCA_IP_Debug+ 0x0000)) #define INCA_IP_Debug_MCD_BBS_BTP1 (1 << 19) #define INCA_IP_Debug_MCD_BBS_BTP0 (1 << 18) @@ -1766,48 +1766,48 @@ If set and clear bit are written concurrently with 1, the associated bit is not #define INCA_IP_Debug_MCD_BBS_BS4EN (1 << 6) #define INCA_IP_Debug_MCD_BBS_BS5 (1 << 5) #define INCA_IP_Debug_MCD_BBS_BS4 (1 << 4) - -/***MCD Multiplexer Control Register***/ + +/***MCD Multiplexer Control Register***/ #define INCA_IP_Debug_MCD_MCR ((volatile u32*)(INCA_IP_Debug+ 0x0008)) #define INCA_IP_Debug_MCD_MCR_MUX5 (1 << 4) #define INCA_IP_Debug_MCD_MCR_MUX4 (1 << 3) -#define INCA_IP_Debug_MCD_MCR_MUX1 (1 << 0) - +#define INCA_IP_Debug_MCD_MCR_MUX1 (1 << 0) + /***********************************************************************/ /* Module : TSF register address and bits */ /***********************************************************************/ - + #define INCA_IP_TSF (0xB8000900) -/***********************************************************************/ +/***********************************************************************/ + - -/***TSF Configuration Register (0000H)***/ +/***TSF Configuration Register (0000H)***/ #define INCA_IP_TSF_TSF_CONF ((volatile u32*)(INCA_IP_TSF+ 0x0000)) #define INCA_IP_TSF_TSF_CONF_PWMEN (1 << 2) #define INCA_IP_TSF_TSF_CONF_LEDEN (1 << 1) #define INCA_IP_TSF_TSF_CONF_KEYEN (1 << 0) - -/***Key scan Configuration Register (0004H)***/ + +/***Key scan Configuration Register (0004H)***/ #define INCA_IP_TSF_KEY_CONF ((volatile u32*)(INCA_IP_TSF+ 0x0004)) #define INCA_IP_TSF_KEY_CONF_SL (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Scan Register Line 0 and 1 (0008H)***/ + +/***Scan Register Line 0 and 1 (0008H)***/ #define INCA_IP_TSF_SREG01 ((volatile u32*)(INCA_IP_TSF+ 0x0008)) #define INCA_IP_TSF_SREG01_RES1x (value) (((( 1 << 12) - 1) & (value)) << 16) #define INCA_IP_TSF_SREG01_RES0x (value) (((( 1 << 13) - 1) & (value)) << 0) - -/***Scan Register Line 2 and 3 (000CH)***/ + +/***Scan Register Line 2 and 3 (000CH)***/ #define INCA_IP_TSF_SREG23 ((volatile u32*)(INCA_IP_TSF+ 0x000C)) #define INCA_IP_TSF_SREG23_RES3x (value) (((( 1 << 10) - 1) & (value)) << 16) #define INCA_IP_TSF_SREG23_RES2x (value) (((( 1 << 11) - 1) & (value)) << 0) - -/***Scan Register Line 4, 5 and 6 (0010H)***/ + +/***Scan Register Line 4, 5 and 6 (0010H)***/ #define INCA_IP_TSF_SREG456 ((volatile u32*)(INCA_IP_TSF+ 0x0010)) #define INCA_IP_TSF_SREG456_RES6x (value) (((( 1 << 7) - 1) & (value)) << 24) #define INCA_IP_TSF_SREG456_RES5x (value) (((( 1 << 8) - 1) & (value)) << 16) #define INCA_IP_TSF_SREG456_RES4x (value) (((( 1 << 9) - 1) & (value)) << 0) - -/***Scan Register Line 7 to 12 (0014H)***/ + +/***Scan Register Line 7 to 12 (0014H)***/ #define INCA_IP_TSF_SREG7to12 ((volatile u32*)(INCA_IP_TSF+ 0x0014)) #define INCA_IP_TSF_SREG7to12_RES12x (1 << 28) #define INCA_IP_TSF_SREG7to12_RES11x (value) (((( 1 << 2) - 1) & (value)) << 24) @@ -1815,8 +1815,8 @@ If set and clear bit are written concurrently with 1, the associated bit is not #define INCA_IP_TSF_SREG7to12_RES9x (value) (((( 1 << 4) - 1) & (value)) << 16) #define INCA_IP_TSF_SREG7to12_RES8x (value) (((( 1 << 5) - 1) & (value)) << 8) #define INCA_IP_TSF_SREG7to12_RES7x (value) (((( 1 << 6) - 1) & (value)) << 0) - -/***LEDMUX Configuration Register (0018H)***/ + +/***LEDMUX Configuration Register (0018H)***/ #define INCA_IP_TSF_LEDMUX_CONF ((volatile u32*)(INCA_IP_TSF+ 0x0018)) #define INCA_IP_TSF_LEDMUX_CONF_ETL1 (1 << 25) #define INCA_IP_TSF_LEDMUX_CONF_ESTA1 (1 << 24) @@ -1830,194 +1830,194 @@ If set and clear bit are written concurrently with 1, the associated bit is not #define INCA_IP_TSF_LEDMUX_CONF_ESPD0 (1 << 16) #define INCA_IP_TSF_LEDMUX_CONF_INV (1 << 1) #define INCA_IP_TSF_LEDMUX_CONF_NCOL (1 << 0) - -/***LED Register (001CH)***/ + +/***LED Register (001CH)***/ #define INCA_IP_TSF_LED_REG ((volatile u32*)(INCA_IP_TSF+ 0x001C)) #define INCA_IP_TSF_LED_REG_Lxy (value) (((( 1 << 24) - 1) & (value)) << 0) - -/***Pulse Width Modulator 1 and 2 Register (0020H)***/ + +/***Pulse Width Modulator 1 and 2 Register (0020H)***/ #define INCA_IP_TSF_PWM12 ((volatile u32*)(INCA_IP_TSF+ 0x0020)) -#define INCA_IP_TSF_PWM12_PW2PW1 (value) (((( 1 << NaN) - 1) & (value)) << NaN) - +#define INCA_IP_TSF_PWM12_PW2PW1 (value) (((( 1 << NaN) - 1) & (value)) << NaN) + /***********************************************************************/ /* Module : Ports register address and bits */ /***********************************************************************/ - + #define INCA_IP_Ports (0xB8000A00) -/***********************************************************************/ +/***********************************************************************/ - -/***Port 1 Data Output Register (0020H)***/ + +/***Port 1 Data Output Register (0020H)***/ #define INCA_IP_Ports_P1_OUT ((volatile u32*)(INCA_IP_Ports+ 0x0020)) #define INCA_IP_Ports_P1_OUT_P(value) (1 << value) - - -/***Port 2 Data Output Register (0040H)***/ + + +/***Port 2 Data Output Register (0040H)***/ #define INCA_IP_Ports_P2_OUT ((volatile u32*)(INCA_IP_Ports+ 0x0040)) #define INCA_IP_Ports_P2_OUT_P(value) (1 << value) - - -/***Port 1 Data Input Register (0024H)***/ + + +/***Port 1 Data Input Register (0024H)***/ #define INCA_IP_Ports_P1_IN ((volatile u32*)(INCA_IP_Ports+ 0x0024)) #define INCA_IP_Ports_P1_IN_P(value) (1 << value) - - -/***Port 2 Data Input Register (0044H)***/ + + +/***Port 2 Data Input Register (0044H)***/ #define INCA_IP_Ports_P2_IN ((volatile u32*)(INCA_IP_Ports+ 0x0044)) #define INCA_IP_Ports_P2_IN_P(value) (1 << value) - - -/***Port 1 Direction Register (0028H)***/ + + +/***Port 1 Direction Register (0028H)***/ #define INCA_IP_Ports_P1_DIR ((volatile u32*)(INCA_IP_Ports+ 0x0028)) #define INCA_IP_Ports_P1_DIR_Port1P(value) (1 << value) - + #define INCA_IP_Ports_P1_DIR_Port2Pn (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***Port 2 Direction Register (0048H)***/ + +/***Port 2 Direction Register (0048H)***/ #define INCA_IP_Ports_P2_DIR ((volatile u32*)(INCA_IP_Ports+ 0x0048)) #define INCA_IP_Ports_P2_DIR_Port1P(value) (1 << value) - + #define INCA_IP_Ports_P2_DIR_Port2Pn (value) (((( 1 << 16) - 1) & (value)) << 0) - + /***Port 0 Alternate Function Select Register 0 (000C H) ***/ #define INCA_IP_Ports_P0_ALTSEL ((volatile u32*)(INCA_IP_Ports+ 0x000C)) #define INCA_IP_Ports_P0_ALTSEL_Port0P(value) (1 << value) - - + + /***Port 1 Alternate Function Select Register 0 (002C H) ***/ #define INCA_IP_Ports_P1_ALTSEL ((volatile u32*)(INCA_IP_Ports+ 0x002C)) #define INCA_IP_Ports_P1_ALTSEL_Port1P(value) (1 << value) - + #define INCA_IP_Ports_P1_ALTSEL_Port2P(value) (1 << value) - - + + /***Port 2 Alternate Function Select Register 0 (004C H) ***/ #define INCA_IP_Ports_P2_ALTSEL ((volatile u32*)(INCA_IP_Ports+ 0x004C)) #define INCA_IP_Ports_P2_ALTSEL_Port1P(value) (1 << value) - + #define INCA_IP_Ports_P2_ALTSEL_Port2P(value) (1 << value) - - + + /***Port 0 Input Schmitt-Trigger Off Register (0010 H) ***/ #define INCA_IP_Ports_P0_STOFF ((volatile u32*)(INCA_IP_Ports+ 0x0010)) #define INCA_IP_Ports_P0_STOFF_Port0P(value) (1 << value) - - + + /***Port 1 Input Schmitt-Trigger Off Register (0030 H) ***/ #define INCA_IP_Ports_P1_STOFF ((volatile u32*)(INCA_IP_Ports+ 0x0030)) #define INCA_IP_Ports_P1_STOFF_Port1P(value) (1 << value) - + #define INCA_IP_Ports_P1_STOFF_Port2P(value) (1 << value) - - + + /***Port 2 Input Schmitt-Trigger Off Register (0050 H) ***/ #define INCA_IP_Ports_P2_STOFF ((volatile u32*)(INCA_IP_Ports+ 0x0050)) #define INCA_IP_Ports_P2_STOFF_Port1P(value) (1 << value) - + #define INCA_IP_Ports_P2_STOFF_Port2P(value) (1 << value) - - -/***Port 2 Open Drain Control Register (0054H)***/ + + +/***Port 2 Open Drain Control Register (0054H)***/ #define INCA_IP_Ports_P2_OD ((volatile u32*)(INCA_IP_Ports+ 0x0054)) #define INCA_IP_Ports_P2_OD_Port2P(value) (1 << value) - - -/***Port 0 Pull Up Device Enable Register (0018 H)***/ + + +/***Port 0 Pull Up Device Enable Register (0018 H)***/ #define INCA_IP_Ports_P0_PUDEN ((volatile u32*)(INCA_IP_Ports+ 0x0018)) #define INCA_IP_Ports_P0_PUDEN_Port0P(value) (1 << value) - - -/***Port 2 Pull Up Device Enable Register (0058 H)***/ + + +/***Port 2 Pull Up Device Enable Register (0058 H)***/ #define INCA_IP_Ports_P2_PUDEN ((volatile u32*)(INCA_IP_Ports+ 0x0058)) #define INCA_IP_Ports_P2_PUDEN_Port2P(value) (1 << value) - + #define INCA_IP_Ports_P2_PUDEN_Port2P(value) (1 << value) - - -/***Port 0 Pull Up/Pull Down Select Register (001C H)***/ + + +/***Port 0 Pull Up/Pull Down Select Register (001C H)***/ #define INCA_IP_Ports_P0_PUDSEL ((volatile u32*)(INCA_IP_Ports+ 0x001C)) #define INCA_IP_Ports_P0_PUDSEL_Port0P(value) (1 << value) - - -/***Port 2 Pull Up/Pull Down Select Register (005C H)***/ + + +/***Port 2 Pull Up/Pull Down Select Register (005C H)***/ #define INCA_IP_Ports_P2_PUDSEL ((volatile u32*)(INCA_IP_Ports+ 0x005C)) #define INCA_IP_Ports_P2_PUDSEL_Port2P(value) (1 << value) - + #define INCA_IP_Ports_P2_PUDSEL_Port2P(value) (1 << value) - - + + /***********************************************************************/ /* Module : DES/3DES register address and bits */ /***********************************************************************/ - + #define INCA_IP_DES_3DES (0xB8000800) -/***********************************************************************/ +/***********************************************************************/ + - -/***DES Input Data High Register***/ +/***DES Input Data High Register***/ #define INCA_IP_DES_3DES_DES_IHR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0000)) #define INCA_IP_DES_3DES_DES_IHR_IH(value) (1 << value) - - -/***DES Input Data Low Register***/ + + +/***DES Input Data Low Register***/ #define INCA_IP_DES_3DES_DES_ILR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0004)) #define INCA_IP_DES_3DES_DES_ILR_IL(value) (1 << value) - - -/***DES Key #1 High Register***/ + + +/***DES Key #1 High Register***/ #define INCA_IP_DES_3DES_DES_K1HR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0008)) #define INCA_IP_DES_3DES_DES_K1HR_K1H(value) (1 << value) - - -/***DES Key #1 Low Register***/ + + +/***DES Key #1 Low Register***/ #define INCA_IP_DES_3DES_DES_K1LR ((volatile u32*)(INCA_IP_DES_3DES+ 0x000C)) #define INCA_IP_DES_3DES_DES_K1LR_K1L(value) (1 << value) - - -/***DES Key #2 High Register***/ + + +/***DES Key #2 High Register***/ #define INCA_IP_DES_3DES_DES_K2HR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0010)) #define INCA_IP_DES_3DES_DES_K2HR_K2H(value) (1 << value) - - -/***DES Key #2 Low Register***/ + + +/***DES Key #2 Low Register***/ #define INCA_IP_DES_3DES_DES_K2LR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0014)) #define INCA_IP_DES_3DES_DES_K2LR_K2L(value) (1 << value) - - -/***DES Key #3 High Register***/ + + +/***DES Key #3 High Register***/ #define INCA_IP_DES_3DES_DES_K3HR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0018)) #define INCA_IP_DES_3DES_DES_K3HR_K3H(value) (1 << value) - - -/***DES Key #3 Low Register***/ + + +/***DES Key #3 Low Register***/ #define INCA_IP_DES_3DES_DES_K3LR ((volatile u32*)(INCA_IP_DES_3DES+ 0x001C)) #define INCA_IP_DES_3DES_DES_K3LR_K3L(value) (1 << value) - - -/***DES Initialization Vector High Register***/ + + +/***DES Initialization Vector High Register***/ #define INCA_IP_DES_3DES_DES_IVHR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0020)) #define INCA_IP_DES_3DES_DES_IVHR_IVH(value) (1 << value) - - -/***DES Initialization Vector Low Register***/ + + +/***DES Initialization Vector Low Register***/ #define INCA_IP_DES_3DES_DES_IVLR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0024)) #define INCA_IP_DES_3DES_DES_IVLR_IVL(value) (1 << value) - - -/***DES Control Register***/ + + +/***DES Control Register***/ #define INCA_IP_DES_3DES_DES_CONTROLR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0028)) #define INCA_IP_DES_3DES_DES_CONTROLR_KRE (1 << 31) #define INCA_IP_DES_3DES_DES_CONTROLR_DAU (1 << 16) #define INCA_IP_DES_3DES_DES_CONTROLR_F(value) (1 << value) - + #define INCA_IP_DES_3DES_DES_CONTROLR_O(value) (1 << value) - + #define INCA_IP_DES_3DES_DES_CONTROLR_GO (1 << 8) #define INCA_IP_DES_3DES_DES_CONTROLR_STP (1 << 7) #define INCA_IP_DES_3DES_DES_CONTROLR_IEN (1 << 6) @@ -2025,134 +2025,134 @@ If set and clear bit are written concurrently with 1, the associated bit is not #define INCA_IP_DES_3DES_DES_CONTROLR_SM (1 << 4) #define INCA_IP_DES_3DES_DES_CONTROLR_E_D (1 << 3) #define INCA_IP_DES_3DES_DES_CONTROLR_M(value) (1 << value) - - -/***DES Output Data High Register***/ + + +/***DES Output Data High Register***/ #define INCA_IP_DES_3DES_DES_OHR ((volatile u32*)(INCA_IP_DES_3DES+ 0x002C)) #define INCA_IP_DES_3DES_DES_OHR_OH(value) (1 << value) - - -/***DES Output Data Low Register***/ + + +/***DES Output Data Low Register***/ #define INCA_IP_DES_3DES_DES_OLR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0030)) #define INCA_IP_DES_3DES_DES_OLR_OL(value) (1 << value) - - + + /***********************************************************************/ /* Module : AES register address and bits */ /***********************************************************************/ - + #define INCA_IP_AES (0xB8000880) -/***********************************************************************/ +/***********************************************************************/ + - -/***AES Input Data 3 Register***/ +/***AES Input Data 3 Register***/ #define INCA_IP_AES_AES_ID3R ((volatile u32*)(INCA_IP_AES+ 0x0000)) #define INCA_IP_AES_AES_ID3R_I(value) (1 << value) - - -/***AES Input Data 2 Register***/ + + +/***AES Input Data 2 Register***/ #define INCA_IP_AES_AES_ID2R ((volatile u32*)(INCA_IP_AES+ 0x0000)) #define INCA_IP_AES_AES_ID2R_I(value) (1 << value) - - -/***AES Input Data 1 Register***/ + + +/***AES Input Data 1 Register***/ #define INCA_IP_AES_AES_ID1R ((volatile u32*)(INCA_IP_AES+ 0x0000)) #define INCA_IP_AES_AES_ID1R_I(value) (1 << value) - - -/***AES Input Data 0 Register***/ + + +/***AES Input Data 0 Register***/ #define INCA_IP_AES_AES_ID0R ((volatile u32*)(INCA_IP_AES+ 0x0000)) #define INCA_IP_AES_AES_ID0R_I(value) (1 << value) - - -/***AES Output Data 3 Register***/ + + +/***AES Output Data 3 Register***/ #define INCA_IP_AES_AES_OD3R ((volatile u32*)(INCA_IP_AES+ 0x0000)) #define INCA_IP_AES_AES_OD3R_O(value) (1 << value) - - -/***AES Output Data 2 Register***/ + + +/***AES Output Data 2 Register***/ #define INCA_IP_AES_AES_OD2R ((volatile u32*)(INCA_IP_AES+ 0x0000)) #define INCA_IP_AES_AES_OD2R_O(value) (1 << value) - - -/***AES Output Data 1 Register***/ + + +/***AES Output Data 1 Register***/ #define INCA_IP_AES_AES_OD1R ((volatile u32*)(INCA_IP_AES+ 0x0000)) #define INCA_IP_AES_AES_OD1R_O(value) (1 << value) - - -/***AES Output Data 0 Register***/ + + +/***AES Output Data 0 Register***/ #define INCA_IP_AES_AES_OD0R ((volatile u32*)(INCA_IP_AES+ 0x0000)) #define INCA_IP_AES_AES_OD0R_O(value) (1 << value) - - -/***AES Key 7 Register***/ + + +/***AES Key 7 Register***/ #define INCA_IP_AES_AES_K7R ((volatile u32*)(INCA_IP_AES+ 0x0000)) #define INCA_IP_AES_AES_K7R_K(value) (1 << value) - - -/***AES Key 6 Register***/ + + +/***AES Key 6 Register***/ #define INCA_IP_AES_AES_K6R ((volatile u32*)(INCA_IP_AES+ 0x0000)) #define INCA_IP_AES_AES_K6R_K(value) (1 << value) - - -/***AES Key 5 Register***/ + + +/***AES Key 5 Register***/ #define INCA_IP_AES_AES_K5R ((volatile u32*)(INCA_IP_AES+ 0x0000)) #define INCA_IP_AES_AES_K5R_K(value) (1 << value) - - -/***AES Key 4 Register***/ + + +/***AES Key 4 Register***/ #define INCA_IP_AES_AES_K4R ((volatile u32*)(INCA_IP_AES+ 0x0000)) #define INCA_IP_AES_AES_K4R_K(value) (1 << value) - - -/***AES Key 3 Register***/ + + +/***AES Key 3 Register***/ #define INCA_IP_AES_AES_K3R ((volatile u32*)(INCA_IP_AES+ 0x0000)) #define INCA_IP_AES_AES_K3R_K(value) (1 << value) - - -/***AES Key 2 Register***/ + + +/***AES Key 2 Register***/ #define INCA_IP_AES_AES_K2R ((volatile u32*)(INCA_IP_AES+ 0x0000)) #define INCA_IP_AES_AES_K2R_K(value) (1 << value) - - -/***AES Key 1 Register***/ + + +/***AES Key 1 Register***/ #define INCA_IP_AES_AES_K1R ((volatile u32*)(INCA_IP_AES+ 0x0000)) #define INCA_IP_AES_AES_K1R_K(value) (1 << value) - - -/***AES Key 0 Register***/ + + +/***AES Key 0 Register***/ #define INCA_IP_AES_AES_K0R ((volatile u32*)(INCA_IP_AES+ 0x0000)) #define INCA_IP_AES_AES_K0R_K(value) (1 << value) - - -/***AES Initialization Vector 3 Register***/ + + +/***AES Initialization Vector 3 Register***/ #define INCA_IP_AES_AES_IV3R ((volatile u32*)(INCA_IP_AES+ 0x0000)) #define INCA_IP_AES_AES_IV3R_IV(value) (1 << value) - - -/***AES Initialization Vector 2 Register***/ + + +/***AES Initialization Vector 2 Register***/ #define INCA_IP_AES_AES_IV2R ((volatile u32*)(INCA_IP_AES+ 0x0000)) #define INCA_IP_AES_AES_IV2R_IV(value) (1 << value) - - -/***AES Initialization Vector 1 Register***/ + + +/***AES Initialization Vector 1 Register***/ #define INCA_IP_AES_AES_IV1R ((volatile u32*)(INCA_IP_AES+ 0x0000)) #define INCA_IP_AES_AES_IV1R_IV(value) (1 << value) - - -/***AES Initialization Vector 0 Register***/ + + +/***AES Initialization Vector 0 Register***/ #define INCA_IP_AES_AES_IV0R ((volatile u32*)(INCA_IP_AES+ 0x0000)) #define INCA_IP_AES_AES_IV0R_IV (value) (((( 1 << 32) - 1) &(value)) << 0) - -/***AES Control Register***/ + +/***AES Control Register***/ #define INCA_IP_AES_AES_CONTROLR ((volatile u32*)(INCA_IP_AES+ 0x0000)) #define INCA_IP_AES_AES_CONTROLR_KRE (1 << 31) #define INCA_IP_AES_AES_CONTROLR_DAU (1 << 16) #define INCA_IP_AES_AES_CONTROLR_PNK (1 << 15) #define INCA_IP_AES_AES_CONTROLR_F(value) (1 << value) - + #define INCA_IP_AES_AES_CONTROLR_O(value) (1 << value) - + #define INCA_IP_AES_AES_CONTROLR_GO (1 << 8) #define INCA_IP_AES_AES_CONTROLR_STP (1 << 7) #define INCA_IP_AES_AES_CONTROLR_IEN (1 << 6) @@ -2161,30 +2161,30 @@ If set and clear bit are written concurrently with 1, the associated bit is not #define INCA_IP_AES_AES_CONTROLR_E_D (1 << 3) #define INCA_IP_AES_AES_CONTROLR_KV (1 << 2) #define INCA_IP_AES_AES_CONTROLR_K(value) (1 << value) - - + + /***********************************************************************/ /* Module : I²C register address and bits */ /***********************************************************************/ - + #define INCA_IP_IIC (0xB8000700) -/***********************************************************************/ +/***********************************************************************/ - -/***I²C Port Input Select Register***/ + +/***I²C Port Input Select Register***/ #define INCA_IP_IIC_IIC_PISEL ((volatile u32*)(INCA_IP_IIC+ 0x0004)) #define INCA_IP_IIC_IIC_PISEL_SDAIS(value) (1 << value) - + #define INCA_IP_IIC_IIC_PISEL_SCLIS(value) (1 << value) - - -/***I²C Clock Control Register***/ + + +/***I²C Clock Control Register***/ #define INCA_IP_IIC_IIC_CLC ((volatile u32*)(INCA_IP_IIC+ 0x0000)) #define INCA_IP_IIC_IIC_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) #define INCA_IP_IIC_IIC_CLC_DISS (1 << 1) #define INCA_IP_IIC_IIC_CLC_DISR (1 << 0) - -/***I²C System Control Register***/ + +/***I²C System Control Register***/ #define INCA_IP_IIC_IIC_SYSCON_0 ((volatile u32*)(INCA_IP_IIC+ 0x0010)) #define INCA_IP_IIC_IIC_SYSCON_0_WMEN (1 << 31) #define INCA_IP_IIC_IIC_SYSCON_0_CI (value) (((( 1 << 2) - 1) & (value)) << 26) @@ -2207,8 +2207,8 @@ If set and clear bit are written concurrently with 1, the associated bit is not #define INCA_IP_IIC_IIC_SYSCON_0_SLA (1 << 2) #define INCA_IP_IIC_IIC_SYSCON_0_AL (1 << 1) #define INCA_IP_IIC_IIC_SYSCON_0_ADR (1 << 0) - -/***I²C System Control Register***/ + +/***I²C System Control Register***/ #define INCA_IP_IIC_IIC_SYSCON_1 ((volatile u32*)(INCA_IP_IIC+ 0x0010)) #define INCA_IP_IIC_IIC_SYSCON_1_RM (value) (((( 1 << 8) - 1) & (value)) << 24) #define INCA_IP_IIC_IIC_SYSCON_1_TRX (1 << 23) @@ -2228,8 +2228,8 @@ If set and clear bit are written concurrently with 1, the associated bit is not #define INCA_IP_IIC_IIC_SYSCON_1_SLA (1 << 2) #define INCA_IP_IIC_IIC_SYSCON_1_AL (1 << 1) #define INCA_IP_IIC_IIC_SYSCON_1_ADR (1 << 0) - -/***I²C System Control Register***/ + +/***I²C System Control Register***/ #define INCA_IP_IIC_IIC_SYSCON_2 ((volatile u32*)(INCA_IP_IIC+ 0x0010)) #define INCA_IP_IIC_IIC_SYSCON_2_WMEN (1 << 31) #define INCA_IP_IIC_IIC_SYSCON_2_CI (value) (((( 1 << 2) - 1) & (value)) << 26) @@ -2251,7 +2251,7 @@ If set and clear bit are written concurrently with 1, the associated bit is not #define INCA_IP_IIC_IIC_SYSCON_2_SLA (1 << 2) #define INCA_IP_IIC_IIC_SYSCON_2_AL (1 << 1) #define INCA_IP_IIC_IIC_SYSCON_2_ADR (1 << 0) - + /***I²C Write Hardware Modified System Control Register ***/ #define INCA_IP_IIC_IIC_WHBSYSCON ((volatile u32*)(INCA_IP_IIC+ 0x0020)) @@ -2277,161 +2277,161 @@ If set and clear bit are written concurrently with 1, the associated bit is not #define INCA_IP_IIC_IIC_WHBSYSCON_CLRIRQD (1 << 5) #define INCA_IP_IIC_IIC_WHBSYSCON_SETAL (1 << 2) #define INCA_IP_IIC_IIC_WHBSYSCON_CLRAL (1 << 1) - -/***I²C Bus Control Register***/ + +/***I²C Bus Control Register***/ #define INCA_IP_IIC_IIC_BUSCON_0 ((volatile u32*)(INCA_IP_IIC+ 0x0014)) #define INCA_IP_IIC_IIC_BUSCON_0_BRPMOD (1 << 31) #define INCA_IP_IIC_IIC_BUSCON_0_PREDIV (value) (((( 1 << 2) - 1) & (value)) << 29) #define INCA_IP_IIC_IIC_BUSCON_0_ICA9_0 (value) (((( 1 << 10) - 1) & (value)) << 16) #define INCA_IP_IIC_IIC_BUSCON_0_BRP (value) (((( 1 << 8) - 1) & (value)) << 8) #define INCA_IP_IIC_IIC_BUSCON_0_SCLEN(value) (1 << value) - + #define INCA_IP_IIC_IIC_BUSCON_0_SDAEN(value) (1 << value) - - -/***I²C Bus Control Register***/ + + +/***I²C Bus Control Register***/ #define INCA_IP_IIC_IIC_BUSCON_1 ((volatile u32*)(INCA_IP_IIC+ 0x0014)) #define INCA_IP_IIC_IIC_BUSCON_1_BRPMOD (1 << 31) #define INCA_IP_IIC_IIC_BUSCON_1_PREDIV (value) (((( 1 << 2) - 1) & (value)) << 29) #define INCA_IP_IIC_IIC_BUSCON_1_ICA7_1 (value) (((( 1 << 7) - 1) & (value)) << 17) #define INCA_IP_IIC_IIC_BUSCON_1_BRP (value) (((( 1 << 8) - 1) & (value)) << 8) #define INCA_IP_IIC_IIC_BUSCON_1_SCLEN(value) (1 << value) - + #define INCA_IP_IIC_IIC_BUSCON_1_SDAEN(value) (1 << value) - - -/***I²C Receive Transmit Buffer***/ + + +/***I²C Receive Transmit Buffer***/ #define INCA_IP_IIC_IIC_RTB ((volatile u32*)(INCA_IP_IIC+ 0x0018)) #define INCA_IP_IIC_IIC_RTB_RTB(value) (1 << value) - - + + /***********************************************************************/ /* Module : FB register address and bits */ /***********************************************************************/ - + #define INCA_IP_FB (0xBF880000) -/***********************************************************************/ +/***********************************************************************/ - -/***FB Access Error Cause Register***/ + +/***FB Access Error Cause Register***/ #define INCA_IP_FB_FB_ERRCAUSE ((volatile u32*)(INCA_IP_FB+ 0x0100)) #define INCA_IP_FB_FB_ERRCAUSE_ERR (1 << 31) #define INCA_IP_FB_FB_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16) #define INCA_IP_FB_FB_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***FB Access Error Address Register***/ + +/***FB Access Error Address Register***/ #define INCA_IP_FB_FB_ERRADDR ((volatile u32*)(INCA_IP_FB+ 0x0108)) #define INCA_IP_FB_FB_ERRADDR_ADDR - -/***FB Configuration Register***/ + +/***FB Configuration Register***/ #define INCA_IP_FB_FB_CFG ((volatile u32*)(INCA_IP_FB+ 0x0800)) -#define INCA_IP_FB_FB_CFG_SVM (1 << 0) - +#define INCA_IP_FB_FB_CFG_SVM (1 << 0) + /***********************************************************************/ /* Module : SRAM register address and bits */ /***********************************************************************/ - + #define INCA_IP_SRAM (0xBF980000) -/***********************************************************************/ +/***********************************************************************/ - -/***SRAM Size Register***/ + +/***SRAM Size Register***/ #define INCA_IP_SRAM_SRAM_SIZE ((volatile u32*)(INCA_IP_SRAM+ 0x0800)) -#define INCA_IP_SRAM_SRAM_SIZE_SIZE (value) (((( 1 << 23) - 1) & (value)) << 0) - +#define INCA_IP_SRAM_SRAM_SIZE_SIZE (value) (((( 1 << 23) - 1) & (value)) << 0) + /***********************************************************************/ /* Module : BIU register address and bits */ /***********************************************************************/ - + #define INCA_IP_BIU (0xBFA80000) -/***********************************************************************/ +/***********************************************************************/ + - -/***BIU Identification Register***/ +/***BIU Identification Register***/ #define INCA_IP_BIU_BIU_ID ((volatile u32*)(INCA_IP_BIU+ 0x0000)) #define INCA_IP_BIU_BIU_ID_ARCH (1 << 16) #define INCA_IP_BIU_BIU_ID_ID (value) (((( 1 << 8) - 1) & (value)) << 8) #define INCA_IP_BIU_BIU_ID_REV (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***BIU Access Error Cause Register***/ + +/***BIU Access Error Cause Register***/ #define INCA_IP_BIU_BIU_ERRCAUSE ((volatile u32*)(INCA_IP_BIU+ 0x0100)) #define INCA_IP_BIU_BIU_ERRCAUSE_ERR (1 << 31) #define INCA_IP_BIU_BIU_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16) #define INCA_IP_BIU_BIU_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***BIU Access Error Address Register***/ + +/***BIU Access Error Address Register***/ #define INCA_IP_BIU_BIU_ERRADDR ((volatile u32*)(INCA_IP_BIU+ 0x0108)) -#define INCA_IP_BIU_BIU_ERRADDR_ADDR - +#define INCA_IP_BIU_BIU_ERRADDR_ADDR + /***********************************************************************/ /* Module : ICU register address and bits */ /***********************************************************************/ - + #define INCA_IP_ICU (0xBF101000) -/***********************************************************************/ +/***********************************************************************/ + - -/***IM0 Interrupt Status Register***/ +/***IM0 Interrupt Status Register***/ #define INCA_IP_ICU_IM0_ISR ((volatile u32*)(INCA_IP_ICU+ 0x0000)) #define INCA_IP_ICU_IM0_ISR_IR(value) (1 << value) - - -/***IM1 Interrupt Status Register***/ + + +/***IM1 Interrupt Status Register***/ #define INCA_IP_ICU_IM1_ISR ((volatile u32*)(INCA_IP_ICU+ 0x0200)) #define INCA_IP_ICU_IM1_ISR_IR(value) (1 << value) - - -/***IM2 Interrupt Status Register***/ + + +/***IM2 Interrupt Status Register***/ #define INCA_IP_ICU_IM2_ISR ((volatile u32*)(INCA_IP_ICU+ 0x0400)) #define INCA_IP_ICU_IM2_ISR_IR(value) (1 << value) - - -/***IM0 Interrupt Enable Register***/ + + +/***IM0 Interrupt Enable Register***/ #define INCA_IP_ICU_IM0_IER ((volatile u32*)(INCA_IP_ICU+ 0x0008)) #define INCA_IP_ICU_IM0_IER_IR(value) (1 << value) - - -/***IM1 Interrupt Enable Register***/ + + +/***IM1 Interrupt Enable Register***/ #define INCA_IP_ICU_IM1_IER ((volatile u32*)(INCA_IP_ICU+ 0x0208)) #define INCA_IP_ICU_IM1_IER_IR(value) (1 << value) - - -/***IM2 Interrupt Enable Register***/ + + +/***IM2 Interrupt Enable Register***/ #define INCA_IP_ICU_IM2_IER ((volatile u32*)(INCA_IP_ICU+ 0x0408)) #define INCA_IP_ICU_IM2_IER_IR(value) (1 << value) - - -/***IM0 Interrupt Output Status Register***/ + + +/***IM0 Interrupt Output Status Register***/ #define INCA_IP_ICU_IM0_IOSR ((volatile u32*)(INCA_IP_ICU+ 0x0010)) #define INCA_IP_ICU_IM0_IOSR_IR(value) (1 << value) - - -/***IM1 Interrupt Output Status Register***/ + + +/***IM1 Interrupt Output Status Register***/ #define INCA_IP_ICU_IM1_IOSR ((volatile u32*)(INCA_IP_ICU+ 0x0210)) #define INCA_IP_ICU_IM1_IOSR_IR(value) (1 << value) - - -/***IM2 Interrupt Output Status Register***/ + + +/***IM2 Interrupt Output Status Register***/ #define INCA_IP_ICU_IM2_IOSR ((volatile u32*)(INCA_IP_ICU+ 0x0410)) #define INCA_IP_ICU_IM2_IOSR_IR(value) (1 << value) - - -/***IM0 Interrupt Request Set Register***/ + + +/***IM0 Interrupt Request Set Register***/ #define INCA_IP_ICU_IM0_IRSR ((volatile u32*)(INCA_IP_ICU+ 0x0018)) #define INCA_IP_ICU_IM0_IRSR_IR(value) (1 << value) - - -/***IM1 Interrupt Request Set Register***/ + + +/***IM1 Interrupt Request Set Register***/ #define INCA_IP_ICU_IM1_IRSR ((volatile u32*)(INCA_IP_ICU+ 0x0218)) #define INCA_IP_ICU_IM1_IRSR_IR(value) (1 << value) - - -/***IM2 Interrupt Request Set Register***/ + + +/***IM2 Interrupt Request Set Register***/ #define INCA_IP_ICU_IM2_IRSR ((volatile u32*)(INCA_IP_ICU+ 0x0418)) #define INCA_IP_ICU_IM2_IRSR_IR(value) (1 << value) - - -/***External Interrupt Control Register***/ + + +/***External Interrupt Control Register***/ #define INCA_IP_ICU_ICU_EICR ((volatile u32*)(INCA_IP_ICU+ 0x0B00)) #define INCA_IP_ICU_ICU_EICR_EII5 (value) (((( 1 << 3) - 1) & (value)) << 20) #define INCA_IP_ICU_ICU_EICR_EII4 (value) (((( 1 << 3) - 1) & (value)) << 16) diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h index 9a7aaf7f4b5..857fb0302ce 100644 --- a/include/asm-mips/io.h +++ b/include/asm-mips/io.h @@ -203,7 +203,7 @@ extern void iounmap(void *addr); #define isa_eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(b),(c),(d)) static inline int check_signature(unsigned long io_addr, - const unsigned char *signature, int length) + const unsigned char *signature, int length) { int retval = 0; do { @@ -286,15 +286,15 @@ extern inline void __outs##s(unsigned int port, const void * addr, unsigned long #define __OUTS2(m) \ if (count) \ __asm__ __volatile__ ( \ - ".set\tnoreorder\n\t" \ - ".set\tnoat\n" \ - "1:\tl" #m "\t$1,(%0)\n\t" \ - "subu\t%1,1\n\t" \ - "s" #m "\t$1,%4(%5)\n\t" \ - "bne\t$0,%1,1b\n\t" \ - "addiu\t%0,%6\n\t" \ - ".set\tat\n\t" \ - ".set\treorder" + ".set\tnoreorder\n\t" \ + ".set\tnoat\n" \ + "1:\tl" #m "\t$1,(%0)\n\t" \ + "subu\t%1,1\n\t" \ + "s" #m "\t$1,%4(%5)\n\t" \ + "bne\t$0,%1,1b\n\t" \ + "addiu\t%0,%6\n\t" \ + ".set\tat\n\t" \ + ".set\treorder" #define __OUTS(m,s,i) \ __OUTS1(s) __OUTS2(m) \ diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h index 56fc3da7856..31007387517 100644 --- a/include/asm-mips/mipsregs.h +++ b/include/asm-mips/mipsregs.h @@ -75,7 +75,7 @@ #define CP0_IWATCH $18 #define CP0_DWATCH $19 -/* +/* * Coprocessor 0 Set 1 register names */ #define CP0_S1_DERRADDR0 $26 @@ -175,69 +175,69 @@ */ #define read_32bit_cp0_register(source) \ ({ int __res; \ - __asm__ __volatile__( \ + __asm__ __volatile__( \ ".set\tpush\n\t" \ ".set\treorder\n\t" \ - "mfc0\t%0,"STR(source)"\n\t" \ + "mfc0\t%0,"STR(source)"\n\t" \ ".set\tpop" \ - : "=r" (__res)); \ - __res;}) + : "=r" (__res)); \ + __res;}) #define read_32bit_cp0_set1_register(source) \ ({ int __res; \ - __asm__ __volatile__( \ + __asm__ __volatile__( \ ".set\tpush\n\t" \ ".set\treorder\n\t" \ - "cfc0\t%0,"STR(source)"\n\t" \ + "cfc0\t%0,"STR(source)"\n\t" \ ".set\tpop" \ - : "=r" (__res)); \ - __res;}) + : "=r" (__res)); \ + __res;}) /* * For now use this only with interrupts disabled! */ #define read_64bit_cp0_register(source) \ ({ int __res; \ - __asm__ __volatile__( \ - ".set\tmips3\n\t" \ - "dmfc0\t%0,"STR(source)"\n\t" \ - ".set\tmips0" \ - : "=r" (__res)); \ - __res;}) + __asm__ __volatile__( \ + ".set\tmips3\n\t" \ + "dmfc0\t%0,"STR(source)"\n\t" \ + ".set\tmips0" \ + : "=r" (__res)); \ + __res;}) #define write_32bit_cp0_register(register,value) \ - __asm__ __volatile__( \ - "mtc0\t%0,"STR(register)"\n\t" \ + __asm__ __volatile__( \ + "mtc0\t%0,"STR(register)"\n\t" \ "nop" \ - : : "r" (value)); + : : "r" (value)); #define write_32bit_cp0_set1_register(register,value) \ - __asm__ __volatile__( \ - "ctc0\t%0,"STR(register)"\n\t" \ + __asm__ __volatile__( \ + "ctc0\t%0,"STR(register)"\n\t" \ "nop" \ - : : "r" (value)); + : : "r" (value)); #define write_64bit_cp0_register(register,value) \ - __asm__ __volatile__( \ - ".set\tmips3\n\t" \ - "dmtc0\t%0,"STR(register)"\n\t" \ - ".set\tmips0" \ - : : "r" (value)) - -/* - * This should be changed when we get a compiler that support the MIPS32 ISA. + __asm__ __volatile__( \ + ".set\tmips3\n\t" \ + "dmtc0\t%0,"STR(register)"\n\t" \ + ".set\tmips0" \ + : : "r" (value)) + +/* + * This should be changed when we get a compiler that support the MIPS32 ISA. */ #define read_mips32_cp0_config1() \ ({ int __res; \ - __asm__ __volatile__( \ + __asm__ __volatile__( \ ".set\tnoreorder\n\t" \ ".set\tnoat\n\t" \ - ".word\t0x40018001\n\t" \ + ".word\t0x40018001\n\t" \ "move\t%0,$1\n\t" \ ".set\tat\n\t" \ ".set\treorder" \ :"=r" (__res)); \ - __res;}) + __res;}) /* * R4x00 interrupt enable / cause bits @@ -273,11 +273,11 @@ extern __inline__ unsigned int \ set_cp0_##name(unsigned int set) \ { \ unsigned int res; \ - \ + \ res = read_32bit_cp0_register(register); \ res |= set; \ write_32bit_cp0_register(register, res); \ - \ + \ return res; \ } \ \ @@ -285,11 +285,11 @@ extern __inline__ unsigned int \ clear_cp0_##name(unsigned int clear) \ { \ unsigned int res; \ - \ + \ res = read_32bit_cp0_register(register); \ res &= ~clear; \ write_32bit_cp0_register(register, res); \ - \ + \ return res; \ } \ \ @@ -297,13 +297,13 @@ extern __inline__ unsigned int \ change_cp0_##name(unsigned int change, unsigned int new) \ { \ unsigned int res; \ - \ + \ res = read_32bit_cp0_register(register); \ res &= ~change; \ res |= (new & change); \ if(change) \ write_32bit_cp0_register(register, res); \ - \ + \ return res; \ } diff --git a/include/asm-mips/posix_types.h b/include/asm-mips/posix_types.h index 6c48b3f8394..879aae210b2 100644 --- a/include/asm-mips/posix_types.h +++ b/include/asm-mips/posix_types.h @@ -45,7 +45,7 @@ typedef long long __kernel_loff_t; #endif typedef struct { - long val[2]; + long val[2]; } __kernel_fsid_t; #if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) @@ -68,7 +68,7 @@ static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp) #undef __FD_ISSET static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p) -{ +{ unsigned long __tmp = __fd / __NFDBITS; unsigned long __rem = __fd % __NFDBITS; return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0; diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h index 8c3de908d55..6838aee98cc 100644 --- a/include/asm-mips/processor.h +++ b/include/asm-mips/processor.h @@ -115,8 +115,8 @@ struct mips_fpu_soft_struct { }; union mips_fpu_union { - struct mips_fpu_hard_struct hard; - struct mips_fpu_soft_struct soft; + struct mips_fpu_hard_struct hard; + struct mips_fpu_soft_struct soft; }; #define INIT_FPU { \ @@ -173,11 +173,11 @@ struct thread_struct { #endif /* !defined (_LANGUAGE_ASSEMBLY) */ #define INIT_THREAD { \ - /* \ - * saved main processor registers \ - */ \ + /* \ + * saved main processor registers \ + */ \ 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, \ + 0, 0, 0, \ /* \ * saved cp0 stuff \ */ \ diff --git a/include/asm-mips/string.h b/include/asm-mips/string.h index 343b45eba32..463a111b49a 100644 --- a/include/asm-mips/string.h +++ b/include/asm-mips/string.h @@ -27,7 +27,7 @@ extern __inline__ char *strcpy(char *__dest, __const__ char *__src) ".set\tat\n\t" ".set\treorder" : "=r" (__dest), "=r" (__src) - : "0" (__dest), "1" (__src) + : "0" (__dest), "1" (__src) : "$1","memory"); return __xdest; @@ -54,9 +54,9 @@ extern __inline__ char *strncpy(char *__dest, __const__ char *__src, size_t __n) "2:\n\t" ".set\tat\n\t" ".set\treorder" - : "=r" (__dest), "=r" (__src), "=r" (__n) - : "0" (__dest), "1" (__src), "2" (__n) - : "$1","memory"); + : "=r" (__dest), "=r" (__src), "=r" (__n) + : "0" (__dest), "1" (__src), "2" (__n) + : "$1","memory"); return __dest; } @@ -110,7 +110,7 @@ strncmp(__const__ char *__cs, __const__ char *__ct, size_t __count) "2:\n\t" #if defined(CONFIG_CPU_R3000) "nop\n\t" -#endif +#endif "move\t%3,$1\n" "3:\tsubu\t%3,$1\n\t" ".set\tat\n\t" diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h index 4b45847e96a..b6d50e2f04e 100644 --- a/include/asm-mips/system.h +++ b/include/asm-mips/system.h @@ -8,7 +8,7 @@ * Copyright (C) 1994 - 1999 by Ralf Baechle * * Changed set_except_vector declaration to allow return of previous - * vector address value - necessary for "borrowing" vectors. + * vector address value - necessary for "borrowing" vectors. * * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com * Copyright (C) 2000 MIPS Technologies, Inc. @@ -124,7 +124,7 @@ extern void __global_cli(void); extern unsigned long __global_save_flags(void); extern void __global_restore_flags(unsigned long); # define sti() __global_sti() -# define cli() __global_cli() +# define cli() __global_cli() # define save_flags(x) do { x = __global_save_flags(); } while (0) # define restore_flags(x) __global_restore_flags(x) # define save_and_cli(x) do { save_flags(x); cli(); } while(0) diff --git a/include/asm-mips/types.h b/include/asm-mips/types.h index 638f75163c3..e757e228ac2 100644 --- a/include/asm-mips/types.h +++ b/include/asm-mips/types.h @@ -32,12 +32,12 @@ typedef __signed__ long __s64; typedef unsigned long __u64; #else - + #if defined(__GNUC__) && !defined(__STRICT_ANSI__) typedef __signed__ long long __s64; typedef unsigned long long __u64; #endif - + #endif /* diff --git a/include/asm-ppc/5xx_immap.h b/include/asm-ppc/5xx_immap.h index ffff975c970..8e570573b6f 100644 --- a/include/asm-ppc/5xx_immap.h +++ b/include/asm-ppc/5xx_immap.h @@ -17,95 +17,95 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, + * Foundation, */ /* * File: 5xx_immap.h - * + * * Discription: MPC555 Internal Memory Map - * + * */ - + #ifndef __IMMAP_5XX__ #define __IMMAP_5XX__ /* System Configuration Registers. */ typedef struct sys_conf { - uint sc_siumcr; - uint sc_sypcr; - char res1[6]; - ushort sc_swsr; - uint sc_sipend; - uint sc_simask; - uint sc_siel; - uint sc_sivec; - uint sc_tesr; - uint sc_sgpiodt1; - uint sc_sgpiodt2; - uint sc_sgpiocr; - uint sc_emcr; - uint sc_res1aa; - uint sc_res1ab; - uint sc_pdmcr; - char res3[192]; + uint sc_siumcr; + uint sc_sypcr; + char res1[6]; + ushort sc_swsr; + uint sc_sipend; + uint sc_simask; + uint sc_siel; + uint sc_sivec; + uint sc_tesr; + uint sc_sgpiodt1; + uint sc_sgpiodt2; + uint sc_sgpiocr; + uint sc_emcr; + uint sc_res1aa; + uint sc_res1ab; + uint sc_pdmcr; + char res3[192]; } sysconf5xx_t; /* Memory Controller Registers. */ typedef struct mem_ctlr { - uint memc_br0; - uint memc_or0; - uint memc_br1; - uint memc_or1; - uint memc_br2; - uint memc_or2; - uint memc_br3; - uint memc_or3; - char res1[32]; - uint memc_dmbr; - uint memc_dmor; - char res2[48]; - ushort memc_mstat; - ushort memc_res4a; - char res3[132]; + uint memc_br0; + uint memc_or0; + uint memc_br1; + uint memc_or1; + uint memc_br2; + uint memc_or2; + uint memc_br3; + uint memc_or3; + char res1[32]; + uint memc_dmbr; + uint memc_dmor; + char res2[48]; + ushort memc_mstat; + ushort memc_res4a; + char res3[132]; } memctl5xx_t; /* System Integration Timers. */ typedef struct sys_int_timers { - ushort sit_tbscr; - char res1[2]; - uint sit_tbref0; - uint sit_tbref1; - char res2[20]; - ushort sit_rtcsc; - char res3[2]; - uint sit_rtc; - uint sit_rtsec; - uint sit_rtcal; - char res4[16]; - ushort sit_piscr; - char res5[2]; - uint sit_pitc; - uint sit_pitr; - char res6[52]; + ushort sit_tbscr; + char res1[2]; + uint sit_tbref0; + uint sit_tbref1; + char res2[20]; + ushort sit_rtcsc; + char res3[2]; + uint sit_rtc; + uint sit_rtsec; + uint sit_rtcal; + char res4[16]; + ushort sit_piscr; + char res5[2]; + uint sit_pitc; + uint sit_pitr; + char res6[52]; } sit5xx_t; /* Clocks and Reset */ typedef struct clk_and_reset { - uint car_sccr; - uint car_plprcr; - ushort car_rsr; - ushort car_res7a; - ushort car_colir; - ushort car_res7b; - ushort car_vsrmcr; - ushort car_res7c; - char res1[108]; + uint car_sccr; + uint car_plprcr; + ushort car_rsr; + ushort car_res7a; + ushort car_colir; + ushort car_res7b; + ushort car_vsrmcr; + ushort car_res7c; + char res1[108]; } car5xx_t; @@ -114,19 +114,19 @@ typedef struct clk_and_reset { /* System Integration Timer Keys */ typedef struct sitk { - uint sitk_tbscrk; - uint sitk_tbref0k; - uint sitk_tbref1k; - uint sitk_tbk; - char res1[16]; - uint sitk_rtcsck; - uint sitk_rtck; - uint sitk_rtseck; - uint sitk_rtcalk; - char res2[16]; - uint sitk_piscrk; - uint sitk_pitck; - char res3[56]; + uint sitk_tbscrk; + uint sitk_tbref0k; + uint sitk_tbref1k; + uint sitk_tbk; + char res1[16]; + uint sitk_rtcsck; + uint sitk_rtck; + uint sitk_rtseck; + uint sitk_rtcalk; + char res2[16]; + uint sitk_piscrk; + uint sitk_pitck; + char res3[56]; } sitk5xx_t; /* Clocks and Reset Keys. @@ -145,114 +145,114 @@ typedef struct cark { /* Flash Configuration */ typedef struct fl { - uint fl_cmfmcr; - uint fl_cmftst; - uint fl_cmfctl; - char res1[52]; + uint fl_cmfmcr; + uint fl_cmftst; + uint fl_cmfctl; + char res1[52]; } fl5xx_t; /* Dpram Control */ -typedef struct dprc { - ushort dprc_dptmcr; - ushort dprc_ramtst; - ushort dprc_rambar; - ushort dprc_misrh; - ushort dprc_misrl; - ushort dprc_miscnt; +typedef struct dprc { + ushort dprc_dptmcr; + ushort dprc_ramtst; + ushort dprc_rambar; + ushort dprc_misrh; + ushort dprc_misrl; + ushort dprc_miscnt; } dprc5xx_t; /* Time Processor Unit */ typedef struct tpu { - ushort tpu_tpumcr; - ushort tpu_tcr; - ushort tpu_dscr; - ushort tpu_dssr; - ushort tpu_ticr; - ushort tpu_cier; - ushort tpu_cfsr0; - ushort tpu_cfsr1; - ushort tpu_cfsr2; - ushort tpu_cfsr3; - ushort tpu_hsqr0; - ushort tpu_hsqr1; - ushort tpu_hsrr0; - ushort tpu_hsrr1; - ushort tpu_cpr0; - ushort tpu_cpr1; - ushort tpu_cisr; - ushort tpu_lr; - ushort tpu_sglr; - ushort tpu_dcnr; - ushort tpu_tpumcr2; - ushort tpu_tpumcr3; - ushort tpu_isdr; - ushort tpu_iscr; - char res1[208]; - char tpu[16][16]; - char res2[512]; + ushort tpu_tpumcr; + ushort tpu_tcr; + ushort tpu_dscr; + ushort tpu_dssr; + ushort tpu_ticr; + ushort tpu_cier; + ushort tpu_cfsr0; + ushort tpu_cfsr1; + ushort tpu_cfsr2; + ushort tpu_cfsr3; + ushort tpu_hsqr0; + ushort tpu_hsqr1; + ushort tpu_hsrr0; + ushort tpu_hsrr1; + ushort tpu_cpr0; + ushort tpu_cpr1; + ushort tpu_cisr; + ushort tpu_lr; + ushort tpu_sglr; + ushort tpu_dcnr; + ushort tpu_tpumcr2; + ushort tpu_tpumcr3; + ushort tpu_isdr; + ushort tpu_iscr; + char res1[208]; + char tpu[16][16]; + char res2[512]; } tpu5xx_t; /* QADC */ typedef struct qadc { - ushort qadc_64mcr; - ushort qadc_64test; - ushort qadc_64int; - u_char qadc_portqa; - u_char qadc_portqb; - ushort qadc_ddrqa; - ushort qadc_qacr0; - ushort qadc_qacr1; - ushort qadc_qacr2; - ushort qadc_qasr0; - ushort qadc_qasr1; - char res1[492]; + ushort qadc_64mcr; + ushort qadc_64test; + ushort qadc_64int; + u_char qadc_portqa; + u_char qadc_portqb; + ushort qadc_ddrqa; + ushort qadc_qacr0; + ushort qadc_qacr1; + ushort qadc_qacr2; + ushort qadc_qasr0; + ushort qadc_qasr1; + char res1[492]; /* command convertion word table */ - ushort qadc_ccw[64]; + ushort qadc_ccw[64]; /* result word table, unsigned right justified */ - ushort qadc_rjurr[64]; + ushort qadc_rjurr[64]; /* result word table, signed left justified */ - ushort qadc_ljsrr[64]; + ushort qadc_ljsrr[64]; /* result word table, unsigned left justified */ - ushort qadc_ljurr[64]; + ushort qadc_ljurr[64]; } qadc5xx_t; /* QSMCM */ typedef struct qsmcm { - ushort qsmcm_qsmcr; - ushort qsmcm_qtest; - ushort qsmcm_qdsci_il; - ushort qsmcm_qspi_il; - ushort qsmcm_scc1r0; - ushort qsmcm_scc1r1; - ushort qsmcm_sc1sr; - ushort qsmcm_sc1dr; - char res1[2]; - char res2[2]; - ushort qsmcm_portqs; - u_char qsmcm_pqspar; - u_char qsmcm_ddrqs; - ushort qsmcm_spcr0; - ushort qsmcm_spcr1; - ushort qsmcm_spcr2; - u_char qsmcm_spcr3; - u_char qsmcm_spsr; - ushort qsmcm_scc2r0; - ushort qsmcm_scc2r1; - ushort qsmcm_sc2sr; - ushort qsmcm_sc2dr; - ushort qsmcm_qsci1cr; - ushort qsmcm_qsci1sr; - ushort qsmcm_sctq[16]; - ushort qsmcm_scrq[16]; - char res3[212]; - ushort qsmcm_recram[32]; - ushort qsmcm_tranram[32]; - u_char qsmcm_comdram[32]; - char res[3616]; + ushort qsmcm_qsmcr; + ushort qsmcm_qtest; + ushort qsmcm_qdsci_il; + ushort qsmcm_qspi_il; + ushort qsmcm_scc1r0; + ushort qsmcm_scc1r1; + ushort qsmcm_sc1sr; + ushort qsmcm_sc1dr; + char res1[2]; + char res2[2]; + ushort qsmcm_portqs; + u_char qsmcm_pqspar; + u_char qsmcm_ddrqs; + ushort qsmcm_spcr0; + ushort qsmcm_spcr1; + ushort qsmcm_spcr2; + u_char qsmcm_spcr3; + u_char qsmcm_spsr; + ushort qsmcm_scc2r0; + ushort qsmcm_scc2r1; + ushort qsmcm_sc2sr; + ushort qsmcm_sc2dr; + ushort qsmcm_qsci1cr; + ushort qsmcm_qsci1sr; + ushort qsmcm_sctq[16]; + ushort qsmcm_scrq[16]; + char res3[212]; + ushort qsmcm_recram[32]; + ushort qsmcm_tranram[32]; + u_char qsmcm_comdram[32]; + char res[3616]; } qsmcm5xx_t; @@ -260,136 +260,136 @@ typedef struct qsmcm { */ typedef struct mios { - ushort mios_mpwmsm0perr; /* mpwmsm0 */ - ushort mios_mpwmsm0pulr; - ushort mios_mpwmsm0cntr; - ushort mios_mpwmsm0scr; - ushort mios_mpwmsm1perr; /* mpwmsm1 */ - ushort mios_mpwmsm1pulr; - ushort mios_mpwmsm1cntr; - ushort mios_mpwmsm1scr; - ushort mios_mpwmsm2perr; /* mpwmsm2 */ - ushort mios_mpwmsm2pulr; - ushort mios_mpwmsm2cntr; - ushort mios_mpwmsm2scr; - ushort mios_mpwmsm3perr; /* mpwmsm3 */ - ushort mios_mpwmsm3pulr; - ushort mios_mpwmsm3cntr; - ushort mios_mpwmsm3scr; - char res1[16]; - ushort mios_mmcsm6cnt; /* mmcsm6 */ - ushort mios_mmcsm6mlr; - ushort mios_mmcsm6scrd, mmcsm6scr; - char res2[32]; - ushort mios_mdasm11ar; /* mdasm11 */ - ushort mios_mdasm11br; - ushort mios_mdasm11scrd, mdasm11scr; - ushort mios_mdasm12ar; /* mdasm12 */ - ushort mios_mdasm12br; - ushort mios_mdasm12scrd, mdasm12scr; - ushort mios_mdasm13ar; /* mdasm13 */ - ushort mios_mdasm13br; - ushort mios_mdasm13scrd, mdasm13scr; - ushort mios_mdasm14ar; /* mdasm14 */ - ushort mios_mdasm14br; - ushort mios_mdasm14scrd, mdasm14scr; - ushort mios_mdasm15ar; /* mdasm15 */ - ushort mios_mdasm15br; - ushort mios_mdasm15scrd, mdasm15scr; - ushort mios_mpwmsm16perr; /* mpwmsm16 */ - ushort mios_mpwmsm16pulr; - ushort mios_mpwmsm16cntr; - ushort mios_mpwmsm16scr; - ushort mios_mpwmsm17perr; /* mpwmsm17 */ - ushort mios_mpwmsm17pulr; - ushort mios_mpwmsm17cntr; - ushort mios_mpwmsm17scr; - ushort mios_mpwmsm18perr; /* mpwmsm18 */ - ushort mios_mpwmsm18pulr; - ushort mios_mpwmsm18cntr; - ushort mios_mpwmsm18scr; - ushort mios_mpwmsm19perr; /* mpwmsm19 */ - ushort mios_mpwmsm19pulr; - ushort mios_mpwmsm19cntr; - ushort mios_mpwmsm19scr; - char res3[16]; - ushort mios_mmcsm22cnt; /* mmcsm22 */ - ushort mios_mmcsm22mlr; - ushort mios_mmcsm22scrd, mmcsm22scr; - char res4[32]; - ushort mios_mdasm27ar; /* mdasm27 */ - ushort mios_mdasm27br; - ushort mios_mdasm27scrd, mdasm27scr; - ushort mios_mdasm28ar; /*mdasm28 */ - ushort mios_mdasm28br; - ushort mios_mdasm28scrd, mdasm28scr; - ushort mios_mdasm29ar; /* mdasm29 */ - ushort mios_mdasm29br; - ushort mios_mdasm29scrd, mdasm29scr; - ushort mios_mdasm30ar; /* mdasm30 */ - ushort mios_mdasm30br; - ushort mios_mdasm30scrd, mdasm30scr; - ushort mios_mdasm31ar; /* mdasm31 */ - ushort mios_mdasm31br; - ushort mios_mdasm31scrd, mdasm31scr; - ushort mios_mpiosm32dr; - ushort mios_mpiosm32ddr; - char res5[1788]; - ushort mios_mios1tpcr; - char mios_res13[2]; - ushort mios_mios1vnr; - ushort mios_mios1mcr; - char res6[12]; - ushort mios_res42z; - ushort mios_mcpsmscr; - char res7[1000]; - ushort mios_mios1sr0; - char res12[2]; - ushort mios_mios1er0; - ushort mios_mios1rpr0; - char res8[40]; - ushort mios_mios1lvl0; - char res9[14]; - ushort mios_mios1sr1; - char res10[2]; - ushort mios_mios1er1; - ushort mios_mios1rpr1; - char res11[40]; - ushort mios_mios1lvl1; - char res13[1038]; + ushort mios_mpwmsm0perr; /* mpwmsm0 */ + ushort mios_mpwmsm0pulr; + ushort mios_mpwmsm0cntr; + ushort mios_mpwmsm0scr; + ushort mios_mpwmsm1perr; /* mpwmsm1 */ + ushort mios_mpwmsm1pulr; + ushort mios_mpwmsm1cntr; + ushort mios_mpwmsm1scr; + ushort mios_mpwmsm2perr; /* mpwmsm2 */ + ushort mios_mpwmsm2pulr; + ushort mios_mpwmsm2cntr; + ushort mios_mpwmsm2scr; + ushort mios_mpwmsm3perr; /* mpwmsm3 */ + ushort mios_mpwmsm3pulr; + ushort mios_mpwmsm3cntr; + ushort mios_mpwmsm3scr; + char res1[16]; + ushort mios_mmcsm6cnt; /* mmcsm6 */ + ushort mios_mmcsm6mlr; + ushort mios_mmcsm6scrd, mmcsm6scr; + char res2[32]; + ushort mios_mdasm11ar; /* mdasm11 */ + ushort mios_mdasm11br; + ushort mios_mdasm11scrd, mdasm11scr; + ushort mios_mdasm12ar; /* mdasm12 */ + ushort mios_mdasm12br; + ushort mios_mdasm12scrd, mdasm12scr; + ushort mios_mdasm13ar; /* mdasm13 */ + ushort mios_mdasm13br; + ushort mios_mdasm13scrd, mdasm13scr; + ushort mios_mdasm14ar; /* mdasm14 */ + ushort mios_mdasm14br; + ushort mios_mdasm14scrd, mdasm14scr; + ushort mios_mdasm15ar; /* mdasm15 */ + ushort mios_mdasm15br; + ushort mios_mdasm15scrd, mdasm15scr; + ushort mios_mpwmsm16perr; /* mpwmsm16 */ + ushort mios_mpwmsm16pulr; + ushort mios_mpwmsm16cntr; + ushort mios_mpwmsm16scr; + ushort mios_mpwmsm17perr; /* mpwmsm17 */ + ushort mios_mpwmsm17pulr; + ushort mios_mpwmsm17cntr; + ushort mios_mpwmsm17scr; + ushort mios_mpwmsm18perr; /* mpwmsm18 */ + ushort mios_mpwmsm18pulr; + ushort mios_mpwmsm18cntr; + ushort mios_mpwmsm18scr; + ushort mios_mpwmsm19perr; /* mpwmsm19 */ + ushort mios_mpwmsm19pulr; + ushort mios_mpwmsm19cntr; + ushort mios_mpwmsm19scr; + char res3[16]; + ushort mios_mmcsm22cnt; /* mmcsm22 */ + ushort mios_mmcsm22mlr; + ushort mios_mmcsm22scrd, mmcsm22scr; + char res4[32]; + ushort mios_mdasm27ar; /* mdasm27 */ + ushort mios_mdasm27br; + ushort mios_mdasm27scrd, mdasm27scr; + ushort mios_mdasm28ar; /*mdasm28 */ + ushort mios_mdasm28br; + ushort mios_mdasm28scrd, mdasm28scr; + ushort mios_mdasm29ar; /* mdasm29 */ + ushort mios_mdasm29br; + ushort mios_mdasm29scrd, mdasm29scr; + ushort mios_mdasm30ar; /* mdasm30 */ + ushort mios_mdasm30br; + ushort mios_mdasm30scrd, mdasm30scr; + ushort mios_mdasm31ar; /* mdasm31 */ + ushort mios_mdasm31br; + ushort mios_mdasm31scrd, mdasm31scr; + ushort mios_mpiosm32dr; + ushort mios_mpiosm32ddr; + char res5[1788]; + ushort mios_mios1tpcr; + char mios_res13[2]; + ushort mios_mios1vnr; + ushort mios_mios1mcr; + char res6[12]; + ushort mios_res42z; + ushort mios_mcpsmscr; + char res7[1000]; + ushort mios_mios1sr0; + char res12[2]; + ushort mios_mios1er0; + ushort mios_mios1rpr0; + char res8[40]; + ushort mios_mios1lvl0; + char res9[14]; + ushort mios_mios1sr1; + char res10[2]; + ushort mios_mios1er1; + ushort mios_mios1rpr1; + char res11[40]; + ushort mios_mios1lvl1; + char res13[1038]; } mios5xx_t; /* Toucan Module */ typedef struct tcan { - ushort tcan_tcnmcr; - ushort tcan_cantcr; - ushort tcan_canicr; - u_char tcan_canctrl0; - u_char tcan_canctrl1; - u_char tcan_presdiv; - u_char tcan_canctrl2; - ushort tcan_timer; - char res1[4]; - ushort tcan_rxgmskhi; - ushort tcan_rxgmsklo; - ushort tcan_rx14mskhi; - ushort tcan_rx14msklo; - ushort tcan_rx15mskhi; - ushort tcan_rx15msklo; - char res2[4]; - ushort tcan_estat; - ushort tcan_imask; - ushort tcan_iflag; - u_char tcan_rxectr; - u_char tcan_txectr; - char res3[88]; - struct { - ushort scr; - ushort id_high; - ushort id_low; - u_char data[8]; - char res4[2]; + ushort tcan_tcnmcr; + ushort tcan_cantcr; + ushort tcan_canicr; + u_char tcan_canctrl0; + u_char tcan_canctrl1; + u_char tcan_presdiv; + u_char tcan_canctrl2; + ushort tcan_timer; + char res1[4]; + ushort tcan_rxgmskhi; + ushort tcan_rxgmsklo; + ushort tcan_rx14mskhi; + ushort tcan_rx14msklo; + ushort tcan_rx15mskhi; + ushort tcan_rx15msklo; + char res2[4]; + ushort tcan_estat; + ushort tcan_imask; + ushort tcan_iflag; + u_char tcan_rxectr; + u_char tcan_txectr; + char res3[88]; + struct { + ushort scr; + ushort id_high; + ushort id_low; + u_char data[8]; + char res4[2]; } tcan_mbuff[16]; char res5[640]; } tcan5xx_t; @@ -397,44 +397,43 @@ typedef struct tcan { /* UIMB */ typedef struct uimb { - uint uimb_umcr; - char res1[12]; - uint uimb_utstcreg; - char res2[12]; - uint uimb_uipend; + uint uimb_umcr; + char res1[12]; + uint uimb_utstcreg; + char res2[12]; + uint uimb_uipend; } uimb5xx_t; - /* Internal Memory Map MPC555 */ typedef struct immap { - char res1[262144]; /* CMF Flash A 256 Kbytes */ - char res2[196608]; /* CMF Flash B 192 Kbytes */ - char res3[2670592]; /* Reserved for Flash */ - sysconf5xx_t im_siu_conf; /* SIU Configuration */ - memctl5xx_t im_memctl; /* Memory Controller */ - sit5xx_t im_sit; /* System Integration Timers */ - car5xx_t im_clkrst; /* Clocks and Reset */ - sitk5xx_t im_sitk; /* System Integration Timer Keys*/ - cark8xx_t im_clkrstk; /* Clocks and Resert Keys */ - fl5xx_t im_fla; /* Flash Module A */ - fl5xx_t im_flb; /* Flash Module B */ - char res4[14208]; /* Reserved for SIU */ - dprc5xx_t im_dprc; /* Dpram Control Register */ - char res5[8180]; /* Reserved */ - char dptram[6144]; /* Dptram */ - char res6[2048]; /* Reserved */ - tpu5xx_t im_tpua; /* Time Proessing Unit A */ - tpu5xx_t im_tpub; /* Time Processing Unit B */ - qadc5xx_t im_qadca; /* QADC A */ - qadc5xx_t im_qadcb; /* QADC B */ - qsmcm5xx_t im_qsmcm; /* SCI and SPI */ - mios5xx_t im_mios; /* MIOS */ - tcan5xx_t im_tcana; /* Toucan A */ - tcan5xx_t im_tcanb; /* Toucan B */ - char res7[1792]; /* Reserved */ - uimb5xx_t im_uimb; /* UIMB */ + char res1[262144]; /* CMF Flash A 256 Kbytes */ + char res2[196608]; /* CMF Flash B 192 Kbytes */ + char res3[2670592]; /* Reserved for Flash */ + sysconf5xx_t im_siu_conf; /* SIU Configuration */ + memctl5xx_t im_memctl; /* Memory Controller */ + sit5xx_t im_sit; /* System Integration Timers */ + car5xx_t im_clkrst; /* Clocks and Reset */ + sitk5xx_t im_sitk; /* System Integration Timer Keys*/ + cark8xx_t im_clkrstk; /* Clocks and Resert Keys */ + fl5xx_t im_fla; /* Flash Module A */ + fl5xx_t im_flb; /* Flash Module B */ + char res4[14208]; /* Reserved for SIU */ + dprc5xx_t im_dprc; /* Dpram Control Register */ + char res5[8180]; /* Reserved */ + char dptram[6144]; /* Dptram */ + char res6[2048]; /* Reserved */ + tpu5xx_t im_tpua; /* Time Proessing Unit A */ + tpu5xx_t im_tpub; /* Time Processing Unit B */ + qadc5xx_t im_qadca; /* QADC A */ + qadc5xx_t im_qadcb; /* QADC B */ + qsmcm5xx_t im_qsmcm; /* SCI and SPI */ + mios5xx_t im_mios; /* MIOS */ + tcan5xx_t im_tcana; /* Toucan A */ + tcan5xx_t im_tcanb; /* Toucan B */ + char res7[1792]; /* Reserved */ + uimb5xx_t im_uimb; /* UIMB */ } immap_t; #endif /* __IMMAP_5XX__ */ diff --git a/include/asm-ppc/bitops.h b/include/asm-ppc/bitops.h index 5326686c8e9..3264915d896 100644 --- a/include/asm-ppc/bitops.h +++ b/include/asm-ppc/bitops.h @@ -285,7 +285,7 @@ extern __inline__ int ext2_test_bit(int nr, __const__ void * addr) */ #define ext2_find_first_zero_bit(addr, size) \ - ext2_find_next_zero_bit((addr), (size), 0) + ext2_find_next_zero_bit((addr), (size), 0) extern __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset) diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index f242d1b2f1c..19c7fd8c02e 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -83,7 +83,7 @@ typedef struct global_data { #endif #ifdef CONFIG_LWMON unsigned long kbd_status; -#endif +#endif } gd_t; /* diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h index 652b12baf5e..8e5fe113cb3 100644 --- a/include/asm-ppc/io.h +++ b/include/asm-ppc/io.h @@ -126,7 +126,7 @@ extern inline int in_le16(volatile u16 *addr) int ret; __asm__ __volatile__("lhbrx %0,0,%1; eieio" : "=r" (ret) : - "r" (addr), "m" (*addr)); + "r" (addr), "m" (*addr)); return ret; } @@ -141,7 +141,7 @@ extern inline int in_be16(volatile u16 *addr) extern inline void out_le16(volatile u16 *addr, int val) { __asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) : - "r" (val), "r" (addr)); + "r" (val), "r" (addr)); } extern inline void out_be16(volatile u16 *addr, int val) @@ -154,7 +154,7 @@ extern inline unsigned in_le32(volatile u32 *addr) unsigned ret; __asm__ __volatile__("lwbrx %0,0,%1; eieio" : "=r" (ret) : - "r" (addr), "m" (*addr)); + "r" (addr), "m" (*addr)); return ret; } @@ -169,7 +169,7 @@ extern inline unsigned in_be32(volatile u32 *addr) extern inline void out_le32(volatile unsigned *addr, int val) { __asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) : - "r" (val), "r" (addr)); + "r" (val), "r" (addr)); } extern inline void out_be32(volatile unsigned *addr, int val) diff --git a/include/asm-ppc/m8260_pci.h b/include/asm-ppc/m8260_pci.h index 267565818a1..45f01de820c 100644 --- a/include/asm-ppc/m8260_pci.h +++ b/include/asm-ppc/m8260_pci.h @@ -35,8 +35,8 @@ /* - * Outbound ATU registers (3 sets). These registers control how 60x bus (local) - * addresses are translated to PCI addresses when the MPC826x is a PCI bus + * Outbound ATU registers (3 sets). These registers control how 60x bus (local) + * addresses are translated to PCI addresses when the MPC826x is a PCI bus * master (initiator). */ @@ -87,7 +87,7 @@ #define PCIGCR_PCI_BUS_EN 0x1 /* - * Inbound ATU registers (2 sets). These registers control how PCI addresses + * Inbound ATU registers (2 sets). These registers control how PCI addresses * are translated to 60x bus (local) addresses when the MPC826x is a PCI bus target. */ diff --git a/include/asm-ppc/pci_io.h b/include/asm-ppc/pci_io.h index 0f57b5378c3..9b738c383f7 100644 --- a/include/asm-ppc/pci_io.h +++ b/include/asm-ppc/pci_io.h @@ -9,20 +9,20 @@ #define pci_read_le16(addr, dest) \ __asm__ __volatile__("lhbrx %0,0,%1" : "=r" (dest) : \ - "r" (addr), "m" (*addr)); + "r" (addr), "m" (*addr)); #define pci_write_le16(addr, val) \ __asm__ __volatile__("sthbrx %1,0,%2" : "=m" (*addr) : \ - "r" (val), "r" (addr)); + "r" (val), "r" (addr)); #define pci_read_le32(addr, dest) \ __asm__ __volatile__("lwbrx %0,0,%1" : "=r" (dest) : \ - "r" (addr), "m" (*addr)); + "r" (addr), "m" (*addr)); #define pci_write_le32(addr, val) \ __asm__ __volatile__("stwbrx %1,0,%2" : "=m" (*addr) : \ - "r" (val), "r" (addr)); + "r" (val), "r" (addr)); #define pci_readb(addr,b) ((b) = *(volatile u8 *) (addr)) #define pci_writeb(b,addr) ((*(volatile u8 *) (addr)) = (b)) diff --git a/include/asm-ppc/pnp.h b/include/asm-ppc/pnp.h index 15bf7f1dbb4..22ceba22530 100644 --- a/include/asm-ppc/pnp.h +++ b/include/asm-ppc/pnp.h @@ -324,8 +324,8 @@ typedef enum _PnP_INTERFACE { GeneralFloppy = 0, Compatible765 = 1, NS398_Floppy = 2, /* NS Super I/O wired to use index - register at port 398 and data - register at port 399 */ + register at port 398 and data + register at port 399 */ NS26E_Floppy = 3, /* Ports 26E and 26F */ NS15C_Floppy = 4, /* Ports 15C and 15D */ NS2E_Floppy = 5, /* Ports 2E and 2F */ @@ -366,8 +366,8 @@ typedef enum _PnP_INTERFACE { Compatible16450 = 2, Compatible16550 = 3, NS398SerPort = 4, /* NS Super I/O wired to use index - register at port 398 and data - register at port 399 */ + register at port 398 and data + register at port 399 */ NS26ESerPort = 5, /* Ports 26E and 26F */ NS15CSerPort = 6, /* Ports 15C and 15D */ NS2ESerPort = 7, /* Ports 2E and 2F */ @@ -375,8 +375,8 @@ typedef enum _PnP_INTERFACE { GeneralParPort = 0, LPTx = 1, NS398ParPort = 2, /* NS Super I/O wired to use index - register at port 398 and data - register at port 399 */ + register at port 398 and data + register at port 399 */ NS26EParPort = 3, /* Ports 26E and 26F */ NS15CParPort = 4, /* Ports 15C and 15D */ NS2EParPort = 5, /* Ports 2E and 2F */ @@ -436,14 +436,14 @@ typedef enum _PnP_INTERFACE { typedef struct _SERIAL_ID { unsigned char VendorID0; /* Bit(7)=0 */ - /* Bits(6:2)=1st character in */ - /* compressed ASCII */ - /* Bits(1:0)=2nd character in */ - /* compressed ASCII bits(4:3) */ + /* Bits(6:2)=1st character in */ + /* compressed ASCII */ + /* Bits(1:0)=2nd character in */ + /* compressed ASCII bits(4:3) */ unsigned char VendorID1; /* Bits(7:5)=2nd character in */ - /* compressed ASCII bits(2:0) */ - /* Bits(4:0)=3rd character in */ - /* compressed ASCII */ + /* compressed ASCII bits(2:0) */ + /* Bits(4:0)=3rd character in */ + /* compressed ASCII */ unsigned char VendorID2; /* Product number - vendor assigned */ unsigned char VendorID3; /* Product number - vendor assigned */ @@ -511,8 +511,8 @@ typedef union _PnP_TAG_PACKET { unsigned char Tag; /* small tag = 0x15 or 0x16 */ unsigned char DevId[4]; /* Logical device id */ unsigned char Flags[2]; /* bit(0) boot device; */ - /* bit(7:1) cmd in range x31-x37 */ - /* bit(7:0) cmd in range x28-x3f (opt)*/ + /* bit(7:1) cmd in range x31-x37 */ + /* bit(7:0) cmd in range x28-x3f (opt)*/ } S2_Pack; struct _S3_Pack{ /* COMPATIBLE DEVICE ID PACKET */ @@ -523,13 +523,13 @@ typedef union _PnP_TAG_PACKET { struct _S4_Pack{ /* IRQ PACKET */ unsigned char Tag; /* small tag = 0x22 or 0x23 */ unsigned char IRQMask[2]; /* bit(0) is IRQ0, ...; */ - /* bit(0) is IRQ8 ... */ + /* bit(0) is IRQ8 ... */ unsigned char IRQInfo; /* optional; assume bit(0)=1; else */ - /* bit(0) - high true edge sensitive */ - /* bit(1) - low true edge sensitive */ - /* bit(2) - high true level sensitive*/ - /* bit(3) - low true level sensitive */ - /* bit(7:4) - must be 0 */ + /* bit(0) - high true edge sensitive */ + /* bit(1) - low true edge sensitive */ + /* bit(2) - high true level sensitive*/ + /* bit(3) - low true level sensitive */ + /* bit(7:4) - must be 0 */ } S4_Pack; struct _S5_Pack{ /* DMA PACKET */ @@ -541,9 +541,9 @@ typedef union _PnP_TAG_PACKET { struct _S6_Pack{ /* START DEPENDENT FUNCTION PACKET */ unsigned char Tag; /* small tag = 0x30 or 0x31 */ unsigned char Priority; /* Optional; if missing then x01; else*/ - /* x00 = best possible */ - /* x01 = acceptible */ - /* x02 = sub-optimal but functional */ + /* x00 = best possible */ + /* x01 = acceptible */ + /* x02 = sub-optimal but functional */ } S6_Pack; struct _S7_Pack{ /* END DEPENDENT FUNCTION PACKET */ @@ -571,9 +571,9 @@ typedef union _PnP_TAG_PACKET { union _S14_Data{ unsigned char Data[7]; /* Vendor defined */ struct _S14_PPCPack{ /* Pr*p s14 pack */ - unsigned char Type; /* 00=non-IBM */ - unsigned char PPCData[6]; /* Vendor defined */ - } S14_PPCPack; + unsigned char Type; /* 00=non-IBM */ + unsigned char PPCData[6]; /* Vendor defined */ + } S14_PPCPack; } S14_Data; } S14_Pack; @@ -587,7 +587,7 @@ typedef union _PnP_TAG_PACKET { unsigned char Count0; /* x09 */ unsigned char Count1; /* x00 */ unsigned char Data[9]; /* a variable array of bytes, */ - /* count in tag */ + /* count in tag */ } L1_Pack; struct _L2_Pack{ /* ANSI ID STRING PACKET */ @@ -595,7 +595,7 @@ typedef union _PnP_TAG_PACKET { unsigned char Count0; /* Length of string */ unsigned char Count1; unsigned char Identifier[1]; /* a variable array of bytes, */ - /* count in tag */ + /* count in tag */ } L2_Pack; struct _L3_Pack{ /* UNICODE ID STRING PACKET */ @@ -605,7 +605,7 @@ typedef union _PnP_TAG_PACKET { unsigned char Country0; /* TBD */ unsigned char Country1; /* TBD */ unsigned char Identifier[1]; /* a variable array of bytes, */ - /* count in tag */ + /* count in tag */ } L3_Pack; struct _L4_Pack{ /* VENDOR DEFINED PACKET */ @@ -614,12 +614,12 @@ typedef union _PnP_TAG_PACKET { unsigned char Count1; union _L4_Data{ unsigned char Data[1]; /* a variable array of bytes, */ - /* count in tag */ + /* count in tag */ struct _L4_PPCPack{ /* Pr*p L4 packet */ - unsigned char Type; /* 00=non-IBM */ - unsigned char PPCData[1]; /* a variable array of bytes, */ - /* count in tag */ - } L4_PPCPack; + unsigned char Type; /* 00=non-IBM */ + unsigned char PPCData[1]; /* a variable array of bytes, */ + /* count in tag */ + } L4_PPCPack; } L4_Data; } L4_Pack; diff --git a/include/asm-ppc/ptrace.h b/include/asm-ppc/ptrace.h index 93a75bd87f6..3c2f4e605a9 100644 --- a/include/asm-ppc/ptrace.h +++ b/include/asm-ppc/ptrace.h @@ -105,4 +105,3 @@ struct pt_regs { #define PT_FPSCR (PT_FPR0 + 2*32 + 1) #endif - diff --git a/include/asm-ppc/residual.h b/include/asm-ppc/residual.h index c037a4e4aea..dc85edbc3ce 100644 --- a/include/asm-ppc/residual.h +++ b/include/asm-ppc/residual.h @@ -76,15 +76,15 @@ typedef struct _VPD { /* Box dependent stuff */ unsigned char PrintableModel[32]; /* Null terminated string. - Must be of the form: - vvv,<20h>,<model designation>,<0x0> - where vvv is the vendor ID - e.g. IBM PPS MODEL 6015<0x0> */ + Must be of the form: + vvv,<20h>,<model designation>,<0x0> + where vvv is the vendor ID + e.g. IBM PPS MODEL 6015<0x0> */ unsigned char Serial[16]; /* 12/94: - Serial Number; must be of the form: - vvv<serial number> where vvv is the - vendor ID. - e.g. IBM60151234567<20h><20h> */ + Serial Number; must be of the form: + vvv<serial number> where vvv is the + vendor ID. + e.g. IBM60151234567<20h><20h> */ unsigned char Reserved[48]; unsigned long FirmwareSupplier; /* See FirmwareSuppliers enum */ unsigned long FirmwareSupports; /* See FirmwareSupport enum */ @@ -103,22 +103,22 @@ typedef struct _VPD { unsigned long WordWidth; /* Word width in bits */ unsigned long PageSize; /* Page size in bytes */ unsigned long CoherenceBlockSize; /* Unit of transfer in/out of cache - for which coherency is maintained; - normally <= CacheLineSize. */ + for which coherency is maintained; + normally <= CacheLineSize. */ unsigned long GranuleSize; /* Unit of lock allocation to avoid */ - /* false sharing of locks. */ + /* false sharing of locks. */ /* L1 Cache variables */ unsigned long CacheSize; /* L1 Cache size in KB. This is the */ - /* total size of the L1, whether */ - /* combined or split */ + /* total size of the L1, whether */ + /* combined or split */ unsigned long CacheAttrib; /* L1CACHE_TYPE */ unsigned long CacheAssoc; /* L1 Cache associativity. Use this - for combined cache. If split, put - zeros here. */ + for combined cache. If split, put + zeros here. */ unsigned long CacheLineSize; /* L1 Cache line size in bytes. Use - for combined cache. If split, put - zeros here. */ + for combined cache. If split, put + zeros here. */ /* For split L1 Cache: (= combined if combined cache) */ unsigned long I_CacheSize; unsigned long I_CacheAssoc; @@ -131,8 +131,8 @@ typedef struct _VPD { unsigned long TLBSize; /* Total number of TLBs on the system */ unsigned long TLBAttrib; /* Combined I+D or split TLB */ unsigned long TLBAssoc; /* TLB Associativity. Use this for - combined TLB. If split, put zeros - here. */ + combined TLB. If split, put zeros + here. */ /* For split TLB: (= combined if combined TLB) */ unsigned long I_TLBSize; unsigned long I_TLBAssoc; @@ -140,7 +140,7 @@ typedef struct _VPD { unsigned long D_TLBAssoc; unsigned long ExtendedVPD; /* Offset to extended VPD area; - null if unused */ + null if unused */ } VPD; typedef enum _DEVICE_FLAGS { @@ -148,11 +148,11 @@ typedef enum _DEVICE_FLAGS { Integrated = 0x2000, Failed = 0x1000, /* 1 - device failed POST code tests */ Static = 0x0800, /* 0 - dynamically configurable - 1 - static */ + 1 - static */ Dock = 0x0400, /* 0 - not a docking station device - 1 - is a docking station device */ + 1 - is a docking station device */ Boot = 0x0200, /* 0 - device cannot be used for BOOT - 1 - can be a BOOT device */ + 1 - can be a BOOT device */ Configurable = 0x0100, /* 1 - device is configurable */ Disableable = 0x80, /* 1 - device can be disabled */ PowerManaged = 0x40, /* 0 - not managed; 1 - managed */ @@ -180,7 +180,7 @@ typedef struct _DEVICE_ID { unsigned long BusId; /* See BUS_ID enum above */ unsigned long DevId; /* Big Endian format */ unsigned long SerialNum; /* For multiple usage of a single - DevId */ + DevId */ unsigned long Flags; /* See DEVICE_FLAGS enum above */ unsigned char BaseType; /* See pnp.h for bit definitions */ unsigned char SubType; /* See pnp.h for bit definitions */ @@ -196,7 +196,7 @@ typedef union _BUS_ACCESS { } PnPAccess; struct _ISAAccess{ unsigned char SlotNumber; /* ISA Slot Number generally not - available; 0 if unknown */ + available; 0 if unknown */ unsigned char LogicalDevNumber; unsigned short ISAReserved; } ISAAccess; @@ -249,9 +249,9 @@ typedef enum _CPU_STATE { typedef struct _PPC_CPU { unsigned long CpuType; /* Result of mfspr from Processor - Version Register (PVR). - PVR(0-15) = Version (e.g. 601) - PVR(16-31 = EC Level */ + Version Register (PVR). + PVR(0-15) = Version (e.g. 601) + PVR(16-31 = EC Level */ unsigned char CpuNumber; /* CPU Number for this processor */ unsigned char CpuState; /* CPU State, see CPU_STATE enum */ unsigned short Reserved; @@ -259,7 +259,7 @@ typedef struct _PPC_CPU { typedef struct _PPC_MEM { unsigned long SIMMSize; /* 0 - absent or bad - 8M, 32M (in MB) */ + 8M, 32M (in MB) */ } PPC_MEM; typedef enum _MEM_USAGE { @@ -297,8 +297,8 @@ typedef struct _RESIDUAL { /* CPU */ unsigned short MaxNumCpus; /* Max CPUs in this system */ unsigned short ActualNumCpus; /* ActualNumCpus < MaxNumCpus means */ - /* that there are unpopulated or */ - /* otherwise unusable cpu locations */ + /* that there are unpopulated or */ + /* otherwise unusable cpu locations */ PPC_CPU Cpus[MAX_CPUS]; /* Memory */ unsigned long TotalMemory; /* Total amount of memory installed */ @@ -329,4 +329,3 @@ extern PnP_TAG_PACKET *PnP_find_large_vendor_packet(unsigned char *p, int n); #endif /* __ASSEMBLY__ */ #endif /* ndef _RESIDUAL_ */ - diff --git a/include/at91rm9200_net.h b/include/at91rm9200_net.h index e41fe3cf7ca..19f0d3edfed 100644 --- a/include/at91rm9200_net.h +++ b/include/at91rm9200_net.h @@ -1,7 +1,7 @@ /* * Ethernet: An implementation of the Ethernet Device Driver suite for the * uClinux 2.0.38 operating system. This Driver has been developed - * for AT75C220 board. + * for AT75C220 board. * * NOTE: The driver is implemented for one MAC * @@ -39,7 +39,7 @@ typedef struct _AT91S_PhyOps unsigned int (*IsPhyConnected)(AT91S_EMAC *pmac); unsigned char (*GetLinkSpeed)(AT91S_EMAC *pmac); unsigned char (*AutoNegotiate)(AT91S_EMAC *pmac, int *); - + } AT91S_PhyOps,*AT91PS_PhyOps; @@ -56,4 +56,3 @@ static UCHAR at91rm9200_EmacWritePhy(AT91PS_EMAC p_mac, unsigned char RegisterAd void at91rm92000_GetPhyInterface(void ); #endif /* AT91RM9200_ETHERNET */ - diff --git a/include/bedbug/tables.h b/include/bedbug/tables.h index 794741a52ec..66cf8eaea31 100644 --- a/include/bedbug/tables.h +++ b/include/bedbug/tables.h @@ -599,4 +599,3 @@ const unsigned int n_sprs = sizeof(spr_map) / sizeof(spr_map[0]); * warranties of merchantability and fitness for a particular * purpose. */ - diff --git a/include/bedbug/type.h b/include/bedbug/type.h new file mode 100644 index 00000000000..38ee9ded739 --- /dev/null +++ b/include/bedbug/type.h @@ -0,0 +1,26 @@ +#ifndef _TYPE_BEDBUG_H +#define _TYPE_BEDBUG_H + +/* Supporting routines */ +int bedbug_puts (const char *); +void bedbug_init (void); +void bedbug860_init (void); +void do_bedbug_breakpoint (struct pt_regs *); +void bedbug_main_loop (unsigned long, struct pt_regs *); + + +typedef struct { + int hw_debug_enabled; + int stopped; + int current_bp; + struct pt_regs *regs; + + void (*do_break) (cmd_tbl_t *, int, int, char *[]); + void (*break_isr) (struct pt_regs *); + int (*find_empty) (void); + int (*set) (int, unsigned long); + int (*clear) (int); +} CPU_DEBUG_CTX; + + +#endif /* _TYPE_BEDBUG_H */ diff --git a/include/bmp_layout.h b/include/bmp_layout.h index 7285a264d68..9d90e7f3933 100644 --- a/include/bmp_layout.h +++ b/include/bmp_layout.h @@ -56,7 +56,7 @@ typedef struct bmp_header { __u32 colors_used; __u32 colors_important; /* ColorTable */ - + } __attribute__((packed)) bmp_header_t; typedef struct bmp_image { diff --git a/include/cmd_autoscript.h b/include/cmd_autoscript.h index 520cfc9daa3..ca5fdb5557a 100644 --- a/include/cmd_autoscript.h +++ b/include/cmd_autoscript.h @@ -28,20 +28,7 @@ #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) -#define CMD_TBL_AUTOSCRIPT MK_CMD_TBL_ENTRY( \ - "autoscr", 5, 2, 0, do_autoscript, \ - "autoscr - run script from memory\n", \ - "[addr] - run script starting at addr. " \ - "A valid autoscr header must be present\n" \ -), - int autoscript (ulong addr); -int do_autoscript (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#else - -#define CMD_TBL_AUTOSCRIPT - #endif #endif /* _CMD_AUTOSCRIPT_H_ */ diff --git a/include/cmd_bedbug.h b/include/cmd_bedbug.h deleted file mode 100644 index 105441e44ca..00000000000 --- a/include/cmd_bedbug.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * BedBug Functions - */ -#ifndef _CMD_BEDBUG_H -#define _CMD_BEDBUG_H - -#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) - -#define CMD_TBL_DIS MK_CMD_TBL_ENTRY( \ - "ds", 2, 3, 1, do_bedbug_dis, \ - "ds - disassemble memory\n", \ - "ds <address> [# instructions]\n" \ - ), - -#define CMD_TBL_ASM MK_CMD_TBL_ENTRY( \ - "as", 2, 2, 0, do_bedbug_asm, \ - "as - assemble memory\n", \ - "as <address>\n" \ - ), - -#define CMD_TBL_BREAK MK_CMD_TBL_ENTRY( \ - "break", 2, 3, 0, do_bedbug_break, \ - "break - set or clear a breakpoint\n", \ - " - Set or clear a breakpoint\n" \ - "break <address> - Break at an address\n" \ - "break off <bp#> - Disable breakpoint.\n" \ - "break show - List breakpoints.\n" \ - ), - -#define CMD_TBL_CONTINUE MK_CMD_TBL_ENTRY( \ - "continue", 4, 1, 0, do_bedbug_continue, \ - "continue- continue from a breakpoint\n", \ - " - continue from a breakpoint.\n" \ - ), - -#define CMD_TBL_STEP MK_CMD_TBL_ENTRY( \ - "step", 4, 1, 1, do_bedbug_step, \ - "step - single step execution.\n", \ - " - single step execution.\n" \ - ), - -#define CMD_TBL_NEXT MK_CMD_TBL_ENTRY( \ - "next", 4, 1, 1, do_bedbug_next, \ - "next - single step execution, stepping over subroutines.\n",\ - " - single step execution, stepping over subroutines.\n" \ - ), - -#define CMD_TBL_STACK MK_CMD_TBL_ENTRY( \ - "where", 5, 1, 1, do_bedbug_stack, \ - "where - Print the running stack.\n", \ - " - Print the running stack.\n" \ - ), - -#define CMD_TBL_RDUMP MK_CMD_TBL_ENTRY( \ - "rdump", 5, 1, 1, do_bedbug_rdump, \ - "rdump - Show registers.\n", \ - " - Show registers.\n" \ - ), - -extern int do_bedbug_dis (cmd_tbl_t *, int, int, char *[]); -extern int do_bedbug_asm (cmd_tbl_t *, int, int, char *[]); -extern int do_bedbug_break (cmd_tbl_t *, int, int, char *[]); -extern int do_bedbug_continue (cmd_tbl_t *, int, int, char *[]); -extern int do_bedbug_step (cmd_tbl_t *, int, int, char *[]); -extern int do_bedbug_next (cmd_tbl_t *, int, int, char *[]); -extern int do_bedbug_stack (cmd_tbl_t *, int, int, char *[]); -extern int do_bedbug_rdump (cmd_tbl_t *, int, int, char *[]); - -/* Supporting routines */ -extern int bedbug_puts (const char *); -extern void bedbug_init (void); -extern void do_bedbug_breakpoint (struct pt_regs *); -extern void bedbug_main_loop (unsigned long, struct pt_regs *); - - -typedef struct { - int hw_debug_enabled; - int stopped; - int current_bp; - struct pt_regs *regs; - - void (*do_break) (cmd_tbl_t *, int, int, char *[]); - void (*break_isr) (struct pt_regs *); - int (*find_empty) (void); - int (*set) (int, unsigned long); - int (*clear) (int); -} CPU_DEBUG_CTX; - -#else /* ! CFG_CMD_BEDBUG */ - -#define CMD_TBL_DIS -#define CMD_TBL_ASM -#define CMD_TBL_BREAK -#define CMD_TBL_CONTINUE -#define CMD_TBL_STEP -#define CMD_TBL_NEXT -#define CMD_TBL_STACK -#define CMD_TBL_RDUMP - -#endif /* CFG_CMD_BEDBUG */ -#endif /* _CMD_BEDBUG_H */ - - -/* - * Copyright (c) 2001 William L. Pitts - * All rights reserved. - * - * Redistribution and use in source and binary forms are freely - * permitted provided that the above copyright notice and this - * paragraph and the following disclaimer are duplicated in all - * such forms. - * - * This software is provided "AS IS" and without any express or - * implied warranties, including, without limitation, the implied - * warranties of merchantability and fitness for a particular - * purpose. - */ diff --git a/include/cmd_boot.h b/include/cmd_boot.h deleted file mode 100644 index 1bd93145233..00000000000 --- a/include/cmd_boot.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Boot support - */ -#ifndef _CMD_BOOT_H -#define _CMD_BOOT_H - -#if (CONFIG_COMMANDS & CFG_CMD_BDI) -#define CMD_TBL_BDINFO MK_CMD_TBL_ENTRY( \ - "bdinfo", 2, 1, 1, do_bdinfo, \ - "bdinfo - print Board Info structure\n", \ - NULL \ -), -int do_bdinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#else -#define CMD_TBL_BDINFO -#endif - - -#define CMD_TBL_GO MK_CMD_TBL_ENTRY( \ - "go", 2, CFG_MAXARGS, 1, do_go, \ - "go - start application at address 'addr'\n", \ - "addr [arg ...]\n - start application at address 'addr'\n" \ - " passing 'arg' as arguments\n" \ -), -int do_go (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#if (CONFIG_COMMANDS & CFG_CMD_LOADS) -#ifdef CFG_LOADS_BAUD_CHANGE -#define CMD_TBL_LOADS MK_CMD_TBL_ENTRY( \ - "loads", 5, 3, 0, do_load_serial, \ - "loads - load S-Record file over serial line\n", \ - "[ off ] [ baud ]\n" \ - " - load S-Record file over serial line" \ - " with offset 'off' and baudrate 'baud'\n" \ -), -#else /* ! CFG_LOADS_BAUD_CHANGE */ -#define CMD_TBL_LOADS MK_CMD_TBL_ENTRY( \ - "loads", 5, 2, 0, do_load_serial, \ - "loads - load S-Record file over serial line\n", \ - "[ off ]\n" \ - " - load S-Record file over serial line with offset 'off'\n" \ -), -#endif /* CFG_LOADS_BAUD_CHANGE */ -int do_load_serial (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -/* - * SAVES always requires LOADS support, but not vice versa - */ -#if (CONFIG_COMMANDS & CFG_CMD_SAVES) -#ifdef CFG_LOADS_BAUD_CHANGE -#define CMD_TBL_SAVES MK_CMD_TBL_ENTRY( \ - "saves", 5, 4, 0, do_save_serial, \ - "saves - save S-Record file over serial line\n", \ - "[ off ] [size] [ baud ]\n" \ - " - save S-Record file over serial line" \ - " with offset 'off', size 'size' and baudrate 'baud'\n" \ -), -#else /* ! CFG_LOADS_BAUD_CHANGE */ -#define CMD_TBL_SAVES MK_CMD_TBL_ENTRY( \ - "saves", 5, 3, 0, do_save_serial, \ - "saves - save S-Record file over serial line\n", \ - "[ off ] [size]\n" \ - " - save S-Record file over serial line with offset 'off' and size 'size'\n" \ -), -#endif /* CFG_LOADS_BAUD_CHANGE */ - -int do_save_serial (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -#else /* ! CFG_CMD_SAVES */ -#define CMD_TBL_SAVES -#endif /* CFG_CMD_SAVES */ - -#else /* ! CFG_CMD_LOADS */ -#define CMD_TBL_LOADS -#define CMD_TBL_SAVES -#endif /* CFG_CMD_LOADS */ - - -#if (CONFIG_COMMANDS & CFG_CMD_LOADB) -#define CMD_TBL_LOADB MK_CMD_TBL_ENTRY( \ - "loadb", 5, 3, 0, do_load_serial_bin, \ - "loadb - load binary file over serial line (kermit mode)\n", \ - "[ off ] [ baud ]\n" \ - " - load binary file over serial line" \ - " with offset 'off' and baudrate 'baud'\n" \ -), -int do_load_serial_bin (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#else -#define CMD_TBL_LOADB -#endif /* CFG_CMD_LOADB */ - -#define CMD_TBL_RESET MK_CMD_TBL_ENTRY( \ - "reset", 5, 1, 0, do_reset, \ - "reset - Perform RESET of the CPU\n", \ - NULL \ -), - -/* Implemented in $(CPU)/cpu.c */ -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#if (CONFIG_COMMANDS & CFG_CMD_HWFLOW) -#define CMD_TBL_HWFLOW MK_CMD_TBL_ENTRY( \ - "hwflow [on|off]", 2, 2, 0, do_hwflow, \ - "hwflow - turn the harwdare flow control on/off\n", \ - "\n - change RTS/CTS hardware flow control over serial line\n" \ -), - -int do_hwflow (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#else -#define CMD_TBL_HWFLOW -#endif -#endif /* _CMD_BOOT_H */ diff --git a/include/cmd_boota.h b/include/cmd_boota.h deleted file mode 100644 index 3ec31183b4a..00000000000 --- a/include/cmd_boota.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * (C) Copyright 2001 - * Thomas Frieden, Hyperion Entertainment - * ThomasF@hyperion-entertainment.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _CMD_BOOTA_H -#define _CMD_BOOTA_H - -#include <common.h> -#include <command.h> - -#if defined(CONFIG_AMIGAONEG3SE) && (CONFIG_COMMANDS & CFG_CMD_BSP) -#define CMD_TBL_BOOTA MK_CMD_TBL_ENTRY( \ - "boota", 5, 3, 1, do_boota, \ - "boota - boot an Amiga kernel\n", \ - "address disk" \ -), - -int do_boota (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ); -#else -#define CMD_TBL_BOOTA -#endif - -#endif /* _CMD_BOOTA_H */ diff --git a/include/cmd_bootm.h b/include/cmd_bootm.h deleted file mode 100644 index 20c12676a70..00000000000 --- a/include/cmd_bootm.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Boot support - */ -#ifndef _CMD_BOOTM_H -#define _CMD_BOOTM_H -int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#define CMD_TBL_BOOTM MK_CMD_TBL_ENTRY( \ - "bootm", 5, CFG_MAXARGS, 1, do_bootm, \ - "bootm - boot application image from memory\n", \ - "[addr [arg ...]]\n - boot application image stored in memory\n" \ - " passing arguments 'arg ...'; when booting a Linux kernel,\n" \ - " 'arg' can be the address of an initrd image\n" \ -), - -#if (CONFIG_COMMANDS & CFG_CMD_BOOTD) -int do_bootd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#define CMD_TBL_BOOTD MK_CMD_TBL_ENTRY( \ - "bootd", 4, 1, 1, do_bootd, \ - "bootd - boot default, i.e., run 'bootcmd'\n", \ - NULL \ -), -#else -#define CMD_TBL_BOOTD -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_IMI) -int do_iminfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -#define CMD_TBL_IMINFO MK_CMD_TBL_ENTRY( \ - "iminfo", 3, CFG_MAXARGS, 1, do_iminfo, \ - "iminfo - print header information for application image\n", \ - "addr [addr ...]\n" \ - " - print header information for application image starting at\n" \ - " address 'addr' in memory; this includes verification of the\n" \ - " image contents (magic number, header and payload checksums)\n" \ -), -#else -#define CMD_TBL_IMINFO -#endif - -#endif /* _CMD_BOOTM_H */ diff --git a/include/cmd_bsp.h b/include/cmd_bsp.h index 008008a8bfe..417d32fb639 100644 --- a/include/cmd_bsp.h +++ b/include/cmd_bsp.h @@ -24,322 +24,6 @@ #ifndef _CMD_BSP_H_ #define _CMD_BSP_H_ -#include <common.h> -#include <command.h> - -#if (CONFIG_COMMANDS & CFG_CMD_BSP) - -/* ----- LWMON --------------------------------------------------------- - */ -#if defined(CONFIG_LWMON) - -#define CMD_TBL_BSP MK_CMD_TBL_ENTRY( \ - "pic", 3, 4, 1, do_pic, \ - "pic - read and write PIC registers\n", \ - "read reg - read PIC register `reg'\n" \ - "pic write reg val - write value `val' to PIC register `reg'\n" \ -), MK_CMD_TBL_ENTRY( \ - "kbd", 3, 1, 1, do_kbd, \ - "kbd - read keyboard status\n", \ - NULL \ -), MK_CMD_TBL_ENTRY( \ - "lsb", 3, 2, 1, do_lsb, \ - "lsb - check and set LSB switch\n", \ - "on - switch LSB on\n" \ - "lsb off - switch LSB off\n" \ - "lsb - print current setting\n" \ -), -int do_pic (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_lsb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#endif /* CONFIG_LWMON */ -/* -------------------------------------------------------------------- */ - -/* ----- PCU E -------------------------------------------------------- */ -#if defined(CONFIG_PCU_E) - -#define CMD_TBL_BSP MK_CMD_TBL_ENTRY( \ - "puma", 4, 4, 1, do_puma, \ - "puma - access PUMA FPGA\n", \ - "status - print PUMA status\n" \ - "puma load addr len - load PUMA configuration data\n" \ -), -int do_puma (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#endif /* CONFIG_PCU_E */ -/* -------------------------------------------------------------------- */ - -/* ----- CCM/SCM ------------------------------------------------------ */ -#if defined(CONFIG_CCM) || defined(CONFIG_SCM) - -#define CMD_TBL_BSP MK_CMD_TBL_ENTRY( \ - "fpga", 4, 4, 1, do_fpga, \ - "fpga - access FPGA(s)\n", \ - "fpga status [name] - print FPGA status\n" \ - "fpga reset [name] - reset FPGA\n" \ - "fpga load [name] addr - load FPGA configuration data\n" \ -), -int do_fpga (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#endif /* CONFIG_CCM, CONFIG_SCM */ -/* -------------------------------------------------------------------- */ - -/* ----- PIP405 ------------------------------------------------------- */ -#if defined(CONFIG_PIP405) - -#define CMD_TBL_BSP MK_CMD_TBL_ENTRY( \ - "pip405", 4, 6, 1, do_pip405, \ - "pip405 - PIP405 specific Cmds\n", \ - "flash mem [SrcAddr] - updates U-Boot with image in memory\n" \ - "pip405 flash floppy [SrcAddr] - updates U-Boot with image from floppy\n" \ - "pip405 flash mps - updates U-Boot with image from MPS\n" \ -), -int do_pip405 (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#endif /* CONFIG_PIP405 */ -/* -------------------------------------------------------------------- */ - -/* ----- MIP405 ------------------------------------------------------- */ -#if defined(CONFIG_MIP405) - -#define CMD_TBL_BSP MK_CMD_TBL_ENTRY( \ - "mip405", 4, 6, 1, do_mip405, \ - "mip405 - MIP405 specific Cmds\n", \ - "flash mem [SrcAddr] - updates U-Boot with image in memory\n" \ - "mip405 flash mps - updates U-Boot with image from MPS\n" \ -), -int do_mip405 (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#endif /* CONFIG_MIP405 */ -/* ----- VCMA9 ----------------------------------------------------------------- - */ -#if defined(CONFIG_VCMA9) - -#define CMD_TBL_BSP MK_CMD_TBL_ENTRY( \ - "vcma9", 4, 6, 1, do_vcma9, \ - "vcma9 - VCMA9 specific Cmds\n", \ - "flash mem [SrcAddr] - updates U-Boot with image in memory\n" \ -), -int do_vcma9 (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#endif /* CONFIG_VCMA9 */ -/* ----------------------------------------------------------------------------*/ - -/* ----- DASA_SIM ----------------------------------------------------- */ -#if defined(CONFIG_DASA_SIM) - -#define CMD_TBL_BSP MK_CMD_TBL_ENTRY( \ - "pci9054", 7, 3, 1, do_pci9054, \ - "pci9054 - PLX PCI9054 EEPROM access\n", \ - "pci9054 info - print EEPROM values\n" \ - "pci9054 update - updates EEPROM with default values\n" \ -), -int do_pci9054 (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#endif /* CONFIG_DASA_SIM */ -/* -------------------------------------------------------------------- */ - -/* ----- HYMOD -------------------------------------------------------- */ -#if defined(CONFIG_HYMOD) - -#define CMD_TBL_BSP MK_CMD_TBL_ENTRY( \ - "fpga", 4, 6, 1, do_fpga, \ - "fpga - FPGA sub-system\n", \ - "load [type] addr size\n" \ - " - write the configuration data at memory address `addr',\n" \ - " size `size' bytes, into the FPGA of type `type' (either\n" \ - " `main' or `mezz', default `main'). e.g.\n" \ - " `fpga load 100000 7d8f'\n" \ - " loads the main FPGA with config data at address 100000\n" \ - " HEX, size 7d8f HEX (32143 DEC) bytes\n" \ - "fpga tftp file addr\n" \ - " - transfers `file' from the tftp server into memory at\n" \ - " address `addr', then writes the entire file contents\n" \ - " into the main FPGA\n" \ - "fpga store addr\n" \ - " - read configuration data from the main FPGA (the mezz\n" \ - " FPGA is write-only), into address `addr'. There must be\n" \ - " enough memory available at `addr' to hold all the config\n"\ - " data - the size of which is determined by VC:???\n" \ - "fpga info\n" \ - " - print information about the Hymod FPGA, namely the\n" \ - " memory addresses at which the four FPGA local bus\n" \ - " address spaces appear in the physical address space\n" \ -), MK_CMD_TBL_ENTRY( \ - "eeclear", 4, 1, 0, do_eecl, \ - "eeclear - Clear the eeprom on a Hymod board\n", \ - "[type]\n" \ - " - write zeroes into the EEPROM on the board of type `type'\n"\ - " (`type' is either `main' or `mezz' - default `main')\n" \ - " Note: the EEPROM write enable jumper must be installed\n" \ -), MK_CMD_TBL_ENTRY( \ - "htest", 5, 1, 0, do_htest, \ - "htest - run HYMOD tests\n", \ - NULL \ -), - -int do_fpga (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_eecl (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_htest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#endif /* CONFIG_HYMOD */ -/* -------------------------------------------------------------------- */ - -/* ----- CRAY405 (L1) ------------------------------------------------- */ -#if defined (CONFIG_CRAYL1) -#define CMD_TBL_BSP MK_CMD_TBL_ENTRY( \ - "L1cmd", 5, 4, 1, do_crayL1, \ - "L1cmd - L1 update, setup, commands \n", \ - "L1cmd update - update flash images from host\n" \ - "L1cmd boot - nfs or ramboot L1\n" \ -), -int do_crayL1 (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -#endif /* CONFIG_CRAY405 */ -/* -------------------------------------------------------------------- */ - -/* ----- EVB64260 ----------------------------------------------------- */ -#if defined (CONFIG_EVB64260) -#ifdef CONFIG_ZUMA_V2 -#define CMD_TBL_BSP ZUMA_TBL_ENTRY - -#define ZUMA_TBL_ENTRY MK_CMD_TBL_ENTRY( \ - "zinit", 5, 1, 0, do_zuma_init_pbb, \ - "zinit - init zuma pbb\n", \ - "\n" \ - " - init zuma pbb\n" \ -), MK_CMD_TBL_ENTRY( \ - "zdtest", 6, 3, 1, do_zuma_test_dma, \ - "zdtest - run dma test\n", \ - "[cmd [count]]\n" \ - " - run dma cmd (w=0,v=1,cp=2,cmp=3,wi=4,vi=5), count bytes\n" \ -), MK_CMD_TBL_ENTRY( \ - "zminit", 5, 1, 0, do_zuma_init_mbox, \ - "zminit - init zuma mbox\n", \ - "\n" \ - " - init zuma mbox\n" \ -), - -int do_zuma_init_pbb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_zuma_test_dma (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_zuma_init_mbox (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -void zuma_init_pbb(void); -int zuma_mbox_init(void); -int zuma_test_dma(int cmd, int size); -#else -#define CMD_TBL_BSP -#endif /* ZUMA_NTL */ - -#endif /* CONFIG_EVB64260 */ -/* -------------------------------------------------------------------- */ - -/* -----W7O------------------------------------------------------------ */ -#if defined(CONFIG_W7O) - -#define CMD_TBL_BSP MK_CMD_TBL_ENTRY( \ - "vpd", 3, 2, 1, do_vpd, \ - "vpd - Read Vital Product Data\n", \ - "[dev_addr]\n" \ - " - Read VPD Data from default address, or device address 'dev_addr'.\n" \ -), - -extern int do_vpd (cmd_tbl_t *, int, int, char *[]); - -#endif /* CONFIG_W7O */ -/* -------------------------------------------------------------------- */ - -/* ---- PCIPPC2 / PCIPPC6 --------------------------------------------- */ -#if defined(CONFIG_PCIPPC2) || defined(CONFIG_PCIPPC6) -#if defined(CONFIG_WATCHDOG) - -#define CMD_TBL_BSP MK_CMD_TBL_ENTRY( \ - "wd", 3, 2, 1, do_wd, \ - "wd - check and set watchdog\n", \ - "on - switch watchDog on\n" \ - "wd off - switch watchdog off\n" \ - "wd - print current status\n" \ -), - -extern int do_wd (cmd_tbl_t *, int, int, char *[]); - -#else -#define CMD_TBL_BSP -#endif /* CONFIG_WATCHDOG */ - -#endif /* CONFIG_PCIPPC2 , CONFIG_PCIPPC6 */ -/* -------------------------------------------------------------------- */ - -/* ----- PN62 --------------------------------------------------------- */ -#if defined(CONFIG_PN62) - -#define CMD_TBL_BSP MK_CMD_TBL_ENTRY( \ - "loadpci", 5, 2, 1, do_loadpci, \ - "loadpci - load binary file over PCI\n", \ - "[addr]\n" \ - " - load binary file over PCI to address 'addr'\n" \ -), MK_CMD_TBL_ENTRY( \ - "led" , 3, 3, 1, do_led, \ - "led - set LED 0..11 on the PN62 board\n", \ - "i fun\n" \ - " - set 'i'th LED to function 'fun'\n" \ -), - -extern int do_loadpci (cmd_tbl_t *, int, int, char *[]); -extern int do_led (cmd_tbl_t *, int, int, char *[]); -#endif /* CONFIG_PN62 */ -/* -------------------------------------------------------------------- */ - -/* ----- TRAB --------------------------------------------------------- */ -#if defined(CONFIG_TRAB) - -#define CMD_TBL_BSP MK_CMD_TBL_ENTRY( \ - "kbd", 3, 1, 1, do_kbd, \ - "kbd - read keyboard status\n", \ - NULL \ -), - -int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#endif /* CONFIG_TRAB */ -/* -------------------------------------------------------------------- */ - -/* ----- R360MPI ------------------------------------------------------ */ -#if defined(CONFIG_R360MPI) - -#define CMD_TBL_BSP MK_CMD_TBL_ENTRY( \ - "kbd", 3, 1, 1, do_kbd, \ - "kbd - read keyboard status\n", \ - NULL \ -), - -int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#endif /* CONFIG_R360MPI */ -/* -------------------------------------------------------------------- */ - -/* ------ AMIGAONEG3SE ------------------------------------------------ */ -#if defined(CONFIG_AMIGAONEG3SE) - -#define CMD_TBL_BSP /* dummy */ - -#endif /* AmigaOneG3SE */ -/* ----- PCI405 ------------------------------------------------------- */ -#if defined(CONFIG_PCI405) - -#define CMD_TBL_BSP MK_CMD_TBL_ENTRY( \ - "loadpci", 7, 1, 1, do_loadpci, \ - "loadpci - wait for sync and boot image\n", \ - NULL \ -), - -int do_loadpci (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#endif /* CONFIG_PCI405 */ -/* -------------------------------------------------------------------- */ - -#else -#define CMD_TBL_BSP -#endif /* CFG_CMD_BSP */ +/* do not edit this file */ #endif /* _CMD_BSP_H_ */ diff --git a/include/cmd_cache.h b/include/cmd_cache.h deleted file mode 100644 index 479a8467099..00000000000 --- a/include/cmd_cache.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Cache support: switch on or off, get status - */ -#ifndef _CMD_CACHE_H -#define _CMD_CACHE_H - -#if (CONFIG_COMMANDS & CFG_CMD_CACHE) -#define CMD_TBL_ICACHE MK_CMD_TBL_ENTRY( \ - "icache", 2, 2, 1, do_icache, \ - "icache - enable or disable instruction cache\n", \ - "[on, off]\n" \ - " - enable or disable instruction cache\n" \ -), - -#define CMD_TBL_DCACHE MK_CMD_TBL_ENTRY( \ - "dcache", 2, 2, 1, do_dcache, \ - "dcache - enable or disable data cache\n", \ - "[on, off]\n" \ - " - enable or disable data (writethrough) cache\n" \ -), -int do_icache (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_dcache (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -#else -#define CMD_TBL_ICACHE -#define CMD_TBL_DCACHE -#endif /* CFG_CMD_CACHE */ - -#endif /* _CMD_CACHE_H */ diff --git a/include/cmd_confdefs.h b/include/cmd_confdefs.h index 74614eb4c7c..577826c1cf5 100644 --- a/include/cmd_confdefs.h +++ b/include/cmd_confdefs.h @@ -136,7 +136,6 @@ #endif - /* * optional BOOTP fields */ diff --git a/include/cmd_console.h b/include/cmd_console.h deleted file mode 100644 index c5f90c939ff..00000000000 --- a/include/cmd_console.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Network boot support - */ -#ifndef _CMD_CONSOLE_H -#define _CMD_CONSOLE_H - -#if (CONFIG_COMMANDS & CFG_CMD_CONSOLE) -#define CMD_TBL_CONINFO MK_CMD_TBL_ENTRY( \ - "coninfo", 5, 3, 1, do_coninfo, \ - "coninfo - print console devices and information\n", \ - "" \ -), -int do_coninfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#else -#define CMD_TBL_CONINFO -#endif /* CFG_CMD_CONSOLE */ - -#endif diff --git a/include/cmd_dcr.h b/include/cmd_dcr.h deleted file mode 100644 index 97196ad37c8..00000000000 --- a/include/cmd_dcr.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * (C) Copyright 2001 - * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * IBM 4XX DCR Functions - */ -#ifndef _CMD_DCR_H -#define _CMD_DCR_H - -#if defined(CONFIG_4xx) && defined(CFG_CMD_SETGETDCR) -#define CMD_TBL_GETDCR MK_CMD_TBL_ENTRY( \ - "getdcr", 6, 2, 1, do_getdcr, \ - "getdcr - Get an IBM PPC 4xx DCR's value\n", \ - "dcrn - return a DCR's value.\n" \ -), -#define CMD_TBL_SETDCR MK_CMD_TBL_ENTRY( \ - "setdcr", 6, 2, 1, do_setdcr, \ - "setdcr - Set an IBM PPC 4xx DCR's value\n", \ - "dcrn - set a DCR's value.\n" \ -), -extern int do_getdcr (cmd_tbl_t *, int, int, char *[]); -extern int do_setdcr (cmd_tbl_t *, int, int, char *[]); - -/* Supporting routines */ -extern unsigned long get_dcr(unsigned short dcrn); -extern unsigned long set_dcr(unsigned short dcrn, unsigned long value); - -#else - -#define CMD_TBL_GETDCR -#define CMD_TBL_SETDCR - -#endif /* CONFIG_4xx & CFG_CMD_SETGETDCR */ - -#endif /* _CMD_DCR_H */ diff --git a/include/cmd_diag.h b/include/cmd_diag.h deleted file mode 100644 index 8834a7feac7..00000000000 --- a/include/cmd_diag.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Diagnostics support - */ -#ifndef _CMD_DIAG_H -#define _CMD_DIAG_H - -#include <common.h> - -#if (CONFIG_COMMANDS & CFG_CMD_DIAG) && defined(CONFIG_POST) -#define CMD_TBL_DIAG MK_CMD_TBL_ENTRY( \ - "diag", 4, CFG_MAXARGS, 0, do_diag, \ - "diag - perform board diagnostics\n", \ - " - print list of available tests\n" \ - "diag [test1 [test2]]\n" \ - " - print information about specified tests\n" \ - "diag run - run all available tests\n" \ - "diag run [test1 [test2]]\n" \ - " - run specified tests\n" \ -), - -int do_diag (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -#else -#define CMD_TBL_DIAG -#endif /* CFG_CMD_DIAG */ - -#endif /* _CMD_DIAG_H */ diff --git a/include/cmd_doc.h b/include/cmd_doc.h deleted file mode 100644 index 07aa864124c..00000000000 --- a/include/cmd_doc.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Disk-On-Chip support - */ -#ifndef _CMD_DOC_H -#define _CMD_DOC_H - -#include <common.h> -#include <command.h> - - -#if (CONFIG_COMMANDS & CFG_CMD_DOC) -#define CMD_TBL_DOC MK_CMD_TBL_ENTRY( \ - "doc", 3, 5, 1, do_doc, \ - "doc - Disk-On-Chip sub-system\n", \ - "info - show available DOC devices\n" \ - "doc device [dev] - show or set current device\n" \ - "doc read addr off size\n" \ - "doc write addr off size - read/write `size'" \ - " bytes starting at offset `off'\n" \ - " to/from memory address `addr'\n" \ - "doc erase off size - erase `size' bytes of DOC from offset `off'\n" \ -), - -#define CMD_TBL_DOCBOOT MK_CMD_TBL_ENTRY( \ - "docboot", 4, 4, 1, do_docboot, \ - "docboot - boot from DOC device\n", \ - "loadAddr dev\n" \ -), - -int do_doc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_docboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#else -#define CMD_TBL_DOC -#define CMD_TBL_DOCBOOT -#endif - -#endif /* _CMD_DOC_H */ diff --git a/include/cmd_dtt.h b/include/cmd_dtt.h deleted file mode 100644 index 57192a3479b..00000000000 --- a/include/cmd_dtt.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * (C) Copyright 2001 - * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Read Digital Thermometers & Thermostats - */ -#ifndef _CMD_DTT_H -#define _CMD_DTT_H - -#if (CONFIG_COMMANDS & CFG_CMD_DTT) - -#define CMD_TBL_DTT MK_CMD_TBL_ENTRY( \ - "dtt", 3, 1, 1, do_dtt, \ - "dtt - Digital Thermometer and Themostat\n", \ - " - Read temperature from digital thermometer and thermostat.\n" \ -), -extern int do_dtt (cmd_tbl_t *, int, int, char *[]); - -#else - -#define CMD_TBL_DTT - -#endif /* (CONFIG_COMMANDS & CFG_CMD_DTT) */ - -#endif /* _CMD_DTT_H */ - diff --git a/include/cmd_eeprom.h b/include/cmd_eeprom.h deleted file mode 100644 index 26d929dc4e3..00000000000 --- a/include/cmd_eeprom.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * EEPROM support - */ -#ifndef _CMD_EEPROM_H -#define _CMD_EEPROM_H - -#include <common.h> -#include <command.h> - -#if (CONFIG_COMMANDS & CFG_CMD_EEPROM) - -#ifdef CFG_I2C_MULTI_EEPROMS -#define CMD_TBL_EEPROM MK_CMD_TBL_ENTRY( \ - "eeprom", 3, 6, 1, do_eeprom, \ - "eeprom - EEPROM sub-system\n", \ - "read devaddr addr off cnt\n" \ - "eeprom write devaddr addr off cnt\n" \ - " - read/write `cnt' bytes from `devaddr` EEPROM at offset `off'\n" \ -), -#else /* One EEPROM */ -#define CMD_TBL_EEPROM MK_CMD_TBL_ENTRY( \ - "eeprom", 3, 5, 1, do_eeprom, \ - "eeprom - EEPROM sub-system\n", \ - "read addr off cnt\n" \ - "eeprom write addr off cnt\n" \ - " - read/write `cnt' bytes at EEPROM offset `off'\n" \ -), -#endif /* CFG_I2C_MULTI_EEPROMS */ -int do_eeprom (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -#else - -#define CMD_TBL_EEPROM - -#endif /* CFG_CMD_EEPROM */ - -#endif /* _CMD_EEPROM_H */ diff --git a/include/cmd_elf.h b/include/cmd_elf.h deleted file mode 100644 index 64c52bc63a6..00000000000 --- a/include/cmd_elf.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Elf Load/Boot Functions - */ -#ifndef _CMD_ELF_H -#define _CMD_ELF_H - -#if (CONFIG_COMMANDS & CFG_CMD_ELF) - -#define CMD_TBL_BOOTELF MK_CMD_TBL_ENTRY( \ - "bootelf", 7, 2, 0, do_bootelf, \ - "bootelf - Boot from an ELF image in memory\n", \ - " [address] - load address of ELF image.\n" \ - ), - -#define CMD_TBL_BOOTVX MK_CMD_TBL_ENTRY( \ - "bootvx", 6, 2, 0, do_bootvx, \ - "bootvx - Boot vxWorks from an ELF image\n", \ - " [address] - load address of vxWorks ELF image.\n" \ - ), - -extern int do_bootelf (cmd_tbl_t *, int, int, char *[]); -extern int do_bootvx (cmd_tbl_t *, int, int, char *[]); - -/* Supporting routines */ -extern int valid_elf_image (unsigned long); -extern unsigned long load_elf_image (unsigned long); - -#else /* ! CFG_CMD_ELF */ - -#define CMD_TBL_BOOTELF -#define CMD_TBL_BOOTVX - -#endif /* CFG_CMD_ELF */ -#endif /* _CMD_ELF_H */ diff --git a/include/cmd_fdc.h b/include/cmd_fdc.h deleted file mode 100644 index f51df1f5a86..00000000000 --- a/include/cmd_fdc.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG, d.peter@mpl.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Floppy support - */ -#ifndef _CMD_FDC_H -#define _CMD_FDC_H - -#include <common.h> -#include <command.h> - - -#if (CONFIG_COMMANDS & CFG_CMD_FDC) - -#define CMD_TBL_FDC MK_CMD_TBL_ENTRY( \ - "fdcboot", 4, 3, 1, do_fdcboot, \ - "fdcboot - boot from floppy device\n", \ - "loadAddr drive\n" \ -), -int do_fdcboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#else -#define CMD_TBL_FDC -#endif - -#endif /* _CMD_FDC_H */ diff --git a/include/cmd_fdos.h b/include/cmd_fdos.h deleted file mode 100644 index a444c7abcf1..00000000000 --- a/include/cmd_fdos.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * (C) Copyright 2002 - * Stäubli Faverges - <www.staubli.com> - * Pierre AUBERT p.aubert@staubli.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Dos floppy support - */ -#ifndef _CMD_FDOS_H -#define _CMD_FDOS_H - -#include <common.h> -#include <command.h> - - -#if (CONFIG_COMMANDS & CFG_CMD_FDOS) - -#define CMD_TBL_FDOS_BOOT MK_CMD_TBL_ENTRY( \ - "fdosboot", 5, 3, 0, do_fdosboot, \ - "fdosboot- boot from a dos floppy file\n", \ - "[loadAddr] [filename]\n" \ -), -#define CMD_TBL_FDOS_LS MK_CMD_TBL_ENTRY( \ - "fdosls", 5, 2, 0, do_fdosls, \ - "fdosls - list files in a directory\n", \ - "[directory]\n" \ -), -int do_fdosboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_fdosls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#else -#define CMD_TBL_FDOS_BOOT -#define CMD_TBL_FDOS_LS -#endif - -#endif /* _CMD_FDOS_H */ diff --git a/include/cmd_flash.h b/include/cmd_flash.h deleted file mode 100644 index 6f5c6cd045d..00000000000 --- a/include/cmd_flash.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * FLASH support - */ -#ifndef _CMD_FLASH_H -#define _CMD_FLASH_H - -#if (CONFIG_COMMANDS & CFG_CMD_FLASH) -#define CMD_TBL_FLINFO MK_CMD_TBL_ENTRY( \ - "flinfo", 3, 2, 1, do_flinfo, \ - "flinfo - print FLASH memory information\n", \ - "\n - print information for all FLASH memory banks\n" \ - "flinfo N\n - print information for FLASH memory bank # N\n" \ -), - -#define CMD_TBL_FLERASE MK_CMD_TBL_ENTRY( \ - "erase", 3, 3, 1, do_flerase, \ - "erase - erase FLASH memory\n", \ - "start end\n" \ - " - erase FLASH from addr 'start' to addr 'end'\n" \ - "erase N:SF[-SL]\n - erase sectors SF-SL in FLASH bank # N\n" \ - "erase bank N\n - erase FLASH bank # N\n" \ - "erase all\n - erase all FLASH banks\n" \ -), - -#define CMD_TBL_PROTECT MK_CMD_TBL_ENTRY( \ - "protect", 4, 4, 1, do_protect, \ - "protect - enable or disable FLASH write protection\n", \ - "on start end\n" \ - " - protect FLASH from addr 'start' to addr 'end'\n" \ - "protect on N:SF[-SL]\n" \ - " - protect sectors SF-SL in FLASH bank # N\n" \ - "protect on bank N\n - protect FLASH bank # N\n" \ - "protect on all\n - protect all FLASH banks\n" \ - "protect off start end\n" \ - " - make FLASH from addr 'start' to addr 'end' writable\n" \ - "protect off N:SF[-SL]\n" \ - " - make sectors SF-SL writable in FLASH bank # N\n" \ - "protect off bank N\n - make FLASH bank # N writable\n" \ - "protect off all\n - make all FLASH banks writable\n" \ -), -int do_flinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_flerase(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_protect(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -#else -#define CMD_TBL_FLINFO -#define CMD_TBL_FLERASE -#define CMD_TBL_PROTECT -#endif /* CFG_CMD_FLASH */ - -#endif /* _CMD_FLASH_H */ diff --git a/include/cmd_fpga.h b/include/cmd_fpga.h deleted file mode 100644 index d74dbce61b4..00000000000 --- a/include/cmd_fpga.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * (C) Copyright 2001 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -/* - * FPGA support - */ -#ifndef _CMD_FPGA_H -#define _CMD_FPGA_H - -#include <common.h> -#include <command.h> - -#if defined(CONFIG_FPGA) && (CONFIG_COMMANDS & CFG_CMD_FPGA) - -#define CMD_TBL_FPGA MK_CMD_TBL_ENTRY( \ - "fpga", 4, 6, 1, do_fpga, \ - "fpga - loadable FPGA image support\n", \ - "fpga [operation type] [device number] [image address] [image size]\n" \ - "fpga operations:\n" \ - "\tinfo\tlist known device information.\n" \ - "\tload\tLoad device from memory buffer.\n" \ - "\tdump\tLoad device to memory buffer.\n" \ -), - -extern int do_fpga (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#else -#define CMD_TBL_FPGA -#endif /* CONFIG_FPGA && CONFIG_COMMANDS & CFG_CMD_FPGA */ - -#endif /* _CMD_FPGA_H */ diff --git a/include/cmd_i2c.h b/include/cmd_i2c.h deleted file mode 100644 index 7334fd4f7ae..00000000000 --- a/include/cmd_i2c.h +++ /dev/null @@ -1,103 +0,0 @@ -/* - * (C) Copyright 2001 - * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * I2C Functions - */ -#ifndef _CMD_I2C_H -#define _CMD_I2C_H - -#if (CONFIG_COMMANDS & CFG_CMD_I2C) -#define CMD_TBL_IMD MK_CMD_TBL_ENTRY( \ - "imd", 3, 4, 1, do_i2c_md, \ - "imd - i2c memory display\n", \ - "chip address[.0, .1, .2] [# of objects]\n - i2c memory display\n" \ -), -#define CMD_TBL_IMM MK_CMD_TBL_ENTRY( \ - "imm", 3, 3, 1, do_i2c_mm, \ - "imm - i2c memory modify (auto-incrementing)\n", \ - "chip address[.0, .1, .2]\n" \ - " - memory modify, auto increment address\n" \ -), -#define CMD_TBL_INM MK_CMD_TBL_ENTRY( \ - "inm", 3, 3, 1, do_i2c_nm, \ - "inm - memory modify (constant address)\n", \ - "chip address[.0, .1, .2]\n - memory modify, read and keep address\n" \ -), -#define CMD_TBL_IMW MK_CMD_TBL_ENTRY( \ - "imw", 3, 5, 1, do_i2c_mw, \ - "imw - memory write (fill)\n", \ - "chip address[.0, .1, .2] value [count]\n - memory write (fill)\n" \ -), -#define CMD_TBL_ICRC MK_CMD_TBL_ENTRY( \ - "icrc32", 4, 5, 1, do_i2c_crc, \ - "icrc32 - checksum calculation\n", \ - "chip address[.0, .1, .2] count\n - compute CRC32 checksum\n" \ -), -#define CMD_TBL_IPROBE MK_CMD_TBL_ENTRY( \ - "iprobe", 3, 1, 1, do_i2c_probe, \ - "iprobe - probe to discover valid I2C chip addresses\n", \ - "\n -discover valid I2C chip addresses\n" \ -), -/* - * Require full name for "iloop" because it is an infinite loop! - */ -#define CMD_TBL_ILOOP MK_CMD_TBL_ENTRY( \ - "iloop", 5, 5, 1, do_i2c_loop, \ - "iloop - infinite loop on address range\n", \ - "chip address[.0, .1, .2] [# of objects]\n" \ - " - loop, reading a set of addresses\n" \ -), -#if (CONFIG_COMMANDS & CFG_CMD_SDRAM) -#define CMD_TBL_ISDRAM MK_CMD_TBL_ENTRY( \ - "isdram", 6, 2, 1, do_sdram, \ - "isdram - print SDRAM configuration information\n", \ - "chip\n - print SDRAM configuration information\n" \ - " (valid chip values 50..57)\n" \ -), -#else -#define CMD_TBL_ISDRAM -#endif - - -int do_i2c_md(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_i2c_mm(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_i2c_nm(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_i2c_mw(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_i2c_crc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_i2c_probe(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_sdram(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#else -#define CMD_TBL_IMD -#define CMD_TBL_IMM -#define CMD_TBL_INM -#define CMD_TBL_IMW -#define CMD_TBL_ICRC -#define CMD_TBL_IPROBE -#define CMD_TBL_ILOOP -#define CMD_TBL_ISDRAM -#endif /* CFG_CMD_MEMORY */ - -#endif /* _CMD_I2C_H */ diff --git a/include/cmd_ide.h b/include/cmd_ide.h deleted file mode 100644 index 0433c20fc76..00000000000 --- a/include/cmd_ide.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * IDE support - */ -#ifndef _CMD_IDE_H -#define _CMD_IDE_H - -#include <common.h> -#include <command.h> - - -#if (CONFIG_COMMANDS & CFG_CMD_IDE) -#define CMD_TBL_IDE MK_CMD_TBL_ENTRY( \ - "ide", 3, 5, 1, do_ide, \ - "ide - IDE sub-system\n", \ - "reset - reset IDE controller\n" \ - "ide info - show available IDE devices\n" \ - "ide device [dev] - show or set current device\n" \ - "ide part [dev] - print partition table of one or all IDE devices\n" \ - "ide read addr blk# cnt\n" \ - "ide write addr blk# cnt - read/write `cnt'" \ - " blocks starting at block `blk#'\n" \ - " to/from memory address `addr'\n" \ -), - -#define CMD_TBL_DISK MK_CMD_TBL_ENTRY( \ - "diskboot", 4, 3, 1, do_diskboot, \ - "diskboot- boot from IDE device\n", \ - "loadAddr dev:part\n" \ -), - -int do_ide (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#else -#define CMD_TBL_IDE -#define CMD_TBL_DISK -#endif - -#endif /* _CMD_IDE_H */ diff --git a/include/cmd_immap.h b/include/cmd_immap.h deleted file mode 100644 index 9febee2f363..00000000000 --- a/include/cmd_immap.h +++ /dev/null @@ -1,181 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * PowerPC 8xx/8260 Internal Memory Map commands - */ -#ifndef _CMD_IMMAP_H -#define _CMD_IMMAP_H - -#if (CONFIG_COMMANDS & CFG_CMD_IMMAP) && \ - (defined(CONFIG_8xx) || defined(CONFIG_8260)) - -#define CMD_TBL_SIUINFO MK_CMD_TBL_ENTRY( \ - "siuinfo", 3, 1, 1, do_siuinfo, \ - "siuinfo - print System Interface Unit (SIU) registers\n", \ - NULL \ -), - -#define CMD_TBL_MEMCINFO MK_CMD_TBL_ENTRY( \ - "memcinfo", 4, 1, 1, do_memcinfo, \ - "memcinfo- print Memory Controller registers\n", \ - NULL \ -), - -#define CMD_TBL_SITINFO MK_CMD_TBL_ENTRY( \ - "sitinfo", 3, 1, 1, do_sitinfo, \ - "sitinfo - print System Integration Timers (SIT) registers\n", \ - NULL \ -), - -#ifdef CONFIG_8260 -#define CMD_TBL_ICINFO MK_CMD_TBL_ENTRY( \ - "icinfo", 3, 1, 1, do_icinfo, \ - "icinfo - print Interrupt Controller registers\n", \ - NULL \ -), -#endif - -#define CMD_TBL_CARINFO MK_CMD_TBL_ENTRY( \ - "carinfo", 3, 1, 1, do_carinfo, \ - "carinfo - print Clocks and Reset registers\n", \ - NULL \ -), - -#define CMD_TBL_IOPINFO MK_CMD_TBL_ENTRY( \ - "iopinfo", 4, 1, 1, do_iopinfo, \ - "iopinfo - print I/O Port registers\n", \ - NULL \ -), - -#define CMD_TBL_IOPSET MK_CMD_TBL_ENTRY( \ - "iopset", 4, 5, 0, do_iopset, \ - "iopset - set I/O Port registers\n", \ - "PORT PIN CMD VALUE\nPORT: A-D, PIN: 0-31, CMD: [dat|dir|odr|sor], VALUE: 0|1" \ -), - -#define CMD_TBL_DMAINFO MK_CMD_TBL_ENTRY( \ - "dmainfo", 3, 1, 1, do_dmainfo, \ - "dmainfo - print SDMA/IDMA registers\n", \ - NULL \ -), - -#define CMD_TBL_FCCINFO MK_CMD_TBL_ENTRY( \ - "fccinfo", 3, 1, 1, do_fccinfo, \ - "fccinfo - print FCC registers\n", \ - NULL \ -), - -#define CMD_TBL_BRGINFO MK_CMD_TBL_ENTRY( \ - "brginfo", 3, 1, 1, do_brginfo, \ - "brginfo - print Baud Rate Generator (BRG) registers\n", \ - NULL \ -), - -#define CMD_TBL_I2CINFO MK_CMD_TBL_ENTRY( \ - "i2cinfo", 4, 1, 1, do_i2cinfo, \ - "i2cinfo - print I2C registers\n", \ - NULL \ -), - -#define CMD_TBL_SCCINFO MK_CMD_TBL_ENTRY( \ - "sccinfo", 3, 1, 1, do_sccinfo, \ - "sccinfo - print SCC registers\n", \ - NULL \ -), - -#define CMD_TBL_SMCINFO MK_CMD_TBL_ENTRY( \ - "smcinfo", 3, 1, 1, do_smcinfo, \ - "smcinfo - print SMC registers\n", \ - NULL \ -), - -#define CMD_TBL_SPIINFO MK_CMD_TBL_ENTRY( \ - "spiinfo", 3, 1, 1, do_spiinfo, \ - "spiinfo - print Serial Peripheral Interface (SPI) registers\n",\ - NULL \ -), - -#define CMD_TBL_MUXINFO MK_CMD_TBL_ENTRY( \ - "muxinfo", 3, 1, 1, do_muxinfo, \ - "muxinfo - print CPM Multiplexing registers\n", \ - NULL \ -), - -#define CMD_TBL_SIINFO MK_CMD_TBL_ENTRY( \ - "siinfo", 3, 1, 1, do_siinfo, \ - "siinfo - print Serial Interface (SI) registers\n", \ - NULL \ -), - -#define CMD_TBL_MCCINFO MK_CMD_TBL_ENTRY( \ - "mccinfo", 3, 1, 1, do_mccinfo, \ - "mccinfo - print MCC registers\n", \ - NULL \ -), - -int do_siuinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_memcinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_sitinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -#ifdef CONFIG_8260 -int do_icinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -#endif -int do_carinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_iopset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_dmainfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_fccinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_brginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_i2cinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_sccinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_smcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_spiinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_muxinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_siinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_mccinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#else - -#define CMD_TBL_SIUINFO -#define CMD_TBL_MEMCINFO -#define CMD_TBL_SITINFO -#ifdef CONFIG_8260 -#define CMD_TBL_ICINFO -#endif -#define CMD_TBL_CARINFO -#define CMD_TBL_IOPINFO -#define CMD_TBL_IOPSET -#define CMD_TBL_DMAINFO -#define CMD_TBL_FCCINFO -#define CMD_TBL_BRGINFO -#define CMD_TBL_I2CINFO -#define CMD_TBL_SCCINFO -#define CMD_TBL_SMCINFO -#define CMD_TBL_SPIINFO -#define CMD_TBL_MUXINFO -#define CMD_TBL_SIINFO -#define CMD_TBL_MCCINFO - -#endif /* CFG_CMD_IMMAP && (CONFIG_8xx || CONFIG_8260) */ - -#endif /* _CMD_IMMAP_H */ diff --git a/include/cmd_jffs2.h b/include/cmd_jffs2.h deleted file mode 100644 index 670455b47a0..00000000000 --- a/include/cmd_jffs2.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * JFFS2 support - */ -#ifndef _CMD_JFFS2_H -#define _CMD_JFFS2_H - -#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) - -#define CMD_TBL_JFFS2_FSLOAD MK_CMD_TBL_ENTRY( \ - "fsload", 5, 3, 0, do_jffs2_fsload, \ - "fsload - load binary file from a filesystem image\n", \ - "[ off ] [ filename ]\n" \ - " - load binary file from flash bank\n" \ - " with offset 'off'\n" \ -), - -#define CMD_TBL_JFFS2_FSINFO MK_CMD_TBL_ENTRY( \ - "fsinfo", 5, 1, 1, do_jffs2_fsinfo, \ - "fsinfo - print information about filesystems\n", \ - " - print information about filesystems\n" \ -), - -#define CMD_TBL_JFFS2_LS MK_CMD_TBL_ENTRY( \ - "ls", 2, 2, 1, do_jffs2_ls, \ - "ls - list files in a directory (default /)\n", \ - "[ directory ]\n" \ - " - list files in a directory.\n" \ -), - -#define CMD_TBL_JFFS2_CHPART MK_CMD_TBL_ENTRY( \ - "chpart", 6, 2, 0, do_jffs2_chpart, \ - "chpart - change active partition\n", \ - " - change active partition\n" \ -), - -int do_jffs2_fsload (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_jffs2_fsinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_jffs2_ls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_jffs2_chpart (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -#else -#define CMD_TBL_JFFS2_FSLOAD -#define CMD_TBL_JFFS2_FSINFO -#define CMD_TBL_JFFS2_LS -#define CMD_TBL_JFFS2_CHPART -#endif /* CFG_CMD_JFFS2 */ - -#endif /* _CMD_JFFS2_H */ diff --git a/include/cmd_kgdb.h b/include/cmd_kgdb.h deleted file mode 100644 index 945c54e8088..00000000000 --- a/include/cmd_kgdb.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * (C) Copyright 2000 - * Murray Jensen <Murray.Jensen@cmst.csiro.au> and - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * KGDB support - */ -#ifndef _CMD_KGDB_H -#define _CMD_KGDB_H - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CMD_TBL_KGDB MK_CMD_TBL_ENTRY( \ - "kgdb", 4, CFG_MAXARGS, 1, do_kgdb, \ - "kgdb - enter gdb remote debug mode\n", \ - "[arg0 arg1 .. argN]\n" \ - " - executes a breakpoint so that kgdb mode is\n" \ - " entered via the exception handler. To return\n" \ - " to the monitor, the remote gdb debugger must\n" \ - " execute a \"continue\" or \"quit\" command.\n" \ - "\n" \ - " if a program is loaded by the remote gdb, any args\n" \ - " passed to the kgdb command are given to the loaded\n" \ - " program if it is executed (see the \"hello_world\"\n" \ - " example program in the U-Boot examples directory)." \ -), - -int do_kgdb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -#else -#define CMD_TBL_KGDB -#endif - -#endif /* _CMD_KGDB_H */ diff --git a/include/cmd_log.h b/include/cmd_log.h deleted file mode 100644 index c879f2f8d5e..00000000000 --- a/include/cmd_log.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * (C) Copyright 2002 - * Detlev Zundel, DENX Software Engineering, dzu@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _CMD_LOG_H_ -#define _CMD_LOG_H_ - -#include <common.h> -#include <command.h> - -#if defined(CONFIG_LOGBUFFER) - -#define LOG_BUF_LEN 16843 -#define LOG_BU_MASK ~(LOG_BUF_LEN-1) - -#define CMD_TBL_LOG MK_CMD_TBL_ENTRY( \ - "log", 3, 255, 1, do_log, \ - "log - manipulate logbuffer\n", \ - "log info - show pointer details\n" \ - "log reset - clear contents\n" \ - "log show - show contents\n" \ - "log append <msg> - append <msg> to the logbuffer\n" \ -), -int do_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#else -#define CMD_TBL_LOG -#endif /* CONFIG_LOGBUFFER */ -/* ----------------------------------------------------------------------------*/ -#endif /* _CMD_LOG_H_ */ diff --git a/include/cmd_mem.h b/include/cmd_mem.h deleted file mode 100644 index aa0c540c105..00000000000 --- a/include/cmd_mem.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Memory Functions - */ -#ifndef _CMD_MEM_H -#define _CMD_MEM_H - -#if (CONFIG_COMMANDS & CFG_CMD_MEMORY) -#define CMD_TBL_MD MK_CMD_TBL_ENTRY( \ - "md", 2, 3, 1, do_mem_md, \ - "md - memory display\n", \ - "[.b, .w, .l] address [# of objects]\n - memory display\n" \ -), -#define CMD_TBL_MM MK_CMD_TBL_ENTRY( \ - "mm", 2, 2, 1, do_mem_mm, \ - "mm - memory modify (auto-incrementing)\n", \ - "[.b, .w, .l] address\n" \ - " - memory modify, auto increment address\n" \ -), -#define CMD_TBL_NM MK_CMD_TBL_ENTRY( \ - "nm", 2, 2, 1, do_mem_nm, \ - "nm - memory modify (constant address)\n", \ - "[.b, .w, .l] address\n - memory modify, read and keep address\n" \ -), -#define CMD_TBL_MW MK_CMD_TBL_ENTRY( \ - "mw", 2, 4, 1, do_mem_mw, \ - "mw - memory write (fill)\n", \ - "[.b, .w, .l] address value [count]\n - write memory\n" \ -), -#define CMD_TBL_CP MK_CMD_TBL_ENTRY( \ - "cp", 2, 4, 1, do_mem_cp, \ - "cp - memory copy\n", \ - "[.b, .w, .l] source target count\n - copy memory\n" \ -), -#define CMD_TBL_CMP MK_CMD_TBL_ENTRY( \ - "cmp", 3, 4, 1, do_mem_cmp, \ - "cmp - memory compare\n", \ - "[.b, .w, .l] addr1 addr2 count\n - compare memory\n" \ -), -#define CMD_TBL_CRC MK_CMD_TBL_ENTRY( \ - "crc32", 3, 4, 1, do_mem_crc, \ - "crc32 - checksum calculation\n", \ - "address count [addr]\n - compute CRC32 checksum [save at addr]\n" \ -), -#define CMD_TBL_BASE MK_CMD_TBL_ENTRY( \ - "base", 2, 2, 1, do_mem_base, \ - "base - print or set address offset\n", \ - "\n - print address offset for memory commands\n" \ - "base off\n - set address offset for memory commands to 'off'\n" \ -), -/* - * Require full name for "loop" and "mtest" because these are infinite loops! - */ -#define CMD_TBL_LOOP MK_CMD_TBL_ENTRY( \ - "loop", 4, 3, 1, do_mem_loop, \ - "loop - infinite loop on address range\n", \ - "[.b, .w, .l] address number_of_objects\n" \ - " - loop on a set of addresses\n" \ -), -#define CMD_TBL_MTEST MK_CMD_TBL_ENTRY( \ - "mtest", 5, 4, 1, do_mem_mtest, \ - "mtest - simple RAM test\n", \ - "[start [end [pattern]]]\n" \ - " - simple RAM read/write test\n" \ -), -int do_mem_md (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_mem_mm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_mem_nm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_mem_mw (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_mem_cp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_mem_cmp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_mem_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_mem_base (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_mem_loop (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#else -#define CMD_TBL_MD -#define CMD_TBL_MM -#define CMD_TBL_NM -#define CMD_TBL_MW -#define CMD_TBL_CP -#define CMD_TBL_CMP -#define CMD_TBL_CRC -#define CMD_TBL_BASE -#define CMD_TBL_LOOP -#define CMD_TBL_MTEST -#endif /* CFG_CMD_MEMORY */ - -#endif /* _CMD_MEM_H */ diff --git a/include/cmd_menu.h b/include/cmd_menu.h deleted file mode 100644 index ad1bd7fdc18..00000000000 --- a/include/cmd_menu.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * (C) Copyright 2001 - * Hans-Jörg Frieden, Hyperion Entertainment - * Hans-JoergF@hyperion-entertainment.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _CMD_MENU_H -#define _CMD_MENU_H - -#include <common.h> -#include <command.h> - -#if defined(CONFIG_AMIGAONEG3SE) && (CONFIG_COMMANDS & CFG_CMD_BSP) -#define CMD_TBL_MENU MK_CMD_TBL_ENTRY( \ - "menu", 3, 1, 1, do_menu, \ - "menu - display BIOS setup menu\n", \ - "" \ -), - -int do_menu( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ); -#else -#define CMD_TBL_MENU -#endif - -#endif /* _CMD_MENU_H */ diff --git a/include/cmd_mii.h b/include/cmd_mii.h deleted file mode 100644 index 7ded0cc93c6..00000000000 --- a/include/cmd_mii.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * (C) Copyright 2001 - * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * MII Functions - */ -#ifndef _CMD_MII_H -#define _CMD_MII_H - -#if (CONFIG_COMMANDS & CFG_CMD_MII) -#define CMD_TBL_MII MK_CMD_TBL_ENTRY( \ - "mii", 3, 5, 1, do_mii, \ - "mii - MII utility commands\n", \ - "\ -info <addr> - display MII PHY info\n\ -mii read <addr> <reg> - read MII PHY <addr> register <reg>\n\ -mii write <addr> <reg> <data> - write MII PHY <addr> register <reg>\n" \ -), - -int do_mii (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#else -#define CMD_TBL_MII -#endif /* CFG_CMD_MII */ - -#endif /* _CMD_MII_H */ diff --git a/include/cmd_misc.h b/include/cmd_misc.h deleted file mode 100644 index 873f5c4320b..00000000000 --- a/include/cmd_misc.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Miscellanious commands - */ -#ifndef _CMD_MISC_H -#define _CMD_MISC_H - -#if (CONFIG_COMMANDS & CFG_CMD_IRQ) -#define CMD_TBL_IRQINFO MK_CMD_TBL_ENTRY( \ - "irqinfo", 3, 1, 1, do_irqinfo, \ - "irqinfo - print information about IRQs\n", \ - NULL \ -), - -/* Implemented in $(CPU)/interrupts.c */ -int do_irqinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#else -#define CMD_TBL_IRQINFO -#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */ - -#if (CONFIG_COMMANDS & CFG_CMD_MISC) -#define CMD_TBL_MISC MK_CMD_TBL_ENTRY( \ - "sleep", 5, 2, 2, do_sleep, \ - "sleep - delay execution for some time\n", \ - "N\n" \ - " - delay execution for N seconds (N is _decimal_ !!!)\n" \ -), - -/* Implemented in common/cmd_misc.c */ -int do_sleep (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -#else -#define CMD_TBL_MISC -#endif /* CFG_CMD_MISC */ - -#endif /* _CMD_MISC_H */ diff --git a/include/cmd_net.h b/include/cmd_net.h deleted file mode 100644 index 842cb3e1543..00000000000 --- a/include/cmd_net.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Network boot support - */ -#ifndef _CMD_NET_H -#define _CMD_NET_H - -#if (CONFIG_COMMANDS & CFG_CMD_NET) -#define CMD_TBL_BOOTP MK_CMD_TBL_ENTRY( \ - "bootp", 5, 3, 1, do_bootp, \ - "bootp - boot image via network using BootP/TFTP protocol\n", \ - "[loadAddress] [bootfilename]\n" \ -), -int do_bootp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -#define CMD_TBL_TFTPB MK_CMD_TBL_ENTRY( \ - "tftpboot", 4, 3, 1, do_tftpb, \ - "tftpboot- boot image via network using TFTP protocol\n" \ - " and env variables ipaddr and serverip\n", \ - "[loadAddress] [bootfilename]\n" \ -), - -int do_tftpb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - - -#define CMD_TBL_RARPB MK_CMD_TBL_ENTRY( \ - "rarpboot", 4, 3, 1, do_rarpb, \ - "rarpboot- boot image via network using RARP/TFTP protocol\n", \ - "[loadAddress] [bootfilename]\n" \ -), - -int do_rarpb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#if (CONFIG_COMMANDS & CFG_CMD_DHCP) -#define CMD_TBL_DHCP MK_CMD_TBL_ENTRY( \ - "dhcp", 4, 3, 1, do_dhcp, \ - "dhcp - invoke DHCP client to obtain IP/boot params\n", \ - "[loadAddress] [bootfilename]\n" \ -), - -int do_dhcp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -#else -#define CMD_TBL_DHCP -#endif /* CFG_CMD_DHCP */ - -#if (CONFIG_COMMANDS & CFG_CMD_PING) -#define CMD_TBL_PING MK_CMD_TBL_ENTRY( \ - "ping", 4, 2, 1, do_ping, \ - "ping - check if host is reachable\n", \ - "host\n" \ -), - -int do_ping (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -#else -#define CMD_TBL_PING -#endif /* CFG_CMD_PING */ - -#else -#define CMD_TBL_BOOTP -#define CMD_TBL_TFTPB -#define CMD_TBL_RARPB -#define CMD_TBL_DHCP -#define CMD_TBL_PING -#endif /* CFG_CMD_NET */ - -#endif diff --git a/include/cmd_nvedit.h b/include/cmd_nvedit.h deleted file mode 100644 index 345127dd9d3..00000000000 --- a/include/cmd_nvedit.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Boot support - */ -#ifndef _CMD_NVEDIT_H -#define _CMD_NVEDIT_H - -#define CMD_TBL_PRINTENV MK_CMD_TBL_ENTRY( \ - "printenv", 4, CFG_MAXARGS, 1, do_printenv, \ - "printenv- print environment variables\n", \ - "\n - print values of all environment variables\n" \ - "printenv name ...\n" \ - " - print value of environment variable 'name'\n" \ -), -int do_printenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#define CMD_TBL_SETENV MK_CMD_TBL_ENTRY( \ - "setenv", 6, CFG_MAXARGS, 0, do_setenv, \ - "setenv - set environment variables\n", \ - "name value ...\n" \ - " - set environment variable 'name' to 'value ...'\n" \ - "setenv name\n" \ - " - delete environment variable 'name'\n" \ -), -int do_setenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#if ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_FLASH)) == (CFG_CMD_ENV|CFG_CMD_FLASH)) -#define CMD_TBL_SAVEENV MK_CMD_TBL_ENTRY( \ - "saveenv", 4, 1, 0, do_saveenv, \ - "saveenv - save environment variables to persistent storage\n", \ - NULL \ -), -int do_saveenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -#else -#define CMD_TBL_SAVEENV -#endif /* CFG_CMD_ENV */ - -#if (CONFIG_COMMANDS & CFG_CMD_ASKENV) -#define CMD_TBL_ASKENV MK_CMD_TBL_ENTRY( \ - "askenv", 8, CFG_MAXARGS, 1, do_askenv, \ - "askenv - get environment variables from stdin\n", \ - "name [message] [size]\n" \ - " - get environment variable 'name' from stdin (max 'size' chars)\n" \ - "askenv name\n" \ - " - get environment variable 'name' from stdin\n" \ - "askenv name size\n" \ - " - get environment variable 'name' from stdin (max 'size' chars)\n" \ - "askenv name [message] size\n" \ - " - display 'message' string and get environment variable 'name'" \ - "from stdin (max 'size' chars)\n" \ -), -int do_askenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -#else -#define CMD_TBL_ASKENV -#endif /* CFG_CMD_ASKENV */ - -#if (CONFIG_COMMANDS & CFG_CMD_RUN) -#define CMD_TBL_RUN MK_CMD_TBL_ENTRY( \ - "run", 3, CFG_MAXARGS, 1, do_run, \ - "run - run commands in an environment variable\n", \ - "var [...]\n" \ - " - run the commands in the environment variable(s) 'var'\n" \ -), -int do_run (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -#else -#define CMD_TBL_RUN -#endif /* CFG_CMD_RUN */ - -#endif /* _CMD_NVEDIT_H */ diff --git a/include/cmd_pci.h b/include/cmd_pci.h deleted file mode 100644 index 520a5c8a137..00000000000 --- a/include/cmd_pci.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * (C) Copyright 2001 - * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * MII Functions - */ -#ifndef _CMD_PCI_H -#define _CMD_PCI_H - -#if (CONFIG_COMMANDS & CFG_CMD_PCI) -#define CMD_TBL_PCI MK_CMD_TBL_ENTRY( \ - "pci", 3, 5, 1, do_pci, \ - "pci - list and access PCI Configuraton Space\n", \ - "[bus] [long]\n" \ - " - short or long list of PCI devices on bus 'bus'\n" \ - "pci header b.d.f\n" \ - " - show header of PCI device 'bus.device.function'\n" \ - "pci display[.b, .w, .l] b.d.f [address] [# of objects]\n" \ - " - display PCI configuration space (CFG)\n" \ - "pci next[.b, .w, .l] b.d.f address\n" \ - " - modify, read and keep CFG address\n" \ - "pci modify[.b, .w, .l] b.d.f address\n" \ - " - modify, auto increment CFG address\n" \ - "pci write[.b, .w, .l] b.d.f address value\n" \ - " - write to CFG address\n" \ -), - -int do_pci (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#else -#define CMD_TBL_PCI -#endif /* CFG_CMD_PCI */ - -#endif /* _CMD_PCI_H */ diff --git a/include/cmd_pcmcia.h b/include/cmd_pcmcia.h deleted file mode 100644 index 24a207bd08a..00000000000 --- a/include/cmd_pcmcia.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * PCMCIA support - */ -#ifndef _CMD_PCMCIA_H -#define _CMD_PCMCIA_H - -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) -#define CMD_TBL_PINIT MK_CMD_TBL_ENTRY( \ - "pinit", 4, 2, 1, do_pinit, \ - "pinit - PCMCIA sub-system\n", \ - "on - power on PCMCIA socket\n" \ - "pinit off - power off PCMCIA socket\n" \ -), - -int do_pinit (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -#else -#define CMD_TBL_PINIT -#endif - -#endif /* _CMD_PCMCIA_H */ - diff --git a/include/cmd_reginfo.h b/include/cmd_reginfo.h deleted file mode 100644 index 8d71e7edd0e..00000000000 --- a/include/cmd_reginfo.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * (C) Copyright 2000 - * Subodh Nijsure, SkyStream Networks, snijsure@skystream.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _CMD_REGINFO_H_ -#define _CMD_REGINFO_H_ - -#if (defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_405GP) || defined(CONFIG_405EP)) && \ - (CONFIG_COMMANDS & CFG_CMD_REGINFO) -#define CMD_TBL_REGINFO MK_CMD_TBL_ENTRY( \ - "reginfo", 3, 2, 1, do_reginfo, \ - "reginfo - print register information\n", \ -), - -int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#else -#define CMD_TBL_REGINFO -#endif /* CONFIG_COMMANDS && CFG_CMD_REGINFO */ - -#endif /* _CMD_REGINFO_H_ */ diff --git a/include/cmd_rtc.h b/include/cmd_rtc.h deleted file mode 100644 index 2149f783525..00000000000 --- a/include/cmd_rtc.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _CMD_RTC_H_ -#define _CMD_RTC_H_ - -#include <common.h> -#include <command.h> - -#if (CONFIG_COMMANDS & CFG_CMD_DATE) - -#define CMD_TBL_DATE MK_CMD_TBL_ENTRY( \ - "date", 3, 2, 1, do_date, \ - "date - get/set/reset date & time\n", \ - "[MMDDhhmm[[CC]YY][.ss]]\ndate reset\n" \ - " - without arguments: print date & time\n" \ - " - with numeric argument: set the system date & time\n" \ - " - with 'reset' argument: reset the RTC\n" \ -), - -int do_date (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#else - -#define CMD_TBL_DATE - -#endif /* CFG_CMD_DATE */ - - -#endif /* _CMD_RTC_H_ */ diff --git a/include/cmd_scsi.h b/include/cmd_scsi.h deleted file mode 100644 index 4dca059abbc..00000000000 --- a/include/cmd_scsi.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ -#ifndef _CMD_SCSI_H -#define _CMD_SCSI_H - -#include <common.h> -#include <command.h> - - -#if (CONFIG_COMMANDS & CFG_CMD_SCSI) - -#define CMD_TBL_SCSI MK_CMD_TBL_ENTRY( \ - "scsi", 4, 5, 1, do_scsi, \ - "scsi - SCSI sub-system\n", \ - "reset - reset SCSI controller\n" \ - "scsi info - show available SCSI devices\n" \ - "scsi scan - (re-)scan SCSI bus\n" \ - "scsi device [dev] - show or set current device\n" \ - "scsi part [dev] - print partition table of one or all SCSI devices\n" \ - "scsi read addr blk# cnt - read `cnt' blocks starting at block `blk#'\n"\ - " to memory address `addr'\n" \ -), - - -#define CMD_TBL_SCSIBOOT MK_CMD_TBL_ENTRY( \ - "scsiboot", 5, 3, 1, do_scsiboot, \ - "scsiboot- boot from SCSI device\n", \ - "loadAddr dev:part\n" \ -), - -int do_scsi (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_scsiboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - - -#else -#define CMD_TBL_SCSI -#define CMD_TBL_SCSIBOOT -#endif - -#endif /* _CMD_SCSI_H */ - diff --git a/include/cmd_spi.h b/include/cmd_spi.h deleted file mode 100644 index 30927c15191..00000000000 --- a/include/cmd_spi.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * (C) Copyright 2002 - * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * SPI Functions - */ -#ifndef _CMD_SPI_H -#define _CMD_SPI_H - -#if (CONFIG_COMMANDS & CFG_CMD_SPI) -#define CMD_TBL_SPI MK_CMD_TBL_ENTRY( \ - "sspi", 3, 5, 1, do_spi, \ - "sspi - SPI utility commands\n", \ - "\ -<device> <bit_len> <dout> - Send <bit_len> bits from <dout> out the SPI\n\ - <device> - Identifies the chip select of the device\n\ - <bit_len> - Number of bits to send (base 10)\n\ - <dout> - Hexadecimal string that gets sent\n" \ -), - -int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - -#else -#define CMD_TBL_SPI -#endif /* CFG_CMD_SPI */ - -#endif /* _CMD_SPI_H */ diff --git a/include/cmd_usb.h b/include/cmd_usb.h deleted file mode 100644 index b7b4e831b55..00000000000 --- a/include/cmd_usb.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ -#ifndef _CMD_USB_H -#define _CMD_USB_H - -#include <common.h> -#include <command.h> - - -#if (CONFIG_COMMANDS & CFG_CMD_USB) - -#ifdef CONFIG_USB_STORAGE -#define CMD_TBL_USB MK_CMD_TBL_ENTRY( \ - "usb", 4, 5, 1, do_usb, \ - "usb - USB sub-system\n", \ - "reset - reset (rescan) USB controller\n" \ - "usb stop [f] - stop USB [f]=force stop\n" \ - "usb tree - show USB device tree\n" \ - "usb info [dev] - show available USB devices\n" \ - "usb scan - (re-)scan USB bus for storage devices\n" \ - "usb device [dev] - show or set current USB storage device\n" \ - "usb part [dev] - print partition table of one or all USB storage devices\n" \ - "usb read addr blk# cnt - read `cnt' blocks starting at block `blk#'\n"\ - " to memory address `addr'\n" \ -), - - -#define CMD_TBL_USBBOOT MK_CMD_TBL_ENTRY( \ - "usbboot", 5, 3, 1, do_usbboot, \ - "usbboot - boot from USB device\n", \ - "loadAddr dev:part\n" \ -), - -#else -#define CMD_TBL_USB MK_CMD_TBL_ENTRY( \ - "usb", 4, 5, 1, do_usb, \ - "usb - USB sub-system\n", \ - "reset - reset (rescan) USB controller\n" \ - "usb tree - show USB device tree\n" \ - "usb info [dev] - show available USB devices\n" \ -), - -#define CMD_TBL_USBBOOT -#endif - -int do_usb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_usbboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - - -#else -#define CMD_TBL_USB -#define CMD_TBL_USBBOOT -#endif - -#endif /* _CMD_USB_H */ - diff --git a/include/cmd_vfd.h b/include/cmd_vfd.h deleted file mode 100644 index ad6f21afb05..00000000000 --- a/include/cmd_vfd.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Miscellanious commands - */ -#ifndef _CMD_VFD_H -#define _CMD_VFD_H - -#if (CONFIG_COMMANDS & CFG_CMD_VFD) -#define CMD_TBL_VFD MK_CMD_TBL_ENTRY( \ - "vfd", 3, 2, 0, do_vfd, \ - "vfd - load a bitmap to the VFDs on TRAB\n", \ - "#N\n" \ - " - load bitmap no. N to the VFDs (N is _decimal_ !!!)\n" \ - "vfd addr\n" \ - " - load bitmap at address _addr_ to the VFDs\n" \ -), - -/* Implemented in common/cmd_misc.c */ -int do_vfd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -#else -#define CMD_TBL_VFD -#endif /* CFG_CMD_VFD */ - -#endif /* _CMD_VFD_H */ diff --git a/include/command.h b/include/command.h index 9453c0d1c0a..a39c12f9afe 100644 --- a/include/command.h +++ b/include/command.h @@ -38,9 +38,9 @@ struct cmd_tbl_s { char *name; /* Command Name */ - int lmin; /* minimum abbreviated length */ int maxargs; /* maximum number of arguments */ int repeatable; /* autorepeat allowed? */ + /* Implementation function */ int (*cmd)(struct cmd_tbl_s *, int, int, char *[]); char *usage; /* Usage message (short) */ @@ -51,15 +51,9 @@ struct cmd_tbl_s { typedef struct cmd_tbl_s cmd_tbl_t; -extern cmd_tbl_t cmd_tbl[]; +extern cmd_tbl_t __u_boot_cmd_start; +extern cmd_tbl_t __u_boot_cmd_end; -#ifdef CFG_LONGHELP -#define MK_CMD_TBL_ENTRY(name,lmin,maxargs,rep,cmd,usage,help) \ - { name, lmin, maxargs, rep, cmd, usage, help } -#else /* no help info */ -#define MK_CMD_TBL_ENTRY(name,lmin,maxargs,rep,cmd,usage,help) \ - { name, lmin, maxargs, rep, cmd, usage } -#endif /* common/command.c */ cmd_tbl_t *find_cmd(const char *cmd); @@ -87,4 +81,20 @@ typedef void command_t (cmd_tbl_t *, int, int, char *[]); * to include/cmd_confdefs.h */ + +#define Struct_Section __attribute__ ((unused,section (".u_boot_cmd"))) +#define U_BOOT_CMD(x) __u_boot_cmd_##x Struct_Section + +#ifdef CFG_LONGHELP + +#define MK_CMD_ENTRY(name,maxargs,rep,cmd,usage,help) \ + { name, maxargs, rep, cmd, usage, help } + +#else /* no long help info */ + +#define MK_CMD_ENTRY(name,maxargs,rep,cmd,usage,help) \ + { name, maxargs, rep, cmd, usage } + +#endif /* CFG_LONGHELP */ + #endif /* __COMMAND_H */ diff --git a/include/common.h b/include/common.h index cc5dbe7f89a..0bb43533c62 100644 --- a/include/common.h +++ b/include/common.h @@ -167,7 +167,7 @@ void setenv (char *, char *); # include <asm/u-boot-arm.h> /* ARM version to be fixed! */ #endif /* CONFIG_ARM */ #ifdef CONFIG_I386 /* x86 version to be fixed! */ -# include <asm/u-boot-i386.h> +# include <asm/u-boot-i386.h> #endif /* CONFIG_I386 */ void pci_init (void); diff --git a/include/commproc.h b/include/commproc.h index c10525d4e87..652d2ab9138 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -1177,8 +1177,8 @@ typedef struct scc_enet { # endif /* CONFIG_FEC_ENET */ #endif /* CONFIG_SVM_SC8xx */ - - + + #if defined(CONFIG_NETVIA) /* Bits in parallel I/O port registers that have to be set/cleared * to configure the pins for SCC2 use. diff --git a/include/configs/A3000.h b/include/configs/A3000.h index f933ea8de38..b25e48cf89d 100644 --- a/include/configs/A3000.h +++ b/include/configs/A3000.h @@ -106,7 +106,7 @@ /* #define CONFIG_TULIP */ /* #define CONFIG_EEPRO100 */ -#define CONFIG_NATSEMI +#define CONFIG_NATSEMI #define PCI_ENET0_IOADDR 0x80000000 #define PCI_ENET0_MEMADDR 0x80000000 @@ -319,6 +319,4 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ - - #endif /* __CONFIG_H */ diff --git a/include/configs/ADCIOP.h b/include/configs/ADCIOP.h index 92b4482cb66..255942aabd9 100644 --- a/include/configs/ADCIOP.h +++ b/include/configs/ADCIOP.h @@ -89,7 +89,7 @@ /* The following table includes the supported baudrates */ #define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 } + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 } #define CFG_LOAD_ADDR 0x100000 /* default load address */ diff --git a/include/configs/AR405.h b/include/configs/AR405.h index acb2fb678c7..632d3999fff 100644 --- a/include/configs/AR405.h +++ b/include/configs/AR405.h @@ -67,7 +67,7 @@ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_COMMANDS \ - (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_ASKENV) + (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_ASKENV) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> @@ -99,8 +99,8 @@ /* The following table includes the supported baudrates */ #define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } #define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ @@ -120,7 +120,7 @@ #define CONFIG_PCI /* include pci support */ #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ + /* resource configuration */ #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h index 4be6158d89b..38689972087 100644 --- a/include/configs/ASH405.h +++ b/include/configs/ASH405.h @@ -117,8 +117,8 @@ /* The following table includes the supported baudrates */ #define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } #define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ @@ -175,7 +175,7 @@ #define CONFIG_PCI /* include pci support */ #define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ #undef CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ + /* resource configuration */ #undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ @@ -239,7 +239,7 @@ #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ #define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ #define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ + /* total size of a CAT24WC16 is 2048 bytes */ #define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ #define CFG_NVRAM_SIZE 242 /* NVRAM size */ @@ -265,7 +265,7 @@ * Cache Configuration */ #define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ + /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/AmigaOneG3SE.h b/include/configs/AmigaOneG3SE.h index 009636b36ab..99b42e9a6d5 100644 --- a/include/configs/AmigaOneG3SE.h +++ b/include/configs/AmigaOneG3SE.h @@ -146,7 +146,7 @@ /* Size in bytes reserved for initial data */ /* HJF: used to be 0x400000 */ -#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_ADDR 0x40000000 #define CFG_INIT_RAM_END 0x8000 #define CFG_GBL_DATA_SIZE 128 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) @@ -180,9 +180,9 @@ #define CFG_IBAT1L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT1U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) /* HJF: -#define CFG_IBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR) | BATL_PP_RW) +#define CFG_IBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR) | BATL_PP_RW) #define CFG_IBAT1U ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR) | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_DBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR + 0x20000) | BATL_PP_RW ) +#define CFG_DBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR + 0x20000) | BATL_PP_RW ) #define CFG_DBAT1U ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR + 0x20000) | BATU_BL_256M | BATU_VS | BATU_VP) */ @@ -191,9 +191,9 @@ #define CFG_DBAT2L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) #define CFG_DBAT2U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) /* This used to be commented out */ -#define CFG_IBAT2L CFG_DBAT2L +#define CFG_IBAT2L CFG_DBAT2L /* This here too */ -#define CFG_IBAT2U CFG_DBAT2U +#define CFG_IBAT2U CFG_DBAT2U /* I/O and PCI memory at 0xf0000000 diff --git a/include/configs/BAB7xx.h b/include/configs/BAB7xx.h index d312e6b5570..5dd7a7e9f7c 100644 --- a/include/configs/BAB7xx.h +++ b/include/configs/BAB7xx.h @@ -71,8 +71,8 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 |\ - CFG_CMD_SCSI | CFG_CMD_IDE | CFG_CMD_DATE |\ - CFG_CMD_FDC | CFG_CMD_ELF) + CFG_CMD_SCSI | CFG_CMD_IDE | CFG_CMD_DATE |\ + CFG_CMD_FDC | CFG_CMD_ELF) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> @@ -319,14 +319,14 @@ extern unsigned char scsi_sym53c8xx_ccf; #define CFG_NS87308 /* Nat Semi super-io cntr on ISA bus */ #define CFG_NS87308_BADDR_10 1 #define CFG_NS87308_DEVS (CFG_NS87308_UART1 | \ - CFG_NS87308_UART2 | \ - CFG_NS87308_KBC1 | \ - CFG_NS87308_MOUSE | \ - CFG_NS87308_FDC | \ - CFG_NS87308_RARP | \ - CFG_NS87308_GPIO | \ - CFG_NS87308_POWRMAN | \ - CFG_NS87308_RTC_APC ) + CFG_NS87308_UART2 | \ + CFG_NS87308_KBC1 | \ + CFG_NS87308_MOUSE | \ + CFG_NS87308_FDC | \ + CFG_NS87308_RARP | \ + CFG_NS87308_GPIO | \ + CFG_NS87308_POWRMAN | \ + CFG_NS87308_RTC_APC ) #define CFG_NS87308_PS2MOD #define CFG_NS87308_GPIO_BASE 0x0220 @@ -431,7 +431,7 @@ extern unsigned long bab7xx_get_gclk_freq (void); */ #undef CFG_L2 #define L2_INIT (L2CR_L2SIZ_HM | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) + L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) #define L2_ENABLE (L2_INIT | L2CR_L2E) #define CFG_L2_BAB7xx diff --git a/include/configs/BUBINGA405EP.h b/include/configs/BUBINGA405EP.h index f776a322918..99fcbae1690 100644 --- a/include/configs/BUBINGA405EP.h +++ b/include/configs/BUBINGA405EP.h @@ -32,7 +32,6 @@ /*#define __DEBUG_START_FROM_SRAM__ */ - /* * High Level Configuration Options * (easy to change) @@ -220,7 +219,7 @@ #define CONFIG_PCI /* include pci support */ #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ + /* resource configuration */ #define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ #define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ diff --git a/include/configs/CANBT.h b/include/configs/CANBT.h index 9b8bd05fb8f..7aceb582b84 100644 --- a/include/configs/CANBT.h +++ b/include/configs/CANBT.h @@ -59,7 +59,7 @@ #define CONFIG_COMMANDS (( CONFIG_CMD_DFL | \ CFG_CMD_IRQ | \ CFG_CMD_EEPROM ) & \ - ~CFG_CMD_NET) + ~CFG_CMD_NET) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> @@ -91,8 +91,8 @@ /* The following table includes the supported baudrates */ #define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } #define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ @@ -153,7 +153,7 @@ #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ #define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ #define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */ - /* total size of a CAT24WC08 is 1024 bytes */ + /* total size of a CAT24WC08 is 1024 bytes */ #endif /*----------------------------------------------------------------------- diff --git a/include/configs/CCM.h b/include/configs/CCM.h index 0fb24dbf97c..ba15e91bffb 100644 --- a/include/configs/CCM.h +++ b/include/configs/CCM.h @@ -60,10 +60,10 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND "setenv bootargs " \ - "mem=$(mem) " \ - "root=/dev/ram rw ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off " \ - "wt_8xx=timeout:3600; " \ - "bootm" + "mem=$(mem) " \ + "root=/dev/ram rw ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off " \ + "wt_8xx=timeout:3600; " \ + "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index d7fbe2e1ecc..4be94ed854d 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -46,10 +46,10 @@ #if 0 #define CONFIG_PREBOOT \ - "crc32 f0207004 ffc 0;" \ - "if cmp 0 f0207000 1;" \ - "then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;" \ - "else;echo Old CRC is bad;fi" + "crc32 f0207004 ffc 0;" \ + "if cmp 0 f0207000 1;" \ + "then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;" \ + "else;echo Old CRC is bad;fi" #endif #undef CONFIG_BOOTARGS @@ -128,8 +128,8 @@ /* The following table includes the supported baudrates */ #define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } #define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ @@ -149,7 +149,7 @@ #define CONFIG_PCI /* include pci support */ #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ + /* resource configuration */ #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ @@ -240,7 +240,7 @@ #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ #define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ #define CFG_ENV_SIZE 0x200 /* 512 bytes may be used for env vars */ - /* total size of a CAT24WC08 is 1024 bytes */ + /* total size of a CAT24WC08 is 1024 bytes */ #endif /*----------------------------------------------------------------------- diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index 2671b5f1970..1f9d39c606a 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -47,10 +47,10 @@ #if 0 #define CONFIG_PREBOOT \ - "crc32 f0207004 ffc 0;" \ - "if cmp 0 f0207000 1;" \ - "then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;" \ - "else;echo Old CRC is bad;fi" + "crc32 f0207004 ffc 0;" \ + "if cmp 0 f0207000 1;" \ + "then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;" \ + "else;echo Old CRC is bad;fi" #endif #undef CONFIG_BOOTARGS @@ -135,8 +135,8 @@ /* The following table includes the supported baudrates */ #define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } #define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ @@ -160,7 +160,7 @@ #define CONFIG_PCI /* include pci support */ #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ + /* resource configuration */ #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ @@ -251,7 +251,7 @@ #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ #define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ #define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ + /* total size of a CAT24WC16 is 2048 bytes */ #endif #define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ @@ -279,7 +279,7 @@ * Cache Configuration */ #define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ + /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index de55e87694c..00adfd5998a 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -48,10 +48,10 @@ #if 0 #define CONFIG_PREBOOT \ - "crc32 f0207004 ffc 0;" \ - "if cmp 0 f0207000 1;" \ - "then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;" \ - "else;echo Old CRC is bad;fi" + "crc32 f0207004 ffc 0;" \ + "if cmp 0 f0207000 1;" \ + "then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;" \ + "else;echo Old CRC is bad;fi" #endif #undef CONFIG_BOOTARGS @@ -123,8 +123,8 @@ /* The following table includes the supported baudrates */ #define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } #define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ @@ -148,7 +148,7 @@ #define CONFIG_PCI /* include pci support */ #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ + /* resource configuration */ #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ @@ -239,7 +239,7 @@ #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ #define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ #define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars*/ - /* total size of a CAT24WC08 is 1024 bytes */ + /* total size of a CAT24WC08 is 1024 bytes */ #endif #define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ @@ -267,7 +267,7 @@ * Cache Configuration */ #define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ + /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/CPCIISER4.h b/include/configs/CPCIISER4.h index 174b0e51fba..bcda6998cc7 100644 --- a/include/configs/CPCIISER4.h +++ b/include/configs/CPCIISER4.h @@ -90,8 +90,8 @@ /* The following table includes the supported baudrates */ #define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } #define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ @@ -111,7 +111,7 @@ #define CONFIG_PCI /* include pci support */ #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ + /* resource configuration */ #define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ #define CFG_PCI_SUBSYS_DEVICEID 0x0404 /* PCI Device ID: CPCI-ISER4 */ @@ -181,7 +181,7 @@ #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ #define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ #define CFG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */ - /* total size of a CAT24WC08 is 1024 bytes */ + /* total size of a CAT24WC08 is 1024 bytes */ /*----------------------------------------------------------------------- * Cache Configuration diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h index 9712d479c17..390b796ada1 100644 --- a/include/configs/CPU86.h +++ b/include/configs/CPU86.h @@ -361,7 +361,7 @@ * HID1 has only read-only information - nothing to set. */ #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\ - HID0_DCI|HID0_IFEM|HID0_ABE) + HID0_DCI|HID0_IFEM|HID0_ABE) #define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) #define CFG_HID2 0 @@ -394,10 +394,10 @@ */ #if defined(CONFIG_WATCHDOG) #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) + SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) #else #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) + SYPCR_SWRI|SYPCR_SWP) #endif /* CONFIG_WATCHDOG */ /*----------------------------------------------------------------------- @@ -498,55 +498,55 @@ /* Bank 0 - Boot ROM */ #define CFG_BR0_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) #define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxU_EHTR_8IDLE) + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_3_CLK |\ + ORxU_EHTR_8IDLE) /* Bank 1 - FLASH */ #define CFG_BR1_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_GPCM_P |\ - BRx_V) + BRx_PS_64 |\ + BRx_MS_GPCM_P |\ + BRx_V) #define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxU_EHTR_8IDLE) + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_3_CLK |\ + ORxU_EHTR_8IDLE) #else /* CONFIG_BOOT_ROM */ /* Bank 0 - FLASH */ #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_GPCM_P |\ - BRx_V) + BRx_PS_64 |\ + BRx_MS_GPCM_P |\ + BRx_V) #define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxU_EHTR_8IDLE) + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_3_CLK |\ + ORxU_EHTR_8IDLE) /* Bank 1 - Boot ROM */ #define CFG_BR1_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) #define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxU_EHTR_8IDLE) + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_3_CLK |\ + ORxU_EHTR_8IDLE) #endif /* CONFIG_BOOT_ROM */ @@ -555,9 +555,9 @@ */ #ifndef CFG_RAMBOOT #define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) #define CFG_OR2_PRELIM CFG_OR2_9COL @@ -567,88 +567,88 @@ /* Bank 3 - Dual Ported SRAM */ #define CFG_BR3_PRELIM ((CFG_DPSRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_16 |\ - BRx_MS_GPCM_P |\ - BRx_V) + BRx_PS_16 |\ + BRx_MS_GPCM_P |\ + BRx_V) #define CFG_OR3_PRELIM (P2SZ_TO_AM(CFG_DPSRAM_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_SETA) + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_5_CLK |\ + ORxG_SETA) /* Bank 4 - DiskOnChip */ #define CFG_BR4_PRELIM ((CFG_DOC_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) #define CFG_OR4_PRELIM (P2SZ_TO_AM(CFG_DOC_SIZE) |\ - ORxG_ACS_DIV2 |\ - ORxG_SCY_5_CLK |\ - ORxU_EHTR_8IDLE) + ORxG_ACS_DIV2 |\ + ORxG_SCY_5_CLK |\ + ORxU_EHTR_8IDLE) /* Bank 5 - FDC37C78 controller */ #define CFG_BR5_PRELIM ((CFG_FDC37C78_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) #define CFG_OR5_PRELIM (P2SZ_TO_AM(CFG_FDC37C78_SIZE) |\ - ORxG_ACS_DIV2 |\ - ORxG_SCY_8_CLK |\ - ORxU_EHTR_8IDLE) + ORxG_ACS_DIV2 |\ + ORxG_SCY_8_CLK |\ + ORxU_EHTR_8IDLE) /* Bank 6 - Board control registers */ #define CFG_BR6_PRELIM ((CFG_BCRS_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) #define CFG_OR6_PRELIM (P2SZ_TO_AM(CFG_BCRS_SIZE) |\ - ORxG_CSNT |\ - ORxG_SCY_5_CLK) + ORxG_CSNT |\ + ORxG_SCY_5_CLK) /* Bank 7 - VME Extended Access Range */ #define CFG_BR7_PRELIM ((CFG_VMEEAR_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_GPCM_P |\ - BRx_V) + BRx_PS_32 |\ + BRx_MS_GPCM_P |\ + BRx_V) #define CFG_OR7_PRELIM (P2SZ_TO_AM(CFG_VMEEAR_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_SETA) + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_5_CLK |\ + ORxG_SETA) /* Bank 8 - VME Standard Access Range */ #define CFG_BR8_PRELIM ((CFG_VMESAR_BASE & BRx_BA_MSK) |\ - BRx_PS_16 |\ - BRx_MS_GPCM_P |\ - BRx_V) + BRx_PS_16 |\ + BRx_MS_GPCM_P |\ + BRx_V) #define CFG_OR8_PRELIM (P2SZ_TO_AM(CFG_VMESAR_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_SETA) + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_5_CLK |\ + ORxG_SETA) /* Bank 9 - VME Short I/O Access Range */ #define CFG_BR9_PRELIM ((CFG_VMESIOAR_BASE & BRx_BA_MSK) |\ - BRx_PS_16 |\ - BRx_MS_GPCM_P |\ - BRx_V) + BRx_PS_16 |\ + BRx_MS_GPCM_P |\ + BRx_V) #define CFG_OR9_PRELIM (P2SZ_TO_AM(CFG_VMESIOAR_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_SETA) + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_5_CLK |\ + ORxG_SETA) #endif /* __CONFIG_H */ diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h index 1bd6899bff9..fd8594493b8 100644 --- a/include/configs/CRAYL1.h +++ b/include/configs/CRAYL1.h @@ -46,7 +46,7 @@ /* set PRAM to keep U-Boot out, mem= to keep linux out, and initrd_hi to * keep possible initrd ramdisk decompression out. This is in k (1024 bytes) - #define CONFIG_PRAM 16 + #define CONFIG_PRAM 16 */ #define CONFIG_LOADADDR 0x100000 /* where TFTP images go */ #undef CONFIG_BOOTARGS @@ -56,10 +56,10 @@ #define CFG_AUTOLOAD "no" #define CONFIG_BOOTCOMMAND "dhcp" -/* +/* * ..during experiments.. #define CONFIG_SERVERIP 10.0.0.1 - #define CONFIG_ETHADDR 00:40:a6:80:14:5 + #define CONFIG_ETHADDR 00:40:a6:80:14:5 */ #define CONFIG_HARD_I2C 1 /* hardware support for i2c */ #define CONFIG_SDRAM_BANK0 1 @@ -108,13 +108,13 @@ CONFIG_BOOTP_BOOTFILESIZE|\ CONFIG_BOOTP_BOOTPATH) -/* +/* * how many time to fail & restart a net-TFTP before giving up & resetting * the board hoping that a reset of net interface might help.. */ #define CONFIG_NET_RESET 5 -/* +/* * bauds. Just to make it compile; in our case, I read the base_baud * from the DCR anyway, so its kinda-tied to the above ref. clock which in turn * drives the system clock. @@ -168,7 +168,7 @@ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ /* BEG ENVIRONNEMENT FLASH: needs to be a whole FlashSector */ -#define CFG_ENV_OFFSET 0x3c8000 +#define CFG_ENV_OFFSET 0x3c8000 #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ #define CFG_ENV_SIZE 0x1000 /* Total Size of Environment area */ #define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ @@ -184,15 +184,15 @@ #define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */ #define CFG_MALLOC_LEN (128 << 10) /* 128k for malloc space */ #define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \ - + CFG_MALLOC_LEN \ - + CFG_ENV_SECT_SIZE \ - + CFG_STACK_USAGE ) + + CFG_MALLOC_LEN \ + + CFG_ENV_SECT_SIZE \ + + CFG_STACK_USAGE ) #define CFG_MEMTEST_END (CFG_SDRAM_SIZE * 1024 * 1024 - CFG_MEM_END_USAGE) /* END ENVIRONNEMENT FLASH */ /*----------------------------------------------------------------------- - * Cache Configuration. Only used to ..?? clear it, I guess.. + * Cache Configuration. Only used to ..?? clear it, I guess.. */ #define CFG_DCACHE_SIZE 16384 #define CFG_CACHELINE_SIZE 32 diff --git a/include/configs/DASA_SIM.h b/include/configs/DASA_SIM.h index 229e4587d07..30e978cdaa6 100644 --- a/include/configs/DASA_SIM.h +++ b/include/configs/DASA_SIM.h @@ -98,7 +98,7 @@ /* The following table includes the supported baudrates */ #define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 } + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 } #define CFG_LOAD_ADDR 0x100000 /* default load address */ diff --git a/include/configs/DU405.h b/include/configs/DU405.h index bac6221194e..3e5fc3fd441 100644 --- a/include/configs/DU405.h +++ b/include/configs/DU405.h @@ -97,8 +97,8 @@ /* The following table includes the supported baudrates */ #define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } #define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ @@ -118,7 +118,7 @@ #define CONFIG_PCI /* include pci support */ #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ + /* resource configuration */ #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ @@ -210,7 +210,7 @@ #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ #define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ #define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */ - /* total size of a CAT24WC08 is 1024 bytes */ + /* total size of a CAT24WC08 is 1024 bytes */ /*----------------------------------------------------------------------- * Cache Configuration diff --git a/include/configs/ELPPC.h b/include/configs/ELPPC.h index 54cdd23f234..7176905a365 100644 --- a/include/configs/ELPPC.h +++ b/include/configs/ELPPC.h @@ -319,7 +319,7 @@ #define L2_INIT 0 /* cpu 750 CXe*/ #else #define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) + L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) #endif #define L2_ENABLE (L2_INIT | L2CR_L2E) diff --git a/include/configs/ELPT860.h b/include/configs/ELPT860.h index e9561b9eb4a..2f253b97879 100644 --- a/include/configs/ELPT860.h +++ b/include/configs/ELPT860.h @@ -64,20 +64,20 @@ "echo Type \"run nfsboot\" to mount root filesystem over NFS;" \ "echo" -#undef CONFIG_BOOTARGS +#undef CONFIG_BOOTARGS #define CONFIG_EXTRA_ENV_SETTINGS \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ "rootargs=setenv rootpath /tftp/$(ipaddr)\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=$(serverip):$(rootpath)\0" \ "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):eth0:off panic=1\0" \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ + ":$(hostname):eth0:off panic=1\0" \ "ramboot=tftp 400000 /home/paugaml/pMulti;" \ - "run ramargs;bootm\0" \ + "run ramargs;bootm\0" \ "nfsboot=tftp 400000 /home/paugaml/uImage;" \ - "run rootargs;run nfsargs;run addip;bootm\0" \ + "run rootargs;run nfsargs;run addip;bootm\0" \ "" #define CONFIG_BOOTCOMMAND "run ramboot" @@ -92,8 +92,8 @@ #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE ) + CFG_CMD_ASKENV | \ + CFG_CMD_DATE ) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> @@ -212,7 +212,7 @@ */ #define CFG_NVRAM_BASE_ADDR CFG_NVRAM_BASE /* Base address of NVRAM area */ #define CFG_NVRAM_SIZE ((128*1024)-8) /* clock regs resident in the */ - /* 8 top NVRAM locations */ + /* 8 top NVRAM locations */ #if defined(CFG_ENV_IS_IN_NVRAM) # define CFG_ENV_ADDR CFG_NVRAM_BASE /* Base address of NVRAM area */ @@ -236,10 +236,10 @@ */ #if defined(CONFIG_WATCHDOG) # define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP) + SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP) #else # define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWP) + SYPCR_SWP) #endif /*----------------------------------------------------------------------- diff --git a/include/configs/ERIC.h b/include/configs/ERIC.h index 9f6baf7fffc..539716f2c57 100644 --- a/include/configs/ERIC.h +++ b/include/configs/ERIC.h @@ -156,7 +156,7 @@ #define CONFIG_PCI /* include pci support */ #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ #undef CONFIG_PCI_PNP /* no pci plug-and-play */ - /* resource configuration */ + /* resource configuration */ #define CFG_PCI_SUBSYS_VENDORID 0x1743 /* PCI Vendor ID: Peppercon AG */ #define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: 405GP */ diff --git a/include/configs/ESTEEM192E.h b/include/configs/ESTEEM192E.h index 7a8fba62fb7..b176c6f37e9 100644 --- a/include/configs/ESTEEM192E.h +++ b/include/configs/ESTEEM192E.h @@ -113,7 +113,6 @@ #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) @@ -301,7 +300,6 @@ #define CFG_MAMR_9COL 0x18803112 /* same as 8 column because its just easier to port with*/ - /* * Internal Definitions * diff --git a/include/configs/ETX094.h b/include/configs/ETX094.h index b6e19419dfd..137b1a71b30 100644 --- a/include/configs/ETX094.h +++ b/include/configs/ETX094.h @@ -282,7 +282,7 @@ /* FLASH timing: ACS = 11, TRLX = 1, CSNT = 0, SCY = 2, EHTR = 0 */ #define CFG_OR_TIMING_FLASH (OR_ACS_DIV2 | OR_BI | \ - OR_SCY_2_CLK | OR_TRLX ) + OR_SCY_2_CLK | OR_TRLX ) #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) diff --git a/include/configs/EVB64260.h b/include/configs/EVB64260.h index acd8538c319..af5122f6f00 100644 --- a/include/configs/EVB64260.h +++ b/include/configs/EVB64260.h @@ -198,11 +198,11 @@ #define CFG_DEV2_PAR 0xc0059bd4 #define CFG_8BIT_BOOT_PAR 0xc00b5e7c #define CFG_32BIT_BOOT_PAR 0xc4a8241c - /* c 4 a 8 2 4 1 c */ - /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ - /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ - /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */ - /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */ + /* c 4 a 8 2 4 1 c */ + /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ + /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ + /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */ + /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */ #if 0 /* Wrong?? NTL */ #define CFG_MPP_CONTROL_0 0x53541717 /* InitAct EOT[4] DBurst TCEn[1] */ @@ -229,11 +229,11 @@ /* GPP[27:26] Int[1:0] */ #else # define CFG_MPP_CONTROL_3 0x22090066 /* MREQ MGNT */ - /* GPP[29] (PCI1Int) */ - /* BClkOut0 */ - /* GPP[27] (PCI0Int) */ - /* GPP[26] (RtcInt or PCI1Int) */ - /* CPUInt[25:24] */ + /* GPP[29] (PCI1Int) */ + /* BClkOut0 */ + /* GPP[27] (PCI0Int) */ + /* GPP[26] (RtcInt or PCI1Int) */ + /* CPUInt[25:24] */ #endif # define CFG_SERIAL_PORT_MUX 0x00000102 /* 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */ @@ -242,9 +242,9 @@ # define CFG_GPP_LEVEL_CONTROL 0x000002c6 #else # define CFG_GPP_LEVEL_CONTROL 0x2c600000 /* 0010 1100 0110 0000 */ - /* gpp[29] */ + /* gpp[29] */ /* gpp[27:26] */ - /* gpp[22:21] */ + /* gpp[22:21] */ # define CFG_SDRAM_CONFIG 0xd8e18200 /* 0x448 */ /* idmas use buffer 1,1 @@ -295,7 +295,6 @@ #define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE) - /* PCI I/O MAP section */ #define CFG_PCI0_IO_BASE 0xfa000000 #define CFG_PCI0_IO_SIZE _16M diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h index 47a87862c2a..0702c2cf639 100644 --- a/include/configs/GEN860T.h +++ b/include/configs/GEN860T.h @@ -50,7 +50,7 @@ * generated by the DS1337 - and the DS1337 clock can be turned off. */ #if !defined(CONFIG_SC) -#define CONFIG_8xx_GCLK_FREQ 66600000 +#define CONFIG_8xx_GCLK_FREQ 66600000 #else #define CONFIG_8xx_GCLK_FREQ 48000000 #endif @@ -204,7 +204,7 @@ * length of time, so we use an external RTC on the I2C bus instead. */ #define CONFIG_RTC_DS1337 -#define CFG_I2C_RTC_ADDR 0x68 +#define CFG_I2C_RTC_ADDR 0x68 #else /* @@ -248,7 +248,7 @@ CFG_CMD_POST_DIAG ) #if !defined(CONFIG_SC) -#define CONFIG_COMMANDS ( BASE_CONFIG_COMMANDS | CFG_CMD_DOC ) +#define CONFIG_COMMANDS ( BASE_CONFIG_COMMANDS | CFG_CMD_DOC ) #else #define CONFIG_COMMANDS BASE_CONFIG_COMMANDS #endif diff --git a/include/configs/IP860.h b/include/configs/IP860.h index fddf0ca3d50..649096274f3 100644 --- a/include/configs/IP860.h +++ b/include/configs/IP860.h @@ -227,7 +227,7 @@ SIUMCR_DBGC11 | SIUMCR_MLRC10) /*----------------------------------------------------------------------- - * Clock Setting - get clock frequency from Board Revision Register + * Clock Setting - get clock frequency from Board Revision Register *----------------------------------------------------------------------- */ #ifndef __ASSEMBLY__ diff --git a/include/configs/KUP4K.h b/include/configs/KUP4K.h index b924b9c5e35..962a4686f31 100644 --- a/include/configs/KUP4K.h +++ b/include/configs/KUP4K.h @@ -432,7 +432,6 @@ cp.b 200000 40040000 14000\0" #define BOOTFLAG_WARM 0x02 /* Software reboot */ - #define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ #if 0 #define CONFIG_AUTOBOOT_PROMPT "Boote in %d Sekunden - stop mit \"2\"\n" diff --git a/include/configs/LANTEC.h b/include/configs/LANTEC.h index 56ecf0c8bf4..4c01cda064c 100644 --- a/include/configs/LANTEC.h +++ b/include/configs/LANTEC.h @@ -297,7 +297,7 @@ /* FLASH timing */ #define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | \ - OR_SCY_5_CLK | OR_TRLX) + OR_SCY_5_CLK | OR_TRLX) #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) diff --git a/include/configs/MBX.h b/include/configs/MBX.h index e62d36cc059..d6e3fb8de9b 100644 --- a/include/configs/MBX.h +++ b/include/configs/MBX.h @@ -72,7 +72,7 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_COMMANDS ( CFG_CMD_NET | CONFIG_CMD_DFL | CFG_CMD_SDRAM | \ - CFG_CMD_PCMCIA | CFG_CMD_IDE ) + CFG_CMD_PCMCIA | CFG_CMD_IDE ) #define CONFIG_DOS_PARTITION diff --git a/include/configs/MHPC.h b/include/configs/MHPC.h index 78caafd847d..e36341fd1e1 100644 --- a/include/configs/MHPC.h +++ b/include/configs/MHPC.h @@ -116,12 +116,12 @@ #define CONFIG_BR0_WORKAROUND 1 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DATE | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_REGINFO ) + CFG_CMD_DATE | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_REGINFO ) #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) @@ -225,7 +225,7 @@ SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) #else #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWP) + SYPCR_SWP) #endif /*----------------------------------------------------------------------- @@ -265,7 +265,7 @@ #define MPC8XX_XIN 5000000L /* ref clk */ #define MPC8XX_FACT (MPC8XX_SPEED/MPC8XX_XIN) #define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) /*----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register 15-27 diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index b29eb8bed5f..8d7930765ac 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -44,7 +44,7 @@ * CONFIG_BOOT_PCI is only used for first boot-up and should * NOT be enabled for production bootloader ***********************************************************/ -/*#define CONFIG_BOOT_PCI 1*/ +/*#define CONFIG_BOOT_PCI 1*/ /*********************************************************** * Clock ***********************************************************/ @@ -260,7 +260,6 @@ #define CONFIG_PORT_ADDR PER_PLD_ADDR + 5 - /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in On Chip SRAM) */ diff --git a/include/configs/ML2.h b/include/configs/ML2.h index d66266126c8..5fe5d5444a6 100644 --- a/include/configs/ML2.h +++ b/include/configs/ML2.h @@ -76,7 +76,6 @@ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - #define CONFIG_COMMANDS ( (CONFIG_CMD_DFL & (~CFG_CMD_NET) & \ (~CFG_CMD_RTC) & ~(CFG_CMD_PCI) & ~(CFG_CMD_I2C)) | \ CFG_CMD_IRQ | \ @@ -142,7 +141,6 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) diff --git a/include/configs/MOUSSE.h b/include/configs/MOUSSE.h index 109ed3d811e..6ad2feb28e7 100644 --- a/include/configs/MOUSSE.h +++ b/include/configs/MOUSSE.h @@ -229,7 +229,7 @@ #define CFG_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory - see 8240 book for details*/ + see 8240 book for details*/ #define PCI_MEM_SPACE1_START 0x80000000 #define PCI_MEM_SPACE2_START 0xfd000000 @@ -296,7 +296,6 @@ #define CFG_CACHELINE_SIZE 16 - /* * Internal Definitions * @@ -328,5 +327,3 @@ #define CONFIG_TULIP #endif /* __CONFIG_H */ - - diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h index 9e8d732e2bd..8501b2b4d9b 100644 --- a/include/configs/MPC8266ADS.h +++ b/include/configs/MPC8266ADS.h @@ -38,7 +38,7 @@ !! 0xfff00000 !! !! The CFG_HRCW_MASTER define below must also be changed to match !! !! !! - !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! + !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */ #ifndef __CONFIG_H @@ -398,15 +398,15 @@ /* Use this HRCW for booting from address 0xfff0000 (JP3 in setting 2-3) */ /* #define CFG_HRCW_MASTER 0x0cb23645 */ -/* This value should actually be situated in the first 256 bytes of the FLASH +/* This value should actually be situated in the first 256 bytes of the FLASH which on the standard MPC8266ADS board is at address 0xFF800000 The linker script places it at 0xFFF00000 instead. - It still works, however, as long as the ADS board jumper JP3 is set to - position 2-3 so the board is using the BCSR as Hardware Configuration Word + It still works, however, as long as the ADS board jumper JP3 is set to + position 2-3 so the board is using the BCSR as Hardware Configuration Word - If you want to use the one defined here instead, ust copy the first 256 bytes from - 0xfff00000 to 0xff800000 (for 8MB flash) + If you want to use the one defined here instead, ust copy the first 256 bytes from + 0xfff00000 to 0xff800000 (for 8MB flash) - Rune @@ -514,12 +514,12 @@ #define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */ #define CFG_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ #define CFG_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \ - PICMR_PREFETCH_EN) + PICMR_PREFETCH_EN) -/* +/* * These are the windows that allow the CPU to access PCI address space. - * All three PCI master windows, which allow the CPU to access PCI - * prefetch, non prefetch, and IO space (see below), must all fit within + * All three PCI master windows, which allow the CPU to access PCI + * prefetch, non prefetch, and IO space (see below), must all fit within * these windows. */ @@ -530,7 +530,7 @@ #define CFG_PCI_MSTR1_LOCAL 0xF4000000 /* Local base */ #define CFG_PCIMSK1_MASK PCIMSK_64MB /* Size of window */ -/* +/* * Master window that allows the CPU to access PCI Memory (prefetch). * This window will be setup with the first set of Outbound ATU registers * in the bridge. @@ -542,7 +542,7 @@ #define CFG_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */ #define CFG_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN) -/* +/* * Master window that allows the CPU to access PCI Memory (non-prefetch). * This window will be setup with the second set of Outbound ATU registers * in the bridge. @@ -554,7 +554,7 @@ #define CFG_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */ #define CFG_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) -/* +/* * Master window that allows the CPU to access PCI IO space. * This window will be setup with the third set of Outbound ATU registers * in the bridge. diff --git a/include/configs/MUSENKI.h b/include/configs/MUSENKI.h index 03765a3dc12..da52e0ec0b8 100644 --- a/include/configs/MUSENKI.h +++ b/include/configs/MUSENKI.h @@ -292,6 +292,4 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ - - #endif /* __CONFIG_H */ diff --git a/include/configs/MVS1.h b/include/configs/MVS1.h index d10fa8ff252..49bdc45a4a2 100644 --- a/include/configs/MVS1.h +++ b/include/configs/MVS1.h @@ -184,7 +184,7 @@ */ #if defined(CONFIG_WATCHDOG) #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) #else #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) #endif diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h index 0ac456ab576..fb3b64218df 100644 --- a/include/configs/OCRTC.h +++ b/include/configs/OCRTC.h @@ -95,8 +95,8 @@ /* The following table includes the supported baudrates */ #define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } #define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ @@ -116,7 +116,7 @@ #define CONFIG_PCI /* include pci support */ #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ + /* resource configuration */ #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ @@ -188,7 +188,7 @@ #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ #define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ #define CFG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */ - /* total size of a CAT24WC08 is 1024 bytes */ + /* total size of a CAT24WC08 is 1024 bytes */ #endif /*----------------------------------------------------------------------- @@ -240,32 +240,32 @@ /* Memory Bank 2 (PLD - FPGA-boot) initialization */ #define CFG_EBC_PB2AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/ + /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/ #define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ /* Memory Bank 3 (PLD - OSL) initialization */ #define CFG_EBC_PB3AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/ + /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/ #define CFG_EBC_PB3CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ /* Memory Bank 4 (Spartan2 1) initialization */ #define CFG_EBC_PB4AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ + /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ #define CFG_EBC_PB4CR 0xF209C000 /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/ /* Memory Bank 5 (Spartan2 2) initialization */ #define CFG_EBC_PB5AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ + /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ #define CFG_EBC_PB5CR 0xF309C000 /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/ /* Memory Bank 6 (Virtex 1) initialization */ #define CFG_EBC_PB6AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ + /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ #define CFG_EBC_PB6CR 0xF409A000 /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/ /* Memory Bank 7 (Virtex 2) initialization */ #define CFG_EBC_PB7AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ + /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ #define CFG_EBC_PB7CR 0xF509A000 /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/ diff --git a/include/configs/ORSG.h b/include/configs/ORSG.h index 7c161c68d4a..5da3fc52918 100644 --- a/include/configs/ORSG.h +++ b/include/configs/ORSG.h @@ -95,8 +95,8 @@ /* The following table includes the supported baudrates */ #define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } #define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ @@ -116,7 +116,7 @@ #define CONFIG_PCI /* include pci support */ #define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci adapter */ #undef CONFIG_PCI_PNP /* no pci plug-and-play */ - /* resource configuration */ + /* resource configuration */ #undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ @@ -186,7 +186,7 @@ #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ #define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ #define CFG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */ - /* total size of a CAT24WC08 is 1024 bytes */ + /* total size of a CAT24WC08 is 1024 bytes */ #endif /*----------------------------------------------------------------------- @@ -238,32 +238,32 @@ /* Memory Bank 2 (PLD - FPGA-boot) initialization */ #define CFG_EBC_PB2AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/ + /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/ #define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ /* Memory Bank 3 (PLD - OSL) initialization */ #define CFG_EBC_PB3AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/ + /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/ #define CFG_EBC_PB3CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ /* Memory Bank 4 (Spartan2 1) initialization */ #define CFG_EBC_PB4AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ + /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ #define CFG_EBC_PB4CR 0xF209C000 /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/ /* Memory Bank 5 (Spartan2 2) initialization */ #define CFG_EBC_PB5AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ + /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ #define CFG_EBC_PB5CR 0xF309C000 /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/ /* Memory Bank 6 (Virtex 1) initialization */ #define CFG_EBC_PB6AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ + /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ #define CFG_EBC_PB6CR 0xF409A000 /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/ /* Memory Bank 7 (Virtex 2) initialization */ #define CFG_EBC_PB7AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ - /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ + /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ #define CFG_EBC_PB7CR 0xF509A000 /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/ diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h index b1ed0cb8080..8ab253a35e6 100644 --- a/include/configs/PCI405.h +++ b/include/configs/PCI405.h @@ -47,10 +47,10 @@ #if 0 #define CONFIG_PREBOOT \ - "crc32 f0207004 ffc 0;" \ - "if cmp 0 f0207000 1;" \ - "then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;" \ - "else;echo Old CRC is bad;fi" + "crc32 f0207004 ffc 0;" \ + "if cmp 0 f0207000 1;" \ + "then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;" \ + "else;echo Old CRC is bad;fi" #endif #undef CONFIG_BOOTARGS @@ -60,8 +60,8 @@ #else #define CONFIG_BOOTCOMMAND \ "mw.l 0 ffffffff; mw.l 4 ffffffff;" \ - "while cmp 0 4 1; do echo Waiting for Host...;done;" \ - "bootm 400000" + "while cmp 0 4 1; do echo Waiting for Host...;done;" \ + "bootm 400000" #endif #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ @@ -123,8 +123,8 @@ /* The following table includes the supported baudrates */ #define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } #define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ @@ -144,7 +144,7 @@ #define CONFIG_PCI /* include pci support */ #define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci host function */ #undef CONFIG_PCI_PNP /* no pci plug-and-play */ - /* resource configuration */ + /* resource configuration */ #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ @@ -218,7 +218,7 @@ #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ #define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ #define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars*/ - /* total size of a CAT24WC08 is 1024 bytes */ + /* total size of a CAT24WC08 is 1024 bytes */ #endif #define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ diff --git a/include/configs/PCIPPC2.h b/include/configs/PCIPPC2.h index 3eb6ac3c1f2..645cdc59d27 100644 --- a/include/configs/PCIPPC2.h +++ b/include/configs/PCIPPC2.h @@ -56,7 +56,7 @@ #define CONFIG_BOOTDELAY 5 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE) + CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -231,7 +231,7 @@ */ #undef CFG_L2 #define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) + L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) #define L2_ENABLE (L2_INIT | L2CR_L2E) /* diff --git a/include/configs/PCIPPC6.h b/include/configs/PCIPPC6.h index f4dfbfefd04..4953458d40d 100644 --- a/include/configs/PCIPPC6.h +++ b/include/configs/PCIPPC6.h @@ -278,6 +278,4 @@ #define CONFIG_MAC_PARTITION #define CONFIG_ISO_PARTITION - - #endif /* __CONFIG_H */ diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index 8fbbe30bd22..60e5a9ac735 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -239,7 +239,6 @@ #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000 - /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in On Chip SRAM) */ diff --git a/include/configs/PM826.h b/include/configs/PM826.h index 6ba14aff149..666857831f9 100644 --- a/include/configs/PM826.h +++ b/include/configs/PM826.h @@ -347,7 +347,7 @@ * HID1 has only read-only information - nothing to set. */ #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) + HID0_IFEM|HID0_ABE) #define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) #define CFG_HID2 0 @@ -385,10 +385,10 @@ */ #if defined(CONFIG_WATCHDOG) #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) + SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) #else #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) + SYPCR_SWRI|SYPCR_SWP) #endif /* CONFIG_WATCHDOG */ /*----------------------------------------------------------------------- @@ -482,16 +482,16 @@ * Bank 0 - Flash (64 bit wide) */ #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_GPCM_P |\ - BRx_V) + BRx_PS_64 |\ + BRx_MS_GPCM_P |\ + BRx_V) #define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxG_EHTR |\ - ORxG_TRLX) + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_3_CLK |\ + ORxG_EHTR |\ + ORxG_TRLX) /* * Bank 1 - Disk-On-Chip @@ -515,43 +515,43 @@ #define CFG_PSRT 0x0F #ifndef CFG_RAMBOOT #define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) /* SDRAM initialization values for 8-column chips */ #define CFG_OR2_8COL (CFG_MIN_AM_MASK |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A9 |\ - ORxS_NUMR_12) + ORxS_BPD_4 |\ + ORxS_ROWST_PBI0_A9 |\ + ORxS_NUMR_12) #define CFG_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\ - PSDMR_BSMA_A14_A16 |\ - PSDMR_SDA10_PBI0_A10 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_1W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) + PSDMR_BSMA_A14_A16 |\ + PSDMR_SDA10_PBI0_A10 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_1W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_1C |\ + PSDMR_CL_2) /* SDRAM initialization values for 9-column chips */ #define CFG_OR2_9COL (CFG_MIN_AM_MASK |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A7 |\ - ORxS_NUMR_13) + ORxS_BPD_4 |\ + ORxS_ROWST_PBI0_A7 |\ + ORxS_NUMR_13) #define CFG_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_1W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) + PSDMR_BSMA_A13_A15 |\ + PSDMR_SDA10_PBI0_A9 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_1W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_1C |\ + PSDMR_CL_2) #define CFG_OR2_PRELIM CFG_OR2_9COL #define CFG_PSDMR CFG_PSDMR_9COL diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h index e3d37856c3a..54b53bc71f1 100644 --- a/include/configs/PMC405.h +++ b/include/configs/PMC405.h @@ -119,8 +119,8 @@ /* The following table includes the supported baudrates */ #define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + 57600, 115200, 230400, 460800, 921600 } #define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ @@ -144,7 +144,7 @@ #define CONFIG_PCI /* include pci support */ #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ + /* resource configuration */ #undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ @@ -197,7 +197,7 @@ #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ #define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ #define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ + /* total size of a CAT24WC16 is 2048 bytes */ #define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ #define CFG_NVRAM_SIZE 242 /* NVRAM size */ @@ -223,7 +223,7 @@ * Cache Configuration */ #define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ + /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ diff --git a/include/configs/RPXClassic.h b/include/configs/RPXClassic.h index f20b8f99ac1..959ee1a4910 100644 --- a/include/configs/RPXClassic.h +++ b/include/configs/RPXClassic.h @@ -182,7 +182,7 @@ #define CFG_SDRAM_BASE 0x00000000 #define CFG_FLASH_BASE 0xFF000000 -#if defined(DEBUG) || defined (CONFIG_VIDEO_SED13806) || (CONFIG_COMMANDS & CFG_CMD_IDE) +#if defined(DEBUG) || defined (CONFIG_VIDEO_SED13806) || (CONFIG_COMMANDS & CFG_CMD_IDE) #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #else #define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ @@ -370,8 +370,8 @@ /* ECCX CS settings */ #define SED13806_OR 0xFFC00108 /* - 4 Mo - - Burst inhibit - - external TA */ + - Burst inhibit + - external TA */ #define SED13806_REG_ADDR 0xa0000000 #define SED13806_ACCES 0x801 /* 16 bit access */ @@ -391,8 +391,8 @@ /* Definitions for CSR8 */ #define ECCX_ENEPSON 0x80 /* Bit 0: - 0= disable and reset SED1386 - 1= enable SED1386 */ + 0= disable and reset SED1386 + 1= enable SED1386 */ /* Bit 1: 0= SED1386 in Big Endian mode */ /* 1= SED1386 in little endian mode */ #define ECCX_LE 0x40 diff --git a/include/configs/RPXsuper.h b/include/configs/RPXsuper.h index c36467263ae..0abff11e3b7 100644 --- a/include/configs/RPXsuper.h +++ b/include/configs/RPXsuper.h @@ -226,18 +226,18 @@ /* get the HRCW ISB field from CFG_IMMR */ #define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) |\ - ((CFG_IMMR & 0x01000000) >> 7) |\ - ((CFG_IMMR & 0x00100000) >> 4) ) + ((CFG_IMMR & 0x01000000) >> 7) |\ + ((CFG_IMMR & 0x00100000) >> 4) ) #define CFG_HRCW_MASTER (HRCW_BPS11 |\ - HRCW_DPPC11 |\ - CFG_SBC_HRCW_IMMR |\ - HRCW_MMR00 |\ - HRCW_LBPC11 |\ - HRCW_APPC10 |\ - HRCW_CS10PC00 |\ - (CFG_SBC_MODCK_H & HRCW_MODCK_H1111) |\ - CFG_SBC_HRCW_BOOT_FLAGS) + HRCW_DPPC11 |\ + CFG_SBC_HRCW_IMMR |\ + HRCW_MMR00 |\ + HRCW_LBPC11 |\ + HRCW_APPC10 |\ + HRCW_CS10PC00 |\ + (CFG_SBC_MODCK_H & HRCW_MODCK_H1111) |\ + CFG_SBC_HRCW_BOOT_FLAGS) /* no slaves */ #define CFG_HRCW_SLAVE1 0 @@ -358,8 +358,8 @@ */ #define CFG_SIUMCR (SIUMCR_L2CPC01 |\ - SIUMCR_APPC10 |\ - SIUMCR_CS10PC01) + SIUMCR_APPC10 |\ + SIUMCR_CS10PC01) /*----------------------------------------------------------------------- @@ -369,11 +369,11 @@ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable */ #define CFG_SYPCR (SYPCR_SWTC |\ - SYPCR_BMT |\ - SYPCR_PBME |\ - SYPCR_LBME |\ - SYPCR_SWRI |\ - SYPCR_SWP) + SYPCR_BMT |\ + SYPCR_PBME |\ + SYPCR_LBME |\ + SYPCR_SWRI |\ + SYPCR_SWP) /*----------------------------------------------------------------------- * TMCNTSC - Time Counter Status and Control 4-40 @@ -382,9 +382,9 @@ * and enable Time Counter */ #define CFG_TMCNTSC (TMCNTSC_SEC |\ - TMCNTSC_ALR |\ - TMCNTSC_TCF |\ - TMCNTSC_TCE) + TMCNTSC_ALR |\ + TMCNTSC_TCF |\ + TMCNTSC_TCE) /*----------------------------------------------------------------------- * PISCR - Periodic Interrupt Status and Control 4-42 @@ -393,8 +393,8 @@ * Periodic timer */ #define CFG_PISCR (PISCR_PS |\ - PISCR_PTF |\ - PISCR_PTE) + PISCR_PTF |\ + PISCR_PTE) /*----------------------------------------------------------------------- * SCCR - System Clock Control 9-8 @@ -431,29 +431,29 @@ * */ #define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ + BRx_PS_64 |\ BRx_DECC_NONE |\ - BRx_MS_GPCM_P |\ - BRx_V) + BRx_MS_GPCM_P |\ + BRx_V) #define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_6_CLK |\ - ORxG_EHTR) + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_6_CLK |\ + ORxG_EHTR) /* Bank 1 - SDRAM * */ #define CFG_BR1_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) #define CFG_OR1_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A8 |\ - ORxS_NUMR_12 |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI0_A8 |\ + ORxS_NUMR_12 |\ ORxS_IBID) #define CFG_PSDMR 0x014DA412 @@ -464,14 +464,14 @@ * */ #define CFG_BR2_PRELIM ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_SDRAM_L |\ - BRx_V) + BRx_PS_32 |\ + BRx_MS_SDRAM_L |\ + BRx_V) #define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM1_SIZE) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A9 |\ - ORxS_NUMR_12) + ORxS_BPD_4 |\ + ORxS_ROWST_PBI0_A9 |\ + ORxS_NUMR_12) #define CFG_LSDMR 0x0169A512 #define CFG_LSRT 0x79 @@ -482,15 +482,15 @@ * */ #define CFG_BR4_PRELIM ((CFG_REGS_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) #define CFG_OR4_PRELIM (ORxG_AM_MSK |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX) + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_5_CLK |\ + ORxG_TRLX) /* * Internal Definitions @@ -501,5 +501,3 @@ #define BOOTFLAG_WARM 0x02 /* Software reboot */ #endif /* __CONFIG_H */ - - diff --git a/include/configs/RRvision.h b/include/configs/RRvision.h index a1327e75aac..926d63a6686 100644 --- a/include/configs/RRvision.h +++ b/include/configs/RRvision.h @@ -135,7 +135,6 @@ #endif /* CONFIG_SOFT_I2C */ - #define CONFIG_COMMANDS ( ( CONFIG_CMD_DFL | \ CFG_CMD_DHCP | \ CFG_CMD_I2C | \ diff --git a/include/configs/SCM.h b/include/configs/SCM.h index 0dd46a0f83d..e4533b465b1 100644 --- a/include/configs/SCM.h +++ b/include/configs/SCM.h @@ -287,10 +287,10 @@ */ #if defined(CONFIG_266MHz) #define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \ - HRCW_MODCK_H0111) + HRCW_MODCK_H0111) #elif defined(CONFIG_300MHz) #define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \ - HRCW_MODCK_H0110) + HRCW_MODCK_H0110) #else #define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS) #endif @@ -367,7 +367,7 @@ * HID1 has only read-only information - nothing to set. */ #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) + HID0_IFEM|HID0_ABE) #define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) #define CFG_HID2 0 @@ -409,10 +409,10 @@ */ #if defined(CONFIG_WATCHDOG) #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) + SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) #else #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) + SYPCR_SWRI|SYPCR_SWP) #endif /* CONFIG_WATCHDOG */ /*----------------------------------------------------------------------- @@ -490,16 +490,16 @@ /* Bank 0 - FLASH */ #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_GPCM_P |\ - BRx_V) + BRx_PS_64 |\ + BRx_MS_GPCM_P |\ + BRx_V) #define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxG_EHTR |\ - ORxG_TRLX) + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_3_CLK |\ + ORxG_EHTR |\ + ORxG_TRLX) /* SDRAM on TQM8260 can have either 8 or 9 columns. * The number affects configuration values. @@ -511,9 +511,9 @@ #define CFG_LSRT 0x20 #ifndef CFG_RAMBOOT #define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) #define CFG_OR1_PRELIM CFG_OR1_8COL @@ -521,48 +521,48 @@ /* SDRAM initialization values for 8-column chips */ #define CFG_OR1_8COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A7 |\ - ORxS_NUMR_12) + ORxS_BPD_4 |\ + ORxS_ROWST_PBI1_A7 |\ + ORxS_NUMR_12) #define CFG_PSDMR_8COL (PSDMR_PBI |\ - PSDMR_SDAM_A15_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A8 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_CL_2) + PSDMR_SDAM_A15_IS_A5 |\ + PSDMR_BSMA_A12_A14 |\ + PSDMR_SDA10_PBI1_A8 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_2C |\ + PSDMR_EAMUX |\ + PSDMR_CL_2) /* SDRAM initialization values for 9-column chips */ #define CFG_OR1_9COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A5 |\ - ORxS_NUMR_13) + ORxS_BPD_4 |\ + ORxS_ROWST_PBI1_A5 |\ + ORxS_NUMR_13) #define CFG_PSDMR_9COL (PSDMR_PBI |\ - PSDMR_SDAM_A16_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A7 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_CL_2) + PSDMR_SDAM_A16_IS_A5 |\ + PSDMR_BSMA_A12_A14 |\ + PSDMR_SDA10_PBI1_A7 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_2C |\ + PSDMR_EAMUX |\ + PSDMR_CL_2) /* Bank 2 - Local bus SDRAM */ #ifdef CFG_INIT_LOCAL_SDRAM #define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_SDRAM_L |\ - BRx_V) + BRx_PS_32 |\ + BRx_MS_SDRAM_L |\ + BRx_V) #define CFG_OR2_PRELIM CFG_OR2_8COL @@ -571,40 +571,40 @@ /* SDRAM initialization values for 8-column chips */ #define CFG_OR2_8COL ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A8 |\ - ORxS_NUMR_12) + ORxS_BPD_4 |\ + ORxS_ROWST_PBI1_A8 |\ + ORxS_NUMR_12) #define CFG_LSDMR_8COL (PSDMR_PBI |\ - PSDMR_SDAM_A15_IS_A5 |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_SDA10_PBI1_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_BL |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_CL_2) + PSDMR_SDAM_A15_IS_A5 |\ + PSDMR_BSMA_A13_A15 |\ + PSDMR_SDA10_PBI1_A9 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_BL |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_2C |\ + PSDMR_CL_2) /* SDRAM initialization values for 9-column chips */ #define CFG_OR2_9COL ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A6 |\ - ORxS_NUMR_13) + ORxS_BPD_4 |\ + ORxS_ROWST_PBI1_A6 |\ + ORxS_NUMR_13) #define CFG_LSDMR_9COL (PSDMR_PBI |\ - PSDMR_SDAM_A16_IS_A5 |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_SDA10_PBI1_A8 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_BL |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_CL_2) + PSDMR_SDAM_A16_IS_A5 |\ + PSDMR_BSMA_A13_A15 |\ + PSDMR_SDA10_PBI1_A8 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_BL |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_2C |\ + PSDMR_CL_2) #endif /* CFG_INIT_LOCAL_SDRAM */ @@ -708,4 +708,3 @@ #endif /* __CONFIG_H */ - diff --git a/include/configs/TQM8260.h b/include/configs/TQM8260.h index 1ea9a5e162e..2961a6a76b3 100644 --- a/include/configs/TQM8260.h +++ b/include/configs/TQM8260.h @@ -394,7 +394,7 @@ * HID1 has only read-only information - nothing to set. */ #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) + HID0_IFEM|HID0_ABE) #define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) #define CFG_HID2 0 @@ -436,10 +436,10 @@ */ #if defined(CONFIG_WATCHDOG) #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) + SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) #else #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) + SYPCR_SWRI|SYPCR_SWP) #endif /* CONFIG_WATCHDOG */ /*----------------------------------------------------------------------- @@ -517,16 +517,16 @@ /* Bank 0 - FLASH */ #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_GPCM_P |\ - BRx_V) + BRx_PS_64 |\ + BRx_MS_GPCM_P |\ + BRx_V) #define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxG_EHTR |\ - ORxG_TRLX) + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_3_CLK |\ + ORxG_EHTR |\ + ORxG_TRLX) /* SDRAM on TQM8260 can have either 8 or 9 columns. * The number affects configuration values. @@ -538,9 +538,9 @@ #define CFG_LSRT 0x20 #ifndef CFG_RAMBOOT #define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) #define CFG_OR1_PRELIM CFG_OR1_8COL @@ -548,48 +548,48 @@ /* SDRAM initialization values for 8-column chips */ #define CFG_OR1_8COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A7 |\ - ORxS_NUMR_12) + ORxS_BPD_4 |\ + ORxS_ROWST_PBI1_A7 |\ + ORxS_NUMR_12) #define CFG_PSDMR_8COL (PSDMR_PBI |\ - PSDMR_SDAM_A15_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A8 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_CL_2) + PSDMR_SDAM_A15_IS_A5 |\ + PSDMR_BSMA_A12_A14 |\ + PSDMR_SDA10_PBI1_A8 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_2C |\ + PSDMR_EAMUX |\ + PSDMR_CL_2) /* SDRAM initialization values for 9-column chips */ #define CFG_OR1_9COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A5 |\ - ORxS_NUMR_13) + ORxS_BPD_4 |\ + ORxS_ROWST_PBI1_A5 |\ + ORxS_NUMR_13) #define CFG_PSDMR_9COL (PSDMR_PBI |\ - PSDMR_SDAM_A16_IS_A5 |\ - PSDMR_BSMA_A12_A14 |\ - PSDMR_SDA10_PBI1_A7 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_EAMUX |\ - PSDMR_CL_2) + PSDMR_SDAM_A16_IS_A5 |\ + PSDMR_BSMA_A12_A14 |\ + PSDMR_SDA10_PBI1_A7 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_2C |\ + PSDMR_EAMUX |\ + PSDMR_CL_2) /* Bank 2 - Local bus SDRAM */ #ifdef CFG_INIT_LOCAL_SDRAM #define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_SDRAM_L |\ - BRx_V) + BRx_PS_32 |\ + BRx_MS_SDRAM_L |\ + BRx_V) #define CFG_OR2_PRELIM CFG_OR2_8COL @@ -598,40 +598,40 @@ /* SDRAM initialization values for 8-column chips */ #define CFG_OR2_8COL ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A8 |\ - ORxS_NUMR_12) + ORxS_BPD_4 |\ + ORxS_ROWST_PBI1_A8 |\ + ORxS_NUMR_12) #define CFG_LSDMR_8COL (PSDMR_PBI |\ - PSDMR_SDAM_A15_IS_A5 |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_SDA10_PBI1_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_BL |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_CL_2) + PSDMR_SDAM_A15_IS_A5 |\ + PSDMR_BSMA_A13_A15 |\ + PSDMR_SDA10_PBI1_A9 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_BL |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_2C |\ + PSDMR_CL_2) /* SDRAM initialization values for 9-column chips */ #define CFG_OR2_9COL ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A6 |\ - ORxS_NUMR_13) + ORxS_BPD_4 |\ + ORxS_ROWST_PBI1_A6 |\ + ORxS_NUMR_13) #define CFG_LSDMR_9COL (PSDMR_PBI |\ - PSDMR_SDAM_A16_IS_A5 |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_SDA10_PBI1_A8 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_BL |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_2C |\ - PSDMR_CL_2) + PSDMR_SDAM_A16_IS_A5 |\ + PSDMR_BSMA_A13_A15 |\ + PSDMR_SDA10_PBI1_A8 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_BL |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_2C |\ + PSDMR_CL_2) #endif /* CFG_INIT_LOCAL_SDRAM */ diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h index b5610c9506f..7ae1c7059c9 100644 --- a/include/configs/W7OLMC.h +++ b/include/configs/W7OLMC.h @@ -323,4 +323,3 @@ #define CONFIG_FPGAS_BANK_SIZE 0x00100000L /* FPGAs' mmap bank size */ #endif /* __CONFIG_H */ - diff --git a/include/configs/WALNUT405.h b/include/configs/WALNUT405.h index 36674dbfbce..cdc9a3cc21a 100644 --- a/include/configs/WALNUT405.h +++ b/include/configs/WALNUT405.h @@ -161,7 +161,7 @@ #define CONFIG_PCI /* include pci support */ #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ + /* resource configuration */ #define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ #define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ diff --git a/include/configs/ZUMA.h b/include/configs/ZUMA.h index 541cf9225db..3fde23838f1 100644 --- a/include/configs/ZUMA.h +++ b/include/configs/ZUMA.h @@ -207,7 +207,6 @@ /* 3| 0|.... ..| 1| 5 | 5 | 5 | 5 | 8 | 5 */ - #define CFG_8BIT_BOOT_PAR 0xc00b5e7c #define CFG_MPP_CONTROL_0 0x00007777 /* GPP[7:4] : REQ0[1:0] GNT0[1:0] */ diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h index e3829770544..415b7fb6ea6 100644 --- a/include/configs/at91rm9200dk.h +++ b/include/configs/at91rm9200dk.h @@ -49,19 +49,19 @@ #undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ -#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTDELAY 3 /* #define CONFIG_ENV_OVERWRITE 1 */ #define CONFIG_COMMANDS \ ((CONFIG_CMD_DFL | \ CFG_CMD_DHCP ) & \ - ~(CFG_CMD_BDI | \ - CFG_CMD_IMI | \ - CFG_CMD_AUTOSCRIPT | \ - CFG_CMD_FPGA | \ - CFG_CMD_MISC | \ - CFG_CMD_LOADS )) - + ~(CFG_CMD_BDI | \ + CFG_CMD_IMI | \ + CFG_CMD_AUTOSCRIPT | \ + CFG_CMD_FPGA | \ + CFG_CMD_MISC | \ + CFG_CMD_LOADS )) + /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> @@ -155,7 +155,7 @@ struct bd_info_ext #endif #define CFG_HZ AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to - AT91C_TC_TIMER_DIV1_CLOCK */ + AT91C_TC_TIMER_DIV1_CLOCK */ #define CONFIG_STACKSIZE (32*1024) /* regular stack */ diff --git a/include/configs/atc.h b/include/configs/atc.h index 1fb6ed8f12c..275124830f5 100644 --- a/include/configs/atc.h +++ b/include/configs/atc.h @@ -299,7 +299,7 @@ * HID1 has only read-only information - nothing to set. */ #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\ - HID0_DCI|HID0_IFEM|HID0_ABE) + HID0_DCI|HID0_IFEM|HID0_ABE) #define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) #define CFG_HID2 0 @@ -332,10 +332,10 @@ */ #if defined(CONFIG_WATCHDOG) #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) + SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) #else #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) + SYPCR_SWRI|SYPCR_SWP) #endif /* CONFIG_WATCHDOG */ /*----------------------------------------------------------------------- @@ -437,24 +437,24 @@ /* Bank 0 - FLASH */ #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_16 |\ - BRx_MS_GPCM_P |\ - BRx_V) + BRx_PS_16 |\ + BRx_MS_GPCM_P |\ + BRx_V) #define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxU_EHTR_8IDLE) + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_3_CLK |\ + ORxU_EHTR_8IDLE) /* Bank 2 - 60x bus SDRAM */ #ifndef CFG_RAMBOOT #define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) #define CFG_OR2_PRELIM CFG_OR2_8COL @@ -462,12 +462,12 @@ #endif /* CFG_RAMBOOT */ #define CFG_BR4_PRELIM ((RTC_BASE_ADDR & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_UPMA |\ - BRx_V) + BRx_PS_8 |\ + BRx_MS_UPMA |\ + BRx_V) #define CFG_OR4_PRELIM (ORxU_AM_MSK | ORxU_BI) - + /*----------------------------------------------------------------------- * PCMCIA stuff *----------------------------------------------------------------------- diff --git a/include/configs/cmi_mpc5xx.h b/include/configs/cmi_mpc5xx.h index e8b3eb5d82c..e4599192941 100644 --- a/include/configs/cmi_mpc5xx.h +++ b/include/configs/cmi_mpc5xx.h @@ -17,13 +17,13 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, + * Foundation, */ /* * File: cmi_mpc5xx.h - * - * Discription: Config header file for cmi + * + * Discription: Config header file for cmi * board using an MPC5xx CPU * */ @@ -63,12 +63,12 @@ #define CONFIG_WATCHDOG /* turn on platform specific watchdog */ -#define CONFIG_STATUS_LED 1 /* Enable status led */ +#define CONFIG_STATUS_LED 1 /* Enable status led */ #define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */ /* - * Miscellaneous configurable options + * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ @@ -104,7 +104,7 @@ /* * Definitions for initial stack pointer and data area */ -#define CFG_INIT_RAM_ADDR (CFG_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */ +#define CFG_INIT_RAM_ADDR (CFG_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */ #define CFG_INIT_RAM_END (CFG_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */ #define CFG_GBL_DATA_SIZE 64 /* Size in bytes reserved for initial global data */ #define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_INIT_RAM_ADDR) - CFG_GBL_DATA_SIZE) /* Offset from the beginning of ram */ @@ -135,9 +135,9 @@ /*----------------------------------------------------------------------- - * FLASH organization + * FLASH organization *----------------------------------------------------------------------- - * + * */ #define CFG_MAX_FLASH_BANKS 1 /* Max number of memory banks */ @@ -154,7 +154,7 @@ #endif /*----------------------------------------------------------------------- - * SYPCR - System Protection Control + * SYPCR - System Protection Control * SYPCR can only be written once after reset! *----------------------------------------------------------------------- * SW Watchdog freeze @@ -164,7 +164,7 @@ SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) #else #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWP) + SYPCR_SWP) #endif /* CONFIG_WATCHDOG */ /*----------------------------------------------------------------------- @@ -202,30 +202,30 @@ * PLPRCR - PLL, Low-Power, and Reset Control Register *----------------------------------------------------------------------- * Set all bits to 40 Mhz - * + * */ #define CFG_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */ #define CFG_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0) - + /*----------------------------------------------------------------------- * UMCR - UIMB Module Configuration Register *----------------------------------------------------------------------- - * + * */ #define CFG_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */ /*----------------------------------------------------------------------- * ICTRL - I-Bus Support Control Register */ -#define CFG_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */ +#define CFG_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */ /*----------------------------------------------------------------------- * USIU - Memory Controller Register - *----------------------------------------------------------------------- + *----------------------------------------------------------------------- */ -#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_V | BR_BI | BR_PS_16) +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_V | BR_BI | BR_PS_16) #define CFG_OR0_PRELIM (OR_ADDR_MK_FF | OR_SCY_3) #define CFG_BR1_PRELIM (ANYBUS_BASE) #define CFG_OR1_PRELIM (OR_ADDR_MK_FFFF | OR_SCY_1 | OR_ETHR) @@ -238,7 +238,7 @@ #define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* We don't realign the flash */ /*----------------------------------------------------------------------- - * DER - Timer Decrementer + * DER - Timer Decrementer *----------------------------------------------------------------------- * Initialise to zero */ diff --git a/include/configs/cradle.h b/include/configs/cradle.h index 5a215e495f0..13996d4ab64 100644 --- a/include/configs/cradle.h +++ b/include/configs/cradle.h @@ -100,7 +100,7 @@ #define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ #define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ - /* valid baudrates */ + /* valid baudrates */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* diff --git a/include/configs/csb226.h b/include/configs/csb226.h index a257b82eb3b..879607cb56d 100644 --- a/include/configs/csb226.h +++ b/include/configs/csb226.h @@ -122,7 +122,7 @@ #define CFG_MONITOR_LEN 0x20000 /* 128 KiB */ - /* valid baudrates */ + /* valid baudrates */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* diff --git a/include/configs/ep8260.h b/include/configs/ep8260.h index b933be9d3da..f1b2cc14f91 100644 --- a/include/configs/ep8260.h +++ b/include/configs/ep8260.h @@ -370,11 +370,11 @@ /* get the HRCW ISB field from CFG_IMMR */ /* #define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) |\ - ((CFG_IMMR & 0x01000000) >> 7) |\ - ((CFG_IMMR & 0x00100000) >> 4) ) + ((CFG_IMMR & 0x01000000) >> 7) |\ + ((CFG_IMMR & 0x00100000) >> 4) ) #define CFG_HRCW_MASTER (HRCW_EBM |\ - HRCW_L2CPC01 |\ + HRCW_L2CPC01 |\ CFG_SBC_HRCW_IMMR |\ HRCW_APPC10 |\ HRCW_CS10PC01 |\ @@ -512,8 +512,8 @@ */ #define CFG_SIUMCR (SIUMCR_L2CPC01 |\ - SIUMCR_APPC10 |\ - SIUMCR_CS10PC01) + SIUMCR_APPC10 |\ + SIUMCR_CS10PC01) /*----------------------------------------------------------------------- @@ -524,15 +524,15 @@ */ #ifdef CFG_LSDRAM #define CFG_SYPCR (SYPCR_SWTC |\ - SYPCR_BMT |\ - SYPCR_PBME |\ - SYPCR_LBME |\ - SYPCR_SWP) + SYPCR_BMT |\ + SYPCR_PBME |\ + SYPCR_LBME |\ + SYPCR_SWP) #else #define CFG_SYPCR (SYPCR_SWTC |\ - SYPCR_BMT |\ - SYPCR_PBME |\ - SYPCR_SWP) + SYPCR_BMT |\ + SYPCR_PBME |\ + SYPCR_SWP) #endif /*----------------------------------------------------------------------- * TMCNTSC - Time Counter Status and Control 4-40 @@ -541,9 +541,9 @@ * and enable Time Counter */ #define CFG_TMCNTSC (TMCNTSC_SEC |\ - TMCNTSC_ALR |\ - TMCNTSC_TCF |\ - TMCNTSC_TCE) + TMCNTSC_ALR |\ + TMCNTSC_TCF |\ + TMCNTSC_TCE) /*----------------------------------------------------------------------- * PISCR - Periodic Interrupt Status and Control 4-42 @@ -552,8 +552,8 @@ * Periodic timer */ /*#define CFG_PISCR (PISCR_PS |\ - PISCR_PTF |\ - PISCR_PTE)*/ + PISCR_PTF |\ + PISCR_PTE)*/ #define CFG_PISCR 0 /*----------------------------------------------------------------------- * SCCR - System Clock Control 9-8 @@ -604,29 +604,29 @@ * */ #define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ + BRx_PS_64 |\ BRx_DECC_NONE |\ - BRx_MS_GPCM_P |\ - BRx_V) + BRx_MS_GPCM_P |\ + BRx_V) #define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_6_CLK |\ - ORxG_EHTR) + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_6_CLK |\ + ORxG_EHTR) /* Bank 1 - SDRAM * PSDRAM */ #define CFG_BR1_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) #define CFG_OR1_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI1_A6 |\ - ORxS_NUMR_12) + ORxS_BPD_4 |\ + ORxS_ROWST_PBI1_A6 |\ + ORxS_NUMR_12) #define CFG_PSDMR 0xC34E2462 #define CFG_PSRT 0x64 @@ -638,14 +638,14 @@ */ #define CFG_BR2_PRELIM ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_SDRAM_L |\ - BRx_V) + BRx_PS_32 |\ + BRx_MS_SDRAM_L |\ + BRx_V) #define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM1_SIZE) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A9 |\ - ORxS_NUMR_12) + ORxS_BPD_4 |\ + ORxS_ROWST_PBI0_A9 |\ + ORxS_NUMR_12) #define CFG_LSDMR 0x416A2562 #define CFG_LSRT 0x64 @@ -657,15 +657,15 @@ * NVRTC and BCSR */ #define CFG_BR4_PRELIM ((CFG_REGS_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) /* #define CFG_OR4_PRELIM (ORxG_AM_MSK |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_10_CLK |\ - ORxG_TRLX) + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_10_CLK |\ + ORxG_TRLX) */ #define CFG_OR4_PRELIM 0xfff00854 @@ -673,15 +673,15 @@ * PCMCIA (currently not working!) */ #define CFG_BR8_PRELIM ((CFG_REGS_BASE & BRx_BA_MSK) |\ - BRx_PS_16 |\ - BRx_MS_GPCM_P |\ - BRx_V) + BRx_PS_16 |\ + BRx_MS_GPCM_P |\ + BRx_V) #define CFG_OR8_PRELIM (ORxG_AM_MSK |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ ORxG_SETA |\ - ORxG_SCY_10_CLK) + ORxG_SCY_10_CLK) /* * Internal Definitions diff --git a/include/configs/gw8260.h b/include/configs/gw8260.h index 0e9a4ec90e2..3666bdbb7e9 100644 --- a/include/configs/gw8260.h +++ b/include/configs/gw8260.h @@ -219,10 +219,10 @@ #define MDIO_READ ((iop->pdat & 0x00400000) != 0) #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ - else iop->pdat &= ~0x00400000 + else iop->pdat &= ~0x00400000 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ - else iop->pdat &= ~0x00200000 + else iop->pdat &= ~0x00200000 #define MIIDELAY udelay(1) #endif /* CONFIG_ETHER_ON_FCC */ @@ -291,8 +291,8 @@ * - DNS */ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE | \ - CONFIG_BOOTP_DNS) + CONFIG_BOOTP_BOOTFILESIZE | \ + CONFIG_BOOTP_DNS) /* undef this to save memory */ #define CFG_LONGHELP @@ -302,13 +302,13 @@ /* What U-Boot subsytems do you want enabled? */ #define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_ELF | \ - CFG_CMD_ASKENV | \ - CFG_CMD_ECHO | \ - CFG_CMD_REGINFO | \ - CFG_CMD_IMMAP | \ - CFG_CMD_MII) + CFG_CMD_BEDBUG | \ + CFG_CMD_ELF | \ + CFG_CMD_ASKENV | \ + CFG_CMD_ECHO | \ + CFG_CMD_REGINFO | \ + CFG_CMD_IMMAP | \ + CFG_CMD_MII) /* Where do the internal registers live? */ #define CFG_IMMR 0xf0000000 @@ -367,12 +367,12 @@ #define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */ #define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \ - + CFG_MALLOC_LEN \ - + CFG_ENV_SECT_SIZE \ - + CFG_STACK_USAGE ) + + CFG_MALLOC_LEN \ + + CFG_ENV_SECT_SIZE \ + + CFG_STACK_USAGE ) #define CFG_MEMTEST_END ( CFG_SDRAM_SIZE * 1024 * 1024 \ - - CFG_MEM_END_USAGE ) + - CFG_MEM_END_USAGE ) /* valid baudrates */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } @@ -399,18 +399,18 @@ /* get the HRCW ISB field from CFG_IMMR */ #define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) | \ - ((CFG_IMMR & 0x01000000) >> 7) | \ - ((CFG_IMMR & 0x00100000) >> 4) ) + ((CFG_IMMR & 0x01000000) >> 7) | \ + ((CFG_IMMR & 0x00100000) >> 4) ) #define CFG_HRCW_MASTER ( HRCW_BPS11 | \ - HRCW_DPPC11 | \ - CFG_SBC_HRCW_IMMR | \ - HRCW_MMR00 | \ - HRCW_LBPC11 | \ - HRCW_APPC10 | \ - HRCW_CS10PC00 | \ - (CFG_SBC_MODCK_H & HRCW_MODCK_H1111) | \ - CFG_SBC_HRCW_BOOT_FLAGS ) + HRCW_DPPC11 | \ + CFG_SBC_HRCW_IMMR | \ + HRCW_MMR00 | \ + HRCW_LBPC11 | \ + HRCW_APPC10 | \ + HRCW_CS10PC00 | \ + (CFG_SBC_MODCK_H & HRCW_MODCK_H1111) | \ + CFG_SBC_HRCW_BOOT_FLAGS ) /* no slaves */ #define CFG_HRCW_SLAVE1 0 @@ -488,16 +488,16 @@ * HID1 has only read-only information - nothing to set. */ #define CFG_HID0_INIT (HID0_ICE |\ - HID0_DCE |\ - HID0_ICFI |\ - HID0_DCI |\ - HID0_IFEM |\ - HID0_ABE) + HID0_DCE |\ + HID0_ICFI |\ + HID0_DCI |\ + HID0_IFEM |\ + HID0_ABE) #define CFG_HID0_FINAL (HID0_ICE |\ - HID0_IFEM |\ - HID0_ABE |\ - HID0_EMCP) + HID0_IFEM |\ + HID0_ABE |\ + HID0_EMCP) #define CFG_HID2 0 /*----------------------------------------------------------------------- @@ -517,9 +517,9 @@ *----------------------------------------------------------------------- */ #define CFG_SIUMCR (SIUMCR_DPPC11 |\ - SIUMCR_L2CPC00 |\ - SIUMCR_APPC10 |\ - SIUMCR_MMR00) + SIUMCR_L2CPC00 |\ + SIUMCR_APPC10 |\ + SIUMCR_MMR00) /*----------------------------------------------------------------------- @@ -529,11 +529,11 @@ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable */ #define CFG_SYPCR (SYPCR_SWTC |\ - SYPCR_BMT |\ - SYPCR_PBME |\ - SYPCR_LBME |\ - SYPCR_SWRI |\ - SYPCR_SWP) + SYPCR_BMT |\ + SYPCR_PBME |\ + SYPCR_LBME |\ + SYPCR_SWRI |\ + SYPCR_SWP) /*----------------------------------------------------------------------- * TMCNTSC - Time Counter Status and Control 4-40 @@ -542,9 +542,9 @@ * and enable Time Counter */ #define CFG_TMCNTSC (TMCNTSC_SEC |\ - TMCNTSC_ALR |\ - TMCNTSC_TCF |\ - TMCNTSC_TCE) + TMCNTSC_ALR |\ + TMCNTSC_TCF |\ + TMCNTSC_TCE) /*----------------------------------------------------------------------- * PISCR - Periodic Interrupt Status and Control 4-42 @@ -553,8 +553,8 @@ * Periodic timer */ #define CFG_PISCR (PISCR_PS |\ - PISCR_PTF |\ - PISCR_PTE) + PISCR_PTF |\ + PISCR_PTE) /*----------------------------------------------------------------------- * SCCR - System Clock Control 9-8 @@ -613,9 +613,9 @@ * - Valid */ #define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_GPCM_P |\ - BRx_V) + BRx_PS_32 |\ + BRx_MS_GPCM_P |\ + BRx_V) /* OR0 is configured as follows: * @@ -632,11 +632,11 @@ * current bank and the next access. */ #define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX |\ - ORxG_EHTR) + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_5_CLK |\ + ORxG_TRLX |\ + ORxG_EHTR) /*----------------------------------------------------------------------- * BR2 - Base Register @@ -668,9 +668,9 @@ * - Valid */ #define CFG_BR2_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) /* With a 16 MB DIMM, the OR2 is configured as follows: * @@ -683,9 +683,9 @@ */ #if (CFG_SDRAM0_SIZE == 16) #define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\ - ORxS_BPD_2 |\ - ORxS_ROWST_PBI0_A9 |\ - ORxS_NUMR_11) + ORxS_BPD_2 |\ + ORxS_ROWST_PBI0_A9 |\ + ORxS_NUMR_11) /* With a 16 MB DIMM, the PSDMR is configured as follows: * @@ -711,15 +711,15 @@ *----------------------------------------------------------------------- */ #define CFG_PSDMR (PSDMR_RFEN |\ - PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A16_A18 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_3W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) + PSDMR_SDAM_A14_IS_A5 |\ + PSDMR_BSMA_A16_A18 |\ + PSDMR_SDA10_PBI0_A9 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_3W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_1C |\ + PSDMR_CL_2) #endif /* (CFG_SDRAM0_SIZE == 16) */ /* With a 64 MB DIMM, the OR2 is configured as follows: @@ -733,9 +733,9 @@ */ #if (CFG_SDRAM0_SIZE == 64) #define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\ - ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A8 |\ - ORxS_NUMR_12) + ORxS_BPD_4 |\ + ORxS_ROWST_PBI0_A8 |\ + ORxS_NUMR_12) /* With a 64 MB DIMM, the PSDMR is configured as follows: * @@ -761,15 +761,15 @@ *----------------------------------------------------------------------- */ #define CFG_PSDMR (PSDMR_RFEN |\ - PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A14_A16 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_7_CLK |\ - PSDMR_PRETOACT_3W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) + PSDMR_SDAM_A14_IS_A5 |\ + PSDMR_BSMA_A14_A16 |\ + PSDMR_SDA10_PBI0_A9 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_3W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_1C |\ + PSDMR_CL_2) #endif /* (CFG_SDRAM0_SIZE == 64) */ #define CFG_PSRT 0x0e @@ -800,13 +800,13 @@ #ifdef CFG_IO_BASE # define CFG_BR4_PRELIM ((CFG_IO_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_L |\ - BRx_V) + BRx_PS_8 |\ + BRx_MS_GPCM_L |\ + BRx_V) # define CFG_OR4_PRELIM (ORxG_AM_MSK |\ - ORxG_SCY_11_CLK |\ - ORxG_EHTR) + ORxG_SCY_11_CLK |\ + ORxG_EHTR) #endif /* CFG_IO_BASE */ /* diff --git a/include/configs/innokom.h b/include/configs/innokom.h index 60699fec458..cfe9032893d 100644 --- a/include/configs/innokom.h +++ b/include/configs/innokom.h @@ -113,7 +113,7 @@ #define CFG_MONITOR_LEN 0x20000 /* 128 KiB */ - /* valid baudrates */ + /* valid baudrates */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* @@ -175,7 +175,7 @@ * JFFS2 Partitions */ #define CFG_JFFS_CUSTOM_PART 1 /* see board/innokom/flash.c */ -#define CONFIG_MTD_INNOKOM_16MB 1 /* development flash */ +#define CONFIG_MTD_INNOKOM_16MB 1 /* development flash */ #undef CONFIG_MTD_INNOKOM_64MB /* production flash */ diff --git a/include/configs/logodl.h b/include/configs/logodl.h index cb737fc2da6..2aee461fdd8 100644 --- a/include/configs/logodl.h +++ b/include/configs/logodl.h @@ -113,7 +113,7 @@ #define CFG_MONITOR_LEN 0x20000 /* 128 KiB */ - /* valid baudrates */ + /* valid baudrates */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* @@ -227,12 +227,12 @@ #define CFG_GAFR0_L_VAL (_BIT22+_BIT24+_BIT31) #define CFG_GAFR0_U_VAL (_BIT15+_BIT17+_BIT19+\ - _BIT20+_BIT22+_BIT24+_BIT26+_BIT29+_BIT31) + _BIT20+_BIT22+_BIT24+_BIT26+_BIT29+_BIT31) #define CFG_GAFR1_L_VAL (_BIT3+_BIT4+_BIT6+_BIT8+_BIT10+_BIT12+_BIT15+_BIT17+_BIT19+\ - _BIT20+_BIT23+_BIT24+_BIT27+_BIT28+_BIT31) + _BIT20+_BIT23+_BIT24+_BIT27+_BIT28+_BIT31) #define CFG_GAFR1_U_VAL (_BIT21+_BIT23+_BIT25+_BIT27+_BIT29+_BIT31) #define CFG_GAFR2_L_VAL (_BIT1+_BIT3+_BIT5+_BIT7+_BIT9+_BIT11+_BIT13+_BIT15+_BIT17+\ - _BIT19+_BIT21+_BIT23+_BIT25+_BIT27+_BIT29+_BIT31) + _BIT19+_BIT21+_BIT23+_BIT25+_BIT27+_BIT29+_BIT31) #define CFG_GAFR2_U_VAL (_BIT1) #define CFG_PSSR_VAL (0x20) @@ -283,4 +283,3 @@ #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ #endif /* __CONFIG_H */ - diff --git a/include/configs/rsdproto.h b/include/configs/rsdproto.h index 95faa417f61..d71b3e9f246 100644 --- a/include/configs/rsdproto.h +++ b/include/configs/rsdproto.h @@ -211,16 +211,16 @@ /* get the HRCW ISB field from CFG_IMMR */ #define CFG_RSD_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) |\ - ((CFG_IMMR & 0x01000000) >> 7) |\ - ((CFG_IMMR & 0x00100000) >> 4) ) + ((CFG_IMMR & 0x01000000) >> 7) |\ + ((CFG_IMMR & 0x00100000) >> 4) ) #define CFG_HRCW_MASTER (HRCW_L2CPC10 | \ HRCW_DPPC11 | \ - CFG_RSD_HRCW_IMMR |\ - HRCW_MMR00 | \ - HRCW_APPC10 | \ - HRCW_CS10PC00 | \ - HRCW_MODCK_H0000 |\ + CFG_RSD_HRCW_IMMR |\ + HRCW_MMR00 | \ + HRCW_APPC10 | \ + HRCW_CS10PC00 | \ + HRCW_MODCK_H0000 |\ CFG_RSD_HRCW_BOOT_FLAGS) /* no slaves */ @@ -388,9 +388,9 @@ /* Virtex-FPGA - Register */ #define CFG_BR3_PRELIM (PHYS_VIRTEX_REGISTER | BRx_V) #define CFG_OR3_PRELIM (ORxS_SIZE_TO_AM(PHYS_VIRTEX_REGISTER_SIZE) | \ - ORxG_SCY_1_CLK | \ - ORxG_ACS_DIV2 | \ - ORxG_CSNT ) + ORxG_SCY_1_CLK | \ + ORxG_ACS_DIV2 | \ + ORxG_CSNT ) /* local bus SDRAM */ #define CFG_BR4_PRELIM (PHYS_SDRAM_LOCAL | BRx_PS_32 | BRx_MS_SDRAM_L | BRx_V) diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h index 7accf745abb..6fd8abc9c3b 100644 --- a/include/configs/sacsng.h +++ b/include/configs/sacsng.h @@ -256,8 +256,8 @@ */ #define CONFIG_SOFT_SPI /* Enable SPI driver */ #define MAX_SPI_BYTES 4 /* Maximum number of bytes we can handle */ -#undef DEBUG_SPI /* Disable SPI debugging */ - +#undef DEBUG_SPI /* Disable SPI debugging */ + /* * Software (bit-bang) SPI driver configuration */ @@ -273,9 +273,9 @@ #undef SPI_INIT /* no port initialization needed */ #define SPI_READ ((immr->im_ioport.iop_pdatd & I2C_MISO) != 0) #define SPI_SDA(bit) if(bit) immr->im_ioport.iop_pdatd |= I2C_MOSI; \ - else immr->im_ioport.iop_pdatd &= ~I2C_MOSI + else immr->im_ioport.iop_pdatd &= ~I2C_MOSI #define SPI_SCL(bit) if(bit) immr->im_ioport.iop_pdatd |= I2C_SCLK; \ - else immr->im_ioport.iop_pdatd &= ~I2C_SCLK + else immr->im_ioport.iop_pdatd &= ~I2C_SCLK #define SPI_DELAY /* No delay is needed */ #endif /* CONFIG_SOFT_SPI */ diff --git a/include/configs/sbc8260.h b/include/configs/sbc8260.h index d47c208f163..1822fbc2246 100644 --- a/include/configs/sbc8260.h +++ b/include/configs/sbc8260.h @@ -284,7 +284,7 @@ /* What should the console's baud rate be? */ #define CONFIG_BAUDRATE 9600 -/* Ethernet MAC address +/* Ethernet MAC address * Note: We are using the EST Corporation OUI (00:a0:1e:xx:xx:xx) * http://standards.ieee.org/regauth/oui/index.shtml */ @@ -315,38 +315,38 @@ /* Define this to contain any number of null terminated strings that * will be part of the default enviroment compiled into the boot image. - * + * * Variable Usage * -------------- ------------------------------------------------------- - * serverip server IP address + * serverip server IP address * ipaddr my IP address * reprog Reload flash with a new copy of U-Boot * zapenv Erase the environment area in flash * root-on-initrd Set the bootcmd variable to allow booting of an initial * ram disk. - * root-on-nfs Set the bootcmd variable to allow booting of a NFS + * root-on-nfs Set the bootcmd variable to allow booting of a NFS * mounted root filesystem. - * boot-hook Convenient stub to do something useful before the + * boot-hook Convenient stub to do something useful before the * bootm command is executed. - * + * * Example usage of root-on-initrd and root-on-nfs : * * Note: The lines have been wrapped to improved its readability. * * => printenv bootcmd * bootcmd=version;echo;bootp;setenv bootargs root=/dev/nfs rw - * nfsroot=$(serverip):$(rootpath) + * nfsroot=$(serverip):$(rootpath) * ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;run boot-hook;bootm * * => run root-on-initrd * => printenv bootcmd * bootcmd=version;echo;bootp;setenv bootargs root=/dev/ram0 rw * ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;run boot-hook;bootm - * + * * => run root-on-nfs * => printenv bootcmd * bootcmd=version;echo;bootp;setenv bootargs root=/dev/nfs rw - * nfsroot=$(serverip):$(rootpath) + * nfsroot=$(serverip):$(rootpath) * ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;run boot-hook;bootm * */ diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h index 292b4bf3f12..764efdf7206 100644 --- a/include/configs/sc520_cdp.h +++ b/include/configs/sc520_cdp.h @@ -37,7 +37,7 @@ #define CONFIG_SC520 1 /* Include support for AMD SC520 */ #define CONFIG_ALI152X 1 /* Include support for Ali 152x SIO */ -#define CFG_SDRAM_PRECHARGE_DELAY 6 /* 6T */ +#define CFG_SDRAM_PRECHARGE_DELAY 6 /* 6T */ #define CFG_SDRAM_REFRESH_RATE 78 /* 7.8uS (choices are 7.8, 15.6, 31.2 or 62.5uS) */ #define CFG_SDRAM_RAS_CAS_DELAY 3 /* 3T */ @@ -123,7 +123,7 @@ #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ #define CONFIG_SPI_EEPROM /* Support for SPI EEPROMs (AT25128) */ -#define CONFIG_MW_EEPROM /* Support for MicroWire EEPROMs (AT93LC46) */ +#define CONFIG_MW_EEPROM /* Support for MicroWire EEPROMs (AT93LC46) */ /* allow to overwrite serial and ethaddr */ @@ -134,7 +134,7 @@ #define CFG_ENV_IS_IN_EEPROM 1 #define CONFIG_SPI #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment EEPROM 16k is SPI is used or 128 bytes if MW is used*/ -#define CFG_ENV_OFFSET 0 +#define CFG_ENV_OFFSET 0 #define CONFIG_SC520_CDP_USE_SPI /* Store configuration in the SPI part */ #undef CONFIG_SC520_CDP_USE_MW /* Store configuration in the MicroWire part */ #define CONFIG_SPI_X 1 @@ -157,7 +157,7 @@ #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ #define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ -//#define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */ +/*#define CFG_ATA_IDE1_OFFSET 0x0170 /###* ide1 offset */ #define CFG_ATA_DATA_OFFSET 0 /* data reg offset */ #define CFG_ATA_REG_OFFSET 0 /* reg offset */ #define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */ @@ -187,7 +187,6 @@ #define CFG_ISA_IO 0 - /************************************************************ * RTC ***********************************************************/ @@ -202,9 +201,8 @@ #define CONFIG_PCI_SCAN_SHOW #define CFG_FIRST_PCI_IRQ 10 -#define CFG_SECOND_PCI_IRQ 9 -#define CFG_THIRD_PCI_IRQ 11 +#define CFG_SECOND_PCI_IRQ 9 +#define CFG_THIRD_PCI_IRQ 11 #define CFG_FORTH_PCI_IRQ 15 - #endif /* __CONFIG_H */ diff --git a/include/configs/sc520_spunk.h b/include/configs/sc520_spunk.h index 0a28805fda0..9d26beb21df 100644 --- a/include/configs/sc520_spunk.h +++ b/include/configs/sc520_spunk.h @@ -189,8 +189,6 @@ #define CONFIG_ISO_PARTITION /* Experimental */ - - /************************************************************ * RTC ***********************************************************/ @@ -209,5 +207,4 @@ #define CFG_THIRD_PCI_IRQ 11 #define CFG_FORTH_PCI_IRQ 12 - #endif /* __CONFIG_H */ diff --git a/include/configs/sc520_spunk_rel.h b/include/configs/sc520_spunk_rel.h index 2d53530f3fd..2e7a7e1fa2c 100644 --- a/include/configs/sc520_spunk_rel.h +++ b/include/configs/sc520_spunk_rel.h @@ -27,6 +27,6 @@ #include "sc520_spunk.h" #undef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTCOMMAND "fsload boot/vmlinuz ; bootm" +#define CONFIG_BOOTCOMMAND "fsload boot/vmlinuz ; bootm" #endif diff --git a/include/configs/svm_sc8xx.h b/include/configs/svm_sc8xx.h index b46b0be9241..e9e86f6d811 100644 --- a/include/configs/svm_sc8xx.h +++ b/include/configs/svm_sc8xx.h @@ -92,22 +92,22 @@ #undef CONFIG_BOOTARGS #define CONFIG_EXTRA_ENV_SETTINGS \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm $(kernel_addr)\0" \ - "flash_self=run ramargs addip;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 0x210000 $(bootfile);run nfsargs addip;bootm\0" \ - "rootpath=/opt/sinovee/ppc8xx-linux-2.0/target\0" \ - "bootfile=pImage-sc855t\0" \ - "kernel_addr=48000000\0" \ - "ramdisk_addr=48100000\0" \ - "" + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath)\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ + ":$(hostname):$(netdev):off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm $(kernel_addr)\0" \ + "flash_self=run ramargs addip;" \ + "bootm $(kernel_addr) $(ramdisk_addr)\0" \ + "net_nfs=tftp 0x210000 $(bootfile);run nfsargs addip;bootm\0" \ + "rootpath=/opt/sinovee/ppc8xx-linux-2.0/target\0" \ + "bootfile=pImage-sc855t\0" \ + "kernel_addr=48000000\0" \ + "ramdisk_addr=48100000\0" \ + "" #define CONFIG_BOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ @@ -133,8 +133,8 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ CFG_CMD_DOC | \ /* CFG_CMD_IDE |*/ \ CFG_CMD_DATE ) @@ -272,7 +272,7 @@ */ #ifndef CONFIG_CAN_DRIVER /*#define CFG_SIUMCR 0x00610c00 */ -#define CFG_SIUMCR 0x00000000 +#define CFG_SIUMCR 0x00000000 #else /* we must activate GPL5 in the SIUMCR for CAN */ #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) #endif /* CONFIG_CAN_DRIVER */ @@ -309,16 +309,16 @@ #elif defined (CONFIG_80MHz) #define CFG_PLPRCR 0x04f01000 #define CONFIG_8xx_GCLK_FREQ 80000000 -#elif defined(CONFIG_75MHz) -#define CFG_PLPRCR 0x04a00100 +#elif defined(CONFIG_75MHz) +#define CFG_PLPRCR 0x04a00100 #define CONFIG_8xx_GCLK_FREQ 75000000 -#elif defined(CONFIG_66MHz) -#define CFG_PLPRCR 0x04101000 +#elif defined(CONFIG_66MHz) +#define CFG_PLPRCR 0x04101000 #define CONFIG_8xx_GCLK_FREQ 66000000 -#elif defined(CONFIG_50MHz) -#define CFG_PLPRCR 0x03101000 +#elif defined(CONFIG_50MHz) +#define CFG_PLPRCR 0x03101000 #define CONFIG_8xx_GCLK_FREQ 50000000 -#endif +#endif /*----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register 15-27 @@ -327,11 +327,11 @@ * power management and some other internal clocks */ #define SCCR_MASK SCCR_EBDF11 -#ifdef CONFIG_BUS_DIV2 +#ifdef CONFIG_BUS_DIV2 #define CFG_SCCR 0x02020000 | SCCR_RTSEL #else /* up to 50 MHz we use a 1:1 clock */ #define CFG_SCCR 0x02000000 | SCCR_RTSEL -#endif +#endif /*----------------------------------------------------------------------- * PCMCIA stuff @@ -370,7 +370,7 @@ */ #define CFG_ATA_ALT_OFFSET 0x0210 /* Offset for alternate registers */ -#define CONFIG_ATAPI +#define CONFIG_ATAPI #define CFG_PIO_MODE 0 /*----------------------------------------------------------------------- @@ -400,35 +400,35 @@ /* * FLASH timing: */ -#if defined(CONFIG_100MHz) -#define CFG_OR_TIMING_FLASH 0x000002f4 -#define CFG_OR_TIMING_DOC 0x000002f4 +#if defined(CONFIG_100MHz) +#define CFG_OR_TIMING_FLASH 0x000002f4 +#define CFG_OR_TIMING_DOC 0x000002f4 #define CFG_MxMR_PTx 0x61000000 #define CFG_MPTPR 0x400 #elif defined(CONFIG_80MHz) -#define CFG_OR_TIMING_FLASH 0x00000ff4 -#define CFG_OR_TIMING_DOC 0x000001f4 +#define CFG_OR_TIMING_FLASH 0x00000ff4 +#define CFG_OR_TIMING_DOC 0x000001f4 #define CFG_MxMR_PTx 0x4e000000 #define CFG_MPTPR 0x400 -#elif defined(CONFIG_75MHz) -#define CFG_OR_TIMING_FLASH 0x000008f4 -#define CFG_OR_TIMING_DOC 0x000002f4 +#elif defined(CONFIG_75MHz) +#define CFG_OR_TIMING_FLASH 0x000008f4 +#define CFG_OR_TIMING_DOC 0x000002f4 #define CFG_MxMR_PTx 0x49000000 #define CFG_MPTPR 0x400 #elif defined(CONFIG_66MHz) #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) + OR_SCY_3_CLK | OR_EHTR | OR_BI) /*#define CFG_OR_TIMING_FLASH 0x000001f4 */ -#define CFG_OR_TIMING_DOC 0x000003f4 +#define CFG_OR_TIMING_DOC 0x000003f4 #define CFG_MxMR_PTx 0x40000000 #define CFG_MPTPR 0x400 #else /* 50 MHz */ #define CFG_OR_TIMING_FLASH 0x00000ff4 -#define CFG_OR_TIMING_DOC 0x000001f4 +#define CFG_OR_TIMING_DOC 0x000001f4 #define CFG_MxMR_PTx 0x30000000 #define CFG_MPTPR 0x400 #endif /*CONFIG_??MHz */ diff --git a/include/configs/v37.h b/include/configs/v37.h index f5274404a9c..6696985bf5c 100644 --- a/include/configs/v37.h +++ b/include/configs/v37.h @@ -376,6 +376,4 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ - - #endif /* __CONFIG_H */ diff --git a/include/configs/wepep250.h b/include/configs/wepep250.h index c88c4ab5ce2..ecb7215e2e6 100644 --- a/include/configs/wepep250.h +++ b/include/configs/wepep250.h @@ -1,4 +1,4 @@ -/* +/* * Copyright (C) 2003 ETC s.r.o. * * This program is free software; you can redistribute it and/or @@ -52,7 +52,7 @@ /* * Boot options. Setting delay to -1 stops autostart count down. * NOTE: Sending parameters to kernel depends on kernel version and - * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept + * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept * parameters at all! Do not get confused by them so. */ #define CONFIG_BOOTDELAY -1 @@ -71,7 +71,7 @@ #define CFG_BARGSIZE CFG_CBSIZE /* boot args buf size */ #define CFG_MEMTEST_START 0xa0400000 /* memtest test area */ -#define CFG_MEMTEST_END 0xa0800000 +#define CFG_MEMTEST_END 0xa0800000 #undef CFG_CLKS_IN_HZ /* use HZ for freq. display */ @@ -128,7 +128,7 @@ #define CFG_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ #define CFG_MAX_FLASH_SECT 128 /* number of sector in FLASH bank */ #define WEP_FLASH_BUS_WIDTH 4 /* we use 32 bit FLASH memory... */ -#define WEP_FLASH_INTERLEAVE 2 /* ... made of 2 chips */ +#define WEP_FLASH_INTERLEAVE 2 /* ... made of 2 chips */ #define WEP_FLASH_BANK_SIZE 0x2000000 /* size of one flash bank*/ #define WEP_FLASH_SECT_SIZE 0x0040000 /* size of erase sector */ #define WEP_FLASH_BASE 0x0000000 /* location of flash memory */ @@ -137,9 +137,9 @@ /* This should be defined if CFI FLASH device is present. Actually benefit is not so clear to me. In other words we can provide more informations - to user, but this expects more complex flash handling we do not provide + to user, but this expects more complex flash handling we do not provide now.*/ -#undef CFG_FLASH_CFI +#undef CFG_FLASH_CFI #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* timeout for Erase operation */ #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* timeout for Write operation */ @@ -173,7 +173,7 @@ #define CFG_MONITOR_LEN 0x20000 /* 128kb ( 1 flash sector ) */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_ADDR 0x20000 /* absolute address for now */ -#define CFG_ENV_SIZE 0x2000 +#define CFG_ENV_SIZE 0x2000 #undef CONFIG_ENV_OVERWRITE /* env is not writable now */ @@ -185,4 +185,3 @@ #define CFG_LOAD_ADDR 0x40000 #endif /* __CONFIG_H */ - diff --git a/include/dataflash.h b/include/dataflash.h index cc4badfd16b..5e1186388e7 100644 --- a/include/dataflash.h +++ b/include/dataflash.h @@ -91,7 +91,6 @@ typedef struct _AT91S_DataFlash { } AT91S_DataFlash, *AT91PS_DataFlash; - typedef struct _AT91S_DATAFLASH_INFO { AT91S_DataflashDesc Desc; diff --git a/include/dm9161.h b/include/dm9161.h index 62999210a33..706e215af35 100644 --- a/include/dm9161.h +++ b/include/dm9161.h @@ -1,5 +1,5 @@ /* - * NOTE: DAVICOM ethernet Physical layer + * NOTE: DAVICOM ethernet Physical layer * * Version: @(#)DM9161.h 1.0.0 01/10/2001 * @@ -13,36 +13,36 @@ */ -// DAVICOM PHYSICAL LAYER TRANSCEIVER DM9161 - -#define DM9161_BMCR 0 // Basic Mode Control Register -#define DM9161_BMSR 1 // Basic Mode Status Register -#define DM9161_PHYID1 2 // PHY Idendifier Register 1 -#define DM9161_PHYID2 3 // PHY Idendifier Register 2 -#define DM9161_ANAR 4 // Auto_Negotiation Advertisement Register -#define DM9161_ANLPAR 5 // Auto_negotiation Link Partner Ability Register -#define DM9161_ANER 6 // Auto-negotiation Expansion Register -#define DM9161_DSCR 16 // Specified Configuration Register -#define DM9161_DSCSR 17 // Specified Configuration and Status Register -#define DM9161_10BTCSR 18 // 10BASE-T Configuration and Satus Register -#define DM9161_MDINTR 21 // Specified Interrupt Register -#define DM9161_RECR 22 // Specified Receive Error Counter Register -#define DM9161_DISCR 23 // Specified Disconnect Counter Register -#define DM9161_RLSR 24 // Hardware Reset Latch State Register - - -// --Bit definitions: DM9161_BMCR -#define DM9161_RESET (1 << 15) // 1= Software Reset; 0=Normal Operation -#define DM9161_LOOPBACK (1 << 14) // 1=loopback Enabled; 0=Normal Operation -#define DM9161_SPEED_SELECT (1 << 13) // 1=100Mbps; 0=10Mbps +/* DAVICOM PHYSICAL LAYER TRANSCEIVER DM9161 */ + +#define DM9161_BMCR 0 /* Basic Mode Control Register */ +#define DM9161_BMSR 1 /* Basic Mode Status Register */ +#define DM9161_PHYID1 2 /* PHY Idendifier Register 1 */ +#define DM9161_PHYID2 3 /* PHY Idendifier Register 2 */ +#define DM9161_ANAR 4 /* Auto_Negotiation Advertisement Register */ +#define DM9161_ANLPAR 5 /* Auto_negotiation Link Partner Ability Register */ +#define DM9161_ANER 6 /* Auto-negotiation Expansion Register */ +#define DM9161_DSCR 16 /* Specified Configuration Register */ +#define DM9161_DSCSR 17 /* Specified Configuration and Status Register */ +#define DM9161_10BTCSR 18 /* 10BASE-T Configuration and Satus Register */ +#define DM9161_MDINTR 21 /* Specified Interrupt Register */ +#define DM9161_RECR 22 /* Specified Receive Error Counter Register */ +#define DM9161_DISCR 23 /* Specified Disconnect Counter Register */ +#define DM9161_RLSR 24 /* Hardware Reset Latch State Register */ + + +/* --Bit definitions: DM9161_BMCR */ +#define DM9161_RESET (1 << 15) /* 1= Software Reset; 0=Normal Operation */ +#define DM9161_LOOPBACK (1 << 14) /* 1=loopback Enabled; 0=Normal Operation */ +#define DM9161_SPEED_SELECT (1 << 13) /* 1=100Mbps; 0=10Mbps */ #define DM9161_AUTONEG (1 << 12) #define DM9161_POWER_DOWN (1 << 11) -#define DM9161_ISOLATE (1 << 10) +#define DM9161_ISOLATE (1 << 10) #define DM9161_RESTART_AUTONEG (1 << 9) #define DM9161_DUPLEX_MODE (1 << 8) #define DM9161_COLLISION_TEST (1 << 7) -//--Bit definitions: DM9161_BMSR +/*--Bit definitions: DM9161_BMSR */ #define DM9161_100BASE_T4 (1 << 15) #define DM9161_100BASE_TX_FD (1 << 14) #define DM9161_100BASE_T4_HD (1 << 13) @@ -56,11 +56,11 @@ #define DM9161_JABBER_DETECT (1 << 1) #define DM9161_EXTEND_CAPAB (1 << 0) -//--definitions: DM9161_PHYID1 +/*--definitions: DM9161_PHYID1 */ #define DM9161_PHYID1_OUI 0x606E #define DM9161_LSB_MASK 0x3F -//--Bit definitions: DM9161_ANAR, DM9161_ANLPAR +/*--Bit definitions: DM9161_ANAR, DM9161_ANLPAR */ #define DM9161_NP (1 << 15) #define DM9161_ACK (1 << 14) #define DM9161_RF (1 << 13) @@ -72,14 +72,14 @@ #define DM9161_10_HDX (1 << 5) #define DM9161_AN_IEEE_802_3 0x0001 -//--Bit definitions: DM9161_ANER +/*--Bit definitions: DM9161_ANER */ #define DM9161_PDF (1 << 4) #define DM9161_LP_NP_ABLE (1 << 3) #define DM9161_NP_ABLE (1 << 2) #define DM9161_PAGE_RX (1 << 1) #define DM9161_LP_AN_ABLE (1 << 0) -//--Bit definitions: DM9161_DSCR +/*--Bit definitions: DM9161_DSCR */ #define DM9161_BP4B5B (1 << 15) #define DM9161_BP_SCR (1 << 14) #define DM9161_BP_ALIGN (1 << 13) @@ -96,13 +96,13 @@ #define DM9161_SLEEP (1 << 1) #define DM9161_RLOUT (1 << 0) -//--Bit definitions: DM9161_DSCSR +/*--Bit definitions: DM9161_DSCSR */ #define DM9161_100FDX (1 << 15) #define DM9161_100HDX (1 << 14) #define DM9161_10FDX (1 << 13) #define DM9161_10HDX (1 << 12) -//--Bit definitions: DM9161_10BTCSR +/*--Bit definitions: DM9161_10BTCSR */ #define DM9161_LP_EN (1 << 14) #define DM9161_HBE (1 << 13) #define DM9161_SQUELCH (1 << 12) @@ -111,7 +111,7 @@ #define DM9161_POLR (1 << 0) -//--Bit definitions: DM9161_MDINTR +/*--Bit definitions: DM9161_MDINTR */ #define DM9161_INTR_PEND (1 << 15) #define DM9161_FDX_MASK (1 << 11) #define DM9161_SPD_MASK (1 << 10) diff --git a/include/elf.h b/include/elf.h index ed238c37f46..1be294a945c 100644 --- a/include/elf.h +++ b/include/elf.h @@ -115,9 +115,9 @@ typedef uint16_t Elf32_Half; /* Unsigned medium integer */ /* e_ident */ #define IS_ELF(ehdr) ((ehdr).e_ident[EI_MAG0] == ELFMAG0 && \ - (ehdr).e_ident[EI_MAG1] == ELFMAG1 && \ - (ehdr).e_ident[EI_MAG2] == ELFMAG2 && \ - (ehdr).e_ident[EI_MAG3] == ELFMAG3) + (ehdr).e_ident[EI_MAG1] == ELFMAG1 && \ + (ehdr).e_ident[EI_MAG2] == ELFMAG2 && \ + (ehdr).e_ident[EI_MAG3] == ELFMAG3) /* ELF Header */ typedef struct elfhdr{ @@ -531,7 +531,7 @@ unsigned long elf_hash(const unsigned char *name); /* Cygnus local bits below */ #define EF_PPC_RELOCATABLE 0x00010000 /* PowerPC -mrelocatable flag*/ #define EF_PPC_RELOCATABLE_LIB 0x00008000 /* PowerPC -mrelocatable-lib - flag */ + flag */ /* PowerPC relocations defined by the ABIs */ #define R_PPC_NONE 0 @@ -606,4 +606,3 @@ unsigned long elf_hash(const unsigned char *name); #define R_PPC_TOC16 255 #endif /* _ELF_H */ - diff --git a/include/fdc.h b/include/fdc.h index 7892b0e25e0..b66f20212b1 100644 --- a/include/fdc.h +++ b/include/fdc.h @@ -25,8 +25,6 @@ #ifndef _FDC_H_ #define _FDC_H_ - - /* Functions prototype */ int fdc_fdos_init (int drive); int fdc_fdos_seek (int where); @@ -36,6 +34,4 @@ int dos_open(char *name); int dos_read (ulong addr); int dos_dir (void); - - #endif diff --git a/include/galileo/core.h b/include/galileo/core.h index 56db09782aa..0735d075b3c 100644 --- a/include/galileo/core.h +++ b/include/galileo/core.h @@ -123,18 +123,18 @@ typedef enum _bool{false,true} bool; #define SHORT_SWAP(X) ((X <<8 ) | (X >> 8)) #define WORD_SWAP(X) (((X)&0xff)<<24)+ \ - (((X)&0xff00)<<8)+ \ - (((X)&0xff0000)>>8)+ \ - (((X)&0xff000000)>>24) + (((X)&0xff00)<<8)+ \ + (((X)&0xff0000)>>8)+ \ + (((X)&0xff000000)>>24) #define LONG_SWAP(X) ( (l64) (((X)&0xffULL)<<56)+ \ - (((X)&0xff00ULL)<<40)+ \ - (((X)&0xff0000ULL)<<24)+ \ - (((X)&0xff000000ULL)<<8)+ \ - (((X)&0xff00000000ULL)>>8)+ \ - (((X)&0xff0000000000ULL)>>24)+ \ - (((X)&0xff000000000000ULL)>>40)+ \ - (((X)&0xff00000000000000ULL)>>56)) + (((X)&0xff00ULL)<<40)+ \ + (((X)&0xff0000ULL)<<24)+ \ + (((X)&0xff000000ULL)<<8)+ \ + (((X)&0xff00000000ULL)>>8)+ \ + (((X)&0xff0000000000ULL)>>24)+ \ + (((X)&0xff000000000000ULL)>>40)+ \ + (((X)&0xff00000000000000ULL)>>56)) #endif @@ -154,44 +154,44 @@ typedef enum _bool{false,true} bool; /* Read/Write to/from GT`s internal registers */ #define GT_REG_READ(offset, pData) \ *pData = ( *((volatile unsigned int *)(NONE_CACHEABLE | \ - INTERNAL_REG_BASE_ADDR | (offset))) ) ; \ + INTERNAL_REG_BASE_ADDR | (offset))) ) ; \ *pData = WORD_SWAP(*pData) #define GTREGREAD(offset) \ - (WORD_SWAP( *((volatile unsigned int *)(NONE_CACHEABLE | \ - INTERNAL_REG_BASE_ADDR | (offset))) )) + (WORD_SWAP( *((volatile unsigned int *)(NONE_CACHEABLE | \ + INTERNAL_REG_BASE_ADDR | (offset))) )) #define GT_REG_WRITE(offset, data) \ *((unsigned int *)( INTERNAL_REG_BASE_ADDR | (offset))) = \ - WORD_SWAP(data) + WORD_SWAP(data) /* Write 32/16/8 bit */ #define WRITE_CHAR(address, data) \ - *((unsigned char *)(address)) = data + *((unsigned char *)(address)) = data #define WRITE_SHORT(address, data) \ - *((unsigned short *)(address)) = data + *((unsigned short *)(address)) = data #define WRITE_WORD(address, data) \ - *((unsigned int *)(address)) = data + *((unsigned int *)(address)) = data /* Read 32/16/8 bits - returns data in variable. */ #define READ_CHAR(address, pData) \ - *pData = *((volatile unsigned char *)(address)) + *pData = *((volatile unsigned char *)(address)) #define READ_SHORT(address, pData) \ - *pData = *((volatile unsigned short *)(address)) + *pData = *((volatile unsigned short *)(address)) #define READ_WORD(address, pData) \ - *pData = *((volatile unsigned int *)(address)) + *pData = *((volatile unsigned int *)(address)) /* Read 32/16/8 bit - returns data direct. */ #define READCHAR(address) \ - *((volatile unsigned char *)((address) | NONE_CACHEABLE)) + *((volatile unsigned char *)((address) | NONE_CACHEABLE)) #define READSHORT(address) \ - *((volatile unsigned short *)((address) | NONE_CACHEABLE)) + *((volatile unsigned short *)((address) | NONE_CACHEABLE)) #define READWORD(address) \ - *((volatile unsigned int *)((address) | NONE_CACHEABLE)) + *((volatile unsigned int *)((address) | NONE_CACHEABLE)) /* Those two Macros were defined to be compatible with MIPS */ #define VIRTUAL_TO_PHY(x) (((unsigned int)x) & 0xffffffff) @@ -203,8 +203,8 @@ typedef enum _bool{false,true} bool; SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic '1' in register 0x840 while the other bits stays as is. */ #define SET_REG_BITS(regOffset,bits) \ - *(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR | \ - regOffset) |= (unsigned int)WORD_SWAP(bits) + *(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR | \ + regOffset) |= (unsigned int)WORD_SWAP(bits) /* RESET_REG_BITS(regOffset,bits) - gets register offset and bits: a 32bit value. It set to logic '0' in the @@ -212,7 +212,7 @@ typedef enum _bool{false,true} bool; RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic '0' in register 0x840 while the other bits stays as is. */ #define RESET_REG_BITS(regOffset,bits) \ - *(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR \ - | regOffset) &= ~( (unsigned int)WORD_SWAP(bits) ) + *(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR \ + | regOffset) &= ~( (unsigned int)WORD_SWAP(bits) ) #endif /* __INCcoreh */ diff --git a/include/galileo/gt64260R.h b/include/galileo/gt64260R.h index 1e6f58bb2b6..ebf087afca9 100644 --- a/include/galileo/gt64260R.h +++ b/include/galileo/gt64260R.h @@ -89,8 +89,6 @@ #define PCI_1MEMORY3_HIGH_ADDRESS_REMAP 0x358 - - /****************************************/ /* CPU Sync Barrier */ /****************************************/ @@ -231,7 +229,6 @@ #define X1_SNOOP_COMMAND 0x54c - /****************************************/ /* Device Parameters */ /****************************************/ diff --git a/include/galileo/memory.h b/include/galileo/memory.h index 99bd79ba6e9..0c46c24d065 100644 --- a/include/galileo/memory.h +++ b/include/galileo/memory.h @@ -36,20 +36,20 @@ typedef enum __memBank{BANK0,BANK1,BANK2,BANK3} MEMORY_BANK; typedef enum __memDevice{DEVICE0,DEVICE1,DEVICE2,DEVICE3,BOOT_DEVICE} DEVICE; typedef enum __memoryProtectRegion{MEM_REGION0,MEM_REGION1,MEM_REGION2, \ - MEM_REGION3,MEM_REGION4,MEM_REGION5, \ - MEM_REGION6,MEM_REGION7} \ - MEMORY_PROTECT_REGION; + MEM_REGION3,MEM_REGION4,MEM_REGION5, \ + MEM_REGION6,MEM_REGION7} \ + MEMORY_PROTECT_REGION; typedef enum __memoryAccess{MEM_ACCESS_ALLOWED,MEM_ACCESS_FORBIDEN} \ - MEMORY_ACCESS; + MEMORY_ACCESS; typedef enum __memoryWrite{MEM_WRITE_ALLOWED,MEM_WRITE_FORBIDEN} \ - MEMORY_ACCESS_WRITE; + MEMORY_ACCESS_WRITE; typedef enum __memoryCacheProtect{MEM_CACHE_ALLOWED,MEM_CACHE_FORBIDEN} \ - MEMORY_CACHE_PROTECT; + MEMORY_CACHE_PROTECT; typedef enum __memorySnoopType{MEM_NO_SNOOP,MEM_SNOOP_WT,MEM_SNOOP_WB} \ - MEMORY_SNOOP_TYPE; + MEMORY_SNOOP_TYPE; typedef enum __memorySnoopRegion{MEM_SNOOP_REGION0,MEM_SNOOP_REGION1, \ - MEM_SNOOP_REGION2,MEM_SNOOP_REGION3} \ - MEMORY_SNOOP_REGION; + MEM_SNOOP_REGION2,MEM_SNOOP_REGION3} \ + MEMORY_SNOOP_REGION; /* functions */ unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank); @@ -68,19 +68,18 @@ bool memoryMapInternalRegistersSpace(unsigned int internalRegBase); unsigned int memoryGetInternalRegistersSpace(void); /* Configurate the protection feature to a given space. */ bool memorySetProtectRegion(MEMORY_PROTECT_REGION region, - MEMORY_ACCESS memoryAccess, - MEMORY_ACCESS_WRITE memoryWrite, - MEMORY_CACHE_PROTECT cacheProtection, - unsigned int baseAddress, - unsigned int regionLength); + MEMORY_ACCESS memoryAccess, + MEMORY_ACCESS_WRITE memoryWrite, + MEMORY_CACHE_PROTECT cacheProtection, + unsigned int baseAddress, + unsigned int regionLength); /* Configurate the snoop feature to a given space. */ bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region, - MEMORY_SNOOP_TYPE snoopType, - unsigned int baseAddress, - unsigned int regionLength); + MEMORY_SNOOP_TYPE snoopType, + unsigned int baseAddress, + unsigned int regionLength); bool memoryRemapAddress(unsigned int remapReg, unsigned int remapValue); bool memoryGetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum); bool memorySetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum); #endif /* __INCmemoryh */ - diff --git a/include/galileo/pci.h b/include/galileo/pci.h index f45dd3617eb..6ed8b95df05 100644 --- a/include/galileo/pci.h +++ b/include/galileo/pci.h @@ -41,20 +41,20 @@ /* typedefs */ typedef enum __pciAccessRegions{REGION0,REGION1,REGION2,REGION3,REGION4,REGION5, - REGION6,REGION7} PCI_ACCESS_REGIONS; + REGION6,REGION7} PCI_ACCESS_REGIONS; typedef enum __pciAgentPrio{LOW_AGENT_PRIO,HI_AGENT_PRIO} PCI_AGENT_PRIO; typedef enum __pciAgentPark{PARK_ON_AGENT,DONT_PARK_ON_AGENT} PCI_AGENT_PARK; typedef enum __pciSnoopType{PCI_NO_SNOOP,PCI_SNOOP_WT,PCI_SNOOP_WB} - PCI_SNOOP_TYPE; + PCI_SNOOP_TYPE; typedef enum __pciSnoopRegion{PCI_SNOOP_REGION0,PCI_SNOOP_REGION1, - PCI_SNOOP_REGION2,PCI_SNOOP_REGION3} - PCI_SNOOP_REGION; + PCI_SNOOP_REGION2,PCI_SNOOP_REGION3} + PCI_SNOOP_REGION; typedef enum __memPciHost{PCI_HOST0,PCI_HOST1} PCI_HOST; typedef enum __memPciRegion{PCI_REGION0,PCI_REGION1, - PCI_REGION2,PCI_REGION3, + PCI_REGION2,PCI_REGION3, PCI_IO} PCI_REGION; @@ -62,23 +62,23 @@ typedef enum __memPciRegion{PCI_REGION0,PCI_REGION1, void pciWriteConfigReg(PCI_HOST host, unsigned int regOffset, unsigned int pciDevNum, unsigned int data); unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum); + unsigned int pciDevNum); /* read/write configuration registers on another PCI bus. */ void pciOverBridgeWriteConfigReg(PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum,unsigned int data); + unsigned int pciDevNum, + unsigned int busNum,unsigned int data); unsigned int pciOverBridgeReadConfigReg(PCI_HOST host, unsigned int regOffset, - unsigned int pciDevNum, - unsigned int busNum); + unsigned int pciDevNum, + unsigned int busNum); /* Master`s memory space */ bool pciMapSpace(PCI_HOST host, PCI_REGION region, unsigned int remapBase, unsigned int deviceBase, - unsigned int deviceLength); + unsigned int deviceLength); unsigned int pciGetSpaceBase(PCI_HOST host, PCI_REGION region); unsigned int pciGetSpaceSize(PCI_HOST host, PCI_REGION region); @@ -99,15 +99,15 @@ void pciDisableAccessRegion(PCI_HOST host, PCI_ACCESS_REGIONS region); bool pciArbiterEnable(PCI_HOST host); bool pciArbiterDisable(PCI_HOST host); bool pciParkingDisable(PCI_HOST host, PCI_AGENT_PARK internalAgent, - PCI_AGENT_PARK externalAgent0, - PCI_AGENT_PARK externalAgent1, - PCI_AGENT_PARK externalAgent2, - PCI_AGENT_PARK externalAgent3, - PCI_AGENT_PARK externalAgent4, - PCI_AGENT_PARK externalAgent5); + PCI_AGENT_PARK externalAgent0, + PCI_AGENT_PARK externalAgent1, + PCI_AGENT_PARK externalAgent2, + PCI_AGENT_PARK externalAgent3, + PCI_AGENT_PARK externalAgent4, + PCI_AGENT_PARK externalAgent5); bool pciSetRegionSnoopMode(PCI_HOST host, PCI_SNOOP_REGION region, PCI_SNOOP_TYPE snoopType, - unsigned int baseAddress, - unsigned int regionLength); + unsigned int baseAddress, + unsigned int regionLength); #endif /* __INCpcih */ diff --git a/include/jffs2/jffs2.h b/include/jffs2/jffs2.h index 909869006d1..fc3a8419a38 100644 --- a/include/jffs2/jffs2.h +++ b/include/jffs2/jffs2.h @@ -201,8 +201,4 @@ void dynrubin_decompress(unsigned char *data_in, unsigned char *cpage_out, long zlib_decompress(unsigned char *data_in, unsigned char *cpage_out, __u32 srclen, __u32 destlen); - - - - #endif /* __LINUX_JFFS2_H__ */ diff --git a/include/linux/bitops.h b/include/linux/bitops.h index b155b779696..7d41ae62ccf 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -44,26 +44,26 @@ static inline int generic_ffs(int x) static inline unsigned int generic_hweight32(unsigned int w) { - unsigned int res = (w & 0x55555555) + ((w >> 1) & 0x55555555); - res = (res & 0x33333333) + ((res >> 2) & 0x33333333); - res = (res & 0x0F0F0F0F) + ((res >> 4) & 0x0F0F0F0F); - res = (res & 0x00FF00FF) + ((res >> 8) & 0x00FF00FF); - return (res & 0x0000FFFF) + ((res >> 16) & 0x0000FFFF); + unsigned int res = (w & 0x55555555) + ((w >> 1) & 0x55555555); + res = (res & 0x33333333) + ((res >> 2) & 0x33333333); + res = (res & 0x0F0F0F0F) + ((res >> 4) & 0x0F0F0F0F); + res = (res & 0x00FF00FF) + ((res >> 8) & 0x00FF00FF); + return (res & 0x0000FFFF) + ((res >> 16) & 0x0000FFFF); } static inline unsigned int generic_hweight16(unsigned int w) { - unsigned int res = (w & 0x5555) + ((w >> 1) & 0x5555); - res = (res & 0x3333) + ((res >> 2) & 0x3333); - res = (res & 0x0F0F) + ((res >> 4) & 0x0F0F); - return (res & 0x00FF) + ((res >> 8) & 0x00FF); + unsigned int res = (w & 0x5555) + ((w >> 1) & 0x5555); + res = (res & 0x3333) + ((res >> 2) & 0x3333); + res = (res & 0x0F0F) + ((res >> 4) & 0x0F0F); + return (res & 0x00FF) + ((res >> 8) & 0x00FF); } static inline unsigned int generic_hweight8(unsigned int w) { - unsigned int res = (w & 0x55) + ((w >> 1) & 0x55); - res = (res & 0x33) + ((res >> 2) & 0x33); - return (res & 0x0F) + ((res >> 4) & 0x0F); + unsigned int res = (w & 0x55) + ((w >> 1) & 0x55); + res = (res & 0x33) + ((res >> 2) & 0x33); + return (res & 0x0F) + ((res >> 4) & 0x0F); } #include <asm/bitops.h> diff --git a/include/linux/byteorder/swab.h b/include/linux/byteorder/swab.h index 813df46c35e..755a8212e78 100644 --- a/include/linux/byteorder/swab.h +++ b/include/linux/byteorder/swab.h @@ -34,7 +34,7 @@ (__u64)(((__u64)(x) & (__u64)0x000000000000ff00ULL) << 40) | \ (__u64)(((__u64)(x) & (__u64)0x0000000000ff0000ULL) << 24) | \ (__u64)(((__u64)(x) & (__u64)0x00000000ff000000ULL) << 8) | \ - (__u64)(((__u64)(x) & (__u64)0x000000ff00000000ULL) >> 8) | \ + (__u64)(((__u64)(x) & (__u64)0x000000ff00000000ULL) >> 8) | \ (__u64)(((__u64)(x) & (__u64)0x0000ff0000000000ULL) >> 24) | \ (__u64)(((__u64)(x) & (__u64)0x00ff000000000000ULL) >> 40) | \ (__u64)(((__u64)(x) & (__u64)0xff00000000000000ULL) >> 56) )) @@ -127,8 +127,8 @@ extern __inline__ __const__ __u64 __fswab64(__u64 x) { # ifdef __SWAB_64_THRU_32__ __u32 h = x >> 32; - __u32 l = x & ((1ULL<<32)-1); - return (((__u64)__swab32(l)) << 32) | ((__u64)(__swab32(h))); + __u32 l = x & ((1ULL<<32)-1); + return (((__u64)__swab32(l)) << 32) | ((__u64)(__swab32(h))); # else return __arch__swab64(x); # endif diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 678bef736a9..d37055f6528 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -24,7 +24,7 @@ * bat later if I did something naughty. * 10-11-2000 SJH Added private NAND flash structure for driver * 10-24-2000 SJH Added prototype for 'nand_scan' function - * 10-29-2001 TG changed nand_chip structure to support + * 10-29-2001 TG changed nand_chip structure to support * hardwarespecific function for accessing control lines * 02-21-2002 TG added support for different read/write adress and * ready/busy line access function @@ -67,7 +67,7 @@ typedef enum { * * Structure overview: * - * IO_ADDR - address to access the 8 I/O lines of the flash device + * IO_ADDR - address to access the 8 I/O lines of the flash device * * hwcontrol - hardwarespecific function for accesing control-lines * @@ -119,8 +119,8 @@ struct nand_chip { char pageadrlen; unsigned long IO_ADDR; /* address to access the 8 I/O lines to the flash device */ unsigned long totlen; - uint oobblock; // Size of OOB blocks (e.g. 512) - uint oobsize; // Amount of OOB data per block (e.g. 16) + uint oobblock; /* Size of OOB blocks (e.g. 512) */ + uint oobsize; /* Amount of OOB data per block (e.g. 16) */ uint eccsize; }; diff --git a/include/linux/mtd/nftl.h b/include/linux/mtd/nftl.h index 37517582d59..438130625df 100644 --- a/include/linux/mtd/nftl.h +++ b/include/linux/mtd/nftl.h @@ -31,8 +31,8 @@ struct nftl_uci1 { } __attribute__((packed)); struct nftl_uci2 { - __u16 FoldMark; - __u16 FoldMark1; + __u16 FoldMark; + __u16 FoldMark1; __u32 unused; } __attribute__((packed)); @@ -94,8 +94,8 @@ struct NFTLrecord { int head,sect,cyl; __u16 *EUNtable; /* [numvunits]: First EUN for each virtual unit */ __u16 *ReplUnitTable; /* [numEUNs]: ReplUnitNumber for each */ - unsigned int nb_blocks; /* number of physical blocks */ - unsigned int nb_boot_blocks; /* number of blocks used by the bios */ + unsigned int nb_blocks; /* number of physical blocks */ + unsigned int nb_boot_blocks; /* number of blocks used by the bios */ }; #define MAX_NFTLS 16 diff --git a/include/lists.h b/include/lists.h index b42a2fae1ca..804b5cdca70 100644 --- a/include/lists.h +++ b/include/lists.h @@ -3,7 +3,7 @@ #define LIST_START -1 /* Handy Constants that substitute for item positions */ #define LIST_END 0 /* END_OF_LIST means one past current length of list when */ - /* inserting. Otherwise it refers the last item in the list. */ + /* inserting. Otherwise it refers the last item in the list. */ typedef struct { diff --git a/include/malloc.h b/include/malloc.h index 08469bc1bc4..47154b0783f 100644 --- a/include/malloc.h +++ b/include/malloc.h @@ -6,8 +6,8 @@ * VERSION 2.6.6 Sun Mar 5 19:10:03 2000 Doug Lea (dl at gee) Note: There may be an updated version of this malloc obtainable at - ftp://g.oswego.edu/pub/misc/malloc.c - Check before installing! + ftp://g.oswego.edu/pub/misc/malloc.c + Check before installing! * Why use this malloc? @@ -84,7 +84,7 @@ and status information. Minimum allocated size: 4-byte ptrs: 16 bytes (including 4 overhead) - 8-byte ptrs: 24/32 bytes (including, 4/8 overhead) + 8-byte ptrs: 24/32 bytes (including, 4/8 overhead) When a chunk is freed, 12 (for 4byte ptrs) or 20 (for 8 byte ptrs but 4 byte size) or 24 (for 8/8) additional bytes are @@ -96,7 +96,7 @@ pointer to something of the minimum allocatable size. Maximum allocated size: 4-byte size_t: 2^31 - 8 bytes - 8-byte size_t: 2^63 - 16 bytes + 8-byte size_t: 2^63 - 16 bytes It is assumed that (possibly signed) size_t bit values suffice to represent chunk sizes. `Possibly signed' is due to the fact @@ -112,11 +112,11 @@ make the normal worst-case wastage 15 bytes (i.e., up to 15 more bytes will be allocated than were requested in malloc), with two exceptions: - 1. Because requests for zero bytes allocate non-zero space, - the worst case wastage for a request of zero bytes is 24 bytes. - 2. For requests >= mmap_threshold that are serviced via - mmap(), the worst case wastage is 8 bytes plus the remainder - from a system page (the minimal mmap unit); typically 4096 bytes. + 1. Because requests for zero bytes allocate non-zero space, + the worst case wastage for a request of zero bytes is 24 bytes. + 2. For requests >= mmap_threshold that are serviced via + mmap(), the worst case wastage is 8 bytes plus the remainder + from a system page (the minimal mmap unit); typically 4096 bytes. * Limitations @@ -372,8 +372,8 @@ void* memset(void*, int, size_t); void* memcpy(void*, const void*, size_t); #else #ifdef WIN32 -// On Win32 platforms, 'memset()' and 'memcpy()' are already declared in -// 'windows.h' +/* On Win32 platforms, 'memset()' and 'memcpy()' are already declared in */ +/* 'windows.h' */ #else Void_t* memset(); Void_t* memcpy(); @@ -393,14 +393,14 @@ do { \ if(mzsz <= 9*sizeof(mzsz)) { \ INTERNAL_SIZE_T* mz = (INTERNAL_SIZE_T*) (charp); \ if(mzsz >= 5*sizeof(mzsz)) { *mz++ = 0; \ - *mz++ = 0; \ + *mz++ = 0; \ if(mzsz >= 7*sizeof(mzsz)) { *mz++ = 0; \ - *mz++ = 0; \ - if(mzsz >= 9*sizeof(mzsz)) { *mz++ = 0; \ - *mz++ = 0; }}} \ - *mz++ = 0; \ - *mz++ = 0; \ - *mz = 0; \ + *mz++ = 0; \ + if(mzsz >= 9*sizeof(mzsz)) { *mz++ = 0; \ + *mz++ = 0; }}} \ + *mz++ = 0; \ + *mz++ = 0; \ + *mz = 0; \ } else memset((charp), 0, mzsz); \ } while(0) @@ -411,14 +411,14 @@ do { \ INTERNAL_SIZE_T* mcsrc = (INTERNAL_SIZE_T*) (src); \ INTERNAL_SIZE_T* mcdst = (INTERNAL_SIZE_T*) (dest); \ if(mcsz >= 5*sizeof(mcsz)) { *mcdst++ = *mcsrc++; \ - *mcdst++ = *mcsrc++; \ + *mcdst++ = *mcsrc++; \ if(mcsz >= 7*sizeof(mcsz)) { *mcdst++ = *mcsrc++; \ - *mcdst++ = *mcsrc++; \ - if(mcsz >= 9*sizeof(mcsz)) { *mcdst++ = *mcsrc++; \ - *mcdst++ = *mcsrc++; }}} \ - *mcdst++ = *mcsrc++; \ - *mcdst++ = *mcsrc++; \ - *mcdst = *mcsrc ; \ + *mcdst++ = *mcsrc++; \ + if(mcsz >= 9*sizeof(mcsz)) { *mcdst++ = *mcsrc++; \ + *mcdst++ = *mcsrc++; }}} \ + *mcdst++ = *mcsrc++; \ + *mcdst++ = *mcsrc++; \ + *mcdst = *mcsrc ; \ } else memcpy(dest, src, mcsz); \ } while(0) @@ -567,7 +567,6 @@ do { \ #endif - /* This version of malloc supports the standard SVID/XPG mallinfo @@ -631,7 +630,6 @@ struct mallinfo { #define M_MMAP_MAX -4 - #ifndef DEFAULT_TRIM_THRESHOLD #define DEFAULT_TRIM_THRESHOLD (128 * 1024) #endif @@ -695,11 +693,11 @@ struct mallinfo { retain whenever sbrk is called. It is used in two ways internally: * When sbrk is called to extend the top of the arena to satisfy - a new malloc request, this much padding is added to the sbrk - request. + a new malloc request, this much padding is added to the sbrk + request. * When malloc_trim is called automatically from free(), - it is used as the `pad' argument. + it is used as the `pad' argument. In both cases, the actual amount of padding is rounded so that the end of the arena is always a system page boundary. @@ -745,15 +743,15 @@ struct mallinfo { However, it has the disadvantages that: - 1. The space cannot be reclaimed, consolidated, and then - used to service later requests, as happens with normal chunks. - 2. It can lead to more wastage because of mmap page alignment - requirements - 3. It causes malloc performance to be more dependent on host - system memory management support routines which may vary in - implementation quality and may impose arbitrary - limitations. Generally, servicing a request via normal - malloc steps is faster than going through a system's mmap. + 1. The space cannot be reclaimed, consolidated, and then + used to service later requests, as happens with normal chunks. + 2. It can lead to more wastage because of mmap page alignment + requirements + 3. It causes malloc performance to be more dependent on host + system memory management support routines which may vary in + implementation quality and may impose arbitrary + limitations. Generally, servicing a request via normal + malloc steps is faster than going through a system's mmap. All together, these considerations should lead you to use mmap only for relatively large requests. @@ -762,7 +760,6 @@ struct mallinfo { */ - #ifndef DEFAULT_MMAP_MAX #if HAVE_MMAP #define DEFAULT_MMAP_MAX (64) @@ -775,15 +772,15 @@ struct mallinfo { M_MMAP_MAX is the maximum number of requests to simultaneously service using mmap. This parameter exists because: - 1. Some systems have a limited number of internal tables for - use by mmap. - 2. In most systems, overreliance on mmap can degrade overall - performance. - 3. If a program allocates many large regions, it is probably - better off using normal sbrk-based allocation routines that - can reclaim and reallocate normal heap memory. Using a - small value allows transition into this mode after the - first few allocations. + 1. Some systems have a limited number of internal tables for + use by mmap. + 2. In most systems, overreliance on mmap can degrade overall + performance. + 3. If a program allocates many large regions, it is probably + better off using normal sbrk-based allocation routines that + can reclaim and reallocate normal heap memory. Using a + small value allows transition into this mode after the + first few allocations. Setting to 0 disables all use of mmap. If HAVE_MMAP is not set, the default value is 0, and attempts to set it to non-zero values @@ -791,8 +788,6 @@ struct mallinfo { */ - - /* USE_DL_PREFIX will prefix all public routines with the string 'dl'. Useful to quickly avoid procedure declaration conflicts and linker @@ -803,8 +798,6 @@ struct mallinfo { /* #define USE_DL_PREFIX */ - - /* Special defines for linux libc diff --git a/include/mii_phy.h b/include/mii_phy.h index a65bd6654ba..f0d3e628231 100644 --- a/include/mii_phy.h +++ b/include/mii_phy.h @@ -6,4 +6,3 @@ unsigned short mii_phy_read(unsigned short reg); void mii_phy_write(unsigned short reg, unsigned short val); #endif - diff --git a/include/miiphy.h b/include/miiphy.h index f1840ae58f9..5122b098f2d 100644 --- a/include/miiphy.h +++ b/include/miiphy.h @@ -42,7 +42,7 @@ int miiphy_read(unsigned char addr, unsigned char reg, unsigned short * value); int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value); int miiphy_info(unsigned char addr, unsigned int *oui, unsigned char *model, - unsigned char *rev); + unsigned char *rev); int miiphy_reset(unsigned char addr); int miiphy_speed(unsigned char addr); int miiphy_duplex(unsigned char addr); diff --git a/include/mpc106.h b/include/mpc106.h index 3926f8b3635..ab6d57e1990 100644 --- a/include/mpc106.h +++ b/include/mpc106.h @@ -155,4 +155,3 @@ #define MBER_BANK3 0x8 #endif - diff --git a/include/mpc5xx.h b/include/mpc5xx.h index 8541ef6f72e..345fca8de31 100644 --- a/include/mpc5xx.h +++ b/include/mpc5xx.h @@ -23,7 +23,7 @@ /* * File: mpc5xx.h - * + * * Discription: mpc5xx specific definitions * */ @@ -88,7 +88,7 @@ #define SIUMCR_MTSC 0x00000100 /* Memory transfer */ /*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control Register + * TBSCR - Time Base Status and Control Register */ #define TBSCR_REFA ((ushort)0x0080) /* Reference Interrupt Status A */ #define TBSCR_REFB ((ushort)0x0040) /* Reference Interrupt Status B */ @@ -113,13 +113,13 @@ #define PLPRCR_CSR 0x00000080 /* CheskStop Reset value */ /*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register + * SCCR - System Clock and reset Control Register */ #define SCCR_DFNL_MSK 0x00000070 /* DFNL mask */ #define SCCR_DFNH_MSK 0x00000007 /* DFNH mask */ #define SCCR_DFNL_SHIFT 0x0000004 /* DFNL shift value */ #define SCCR_RTSEL 0x00100000 /* RTC circuit input source select */ -#define SCCR_EBDF00 0x00000000 /* Division factor 1. CLKOUT is GCLK2 */ +#define SCCR_EBDF00 0x00000000 /* Division factor 1. CLKOUT is GCLK2 */ #define SCCR_EBDF11 0x00060000 /* reserved */ #define SCCR_TBS 0x02000000 /* Time Base Source */ #define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */ diff --git a/include/net.h b/include/net.h index 2a1d3365e46..b9bf133d9f0 100644 --- a/include/net.h +++ b/include/net.h @@ -64,7 +64,6 @@ typedef ulong IPaddr_t; - /* * The current receive packet handler. Called with a pointer to the * application packet, and a protocol type (PORT_BOOTPC or PORT_TFTP). @@ -184,9 +183,9 @@ typedef struct # define RARPOP_REPLY 4 /* Response to previous request */ /* - * The remaining fields are variable in size, according to - * the sizes above, and are defined as appropriate for - * specific hardware/protocol combinations. + * The remaining fields are variable in size, according to + * the sizes above, and are defined as appropriate for + * specific hardware/protocol combinations. */ uchar ar_data[0]; #if 0 @@ -228,7 +227,6 @@ typedef struct icmphdr { } ICMP_t; - /* * Maximum packet size; used to allocate packet storage. * TFTP packets can be 524 bytes + IP header + ethernet header. diff --git a/include/part.h b/include/part.h index 9aa9f5ab455..35afa28d3e6 100644 --- a/include/part.h +++ b/include/part.h @@ -104,5 +104,3 @@ int test_part_amiga (block_dev_desc_t *dev_desc); #endif #endif /* _PART_H */ - - diff --git a/include/pcmcia/i82365.h b/include/pcmcia/i82365.h index 27ee5837c1c..0b432a80bab 100644 --- a/include/pcmcia/i82365.h +++ b/include/pcmcia/i82365.h @@ -9,7 +9,7 @@ * Software distributed under the License is distributed on an "AS IS" * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See * the License for the specific language governing rights and - * limitations under the License. + * limitations under the License. * * The initial developer of the original code is David A. Hinds * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds diff --git a/include/pcmcia/ss.h b/include/pcmcia/ss.h index d197e42d235..aafae8a547d 100644 --- a/include/pcmcia/ss.h +++ b/include/pcmcia/ss.h @@ -9,7 +9,7 @@ * Software distributed under the License is distributed on an "AS IS" * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See * the License for the specific language governing rights and - * limitations under the License. + * limitations under the License. * * The initial developer of the original code is David A. Hinds * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds diff --git a/include/pcmcia/ti113x.h b/include/pcmcia/ti113x.h index 26c57648e73..5453588d0ce 100644 --- a/include/pcmcia/ti113x.h +++ b/include/pcmcia/ti113x.h @@ -9,7 +9,7 @@ * Software distributed under the License is distributed on an "AS IS" * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See * the License for the specific language governing rights and - * limitations under the License. + * limitations under the License. * * The initial developer of the original code is David A. Hinds * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds @@ -115,7 +115,7 @@ #define TI113X_SCR_CDMA_EN 0x00000008 #define TI113X_SCR_ASYNC_IRQ 0x00000004 #define TI113X_SCR_KEEPCLK 0x00000002 -#define TI113X_SCR_CLKRUN_ENA 0x00000001 +#define TI113X_SCR_CLKRUN_ENA 0x00000001 #define TI122X_SCR_SER_STEP 0xc0000000 #define TI122X_SCR_INTRTIE 0x20000000 diff --git a/include/pcmcia/yenta.h b/include/pcmcia/yenta.h index 525d8ecc82a..5cd58a7da3d 100644 --- a/include/pcmcia/yenta.h +++ b/include/pcmcia/yenta.h @@ -9,7 +9,7 @@ * Software distributed under the License is distributed on an "AS IS" * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See * the License for the specific language governing rights and - * limitations under the License. + * limitations under the License. * * The initial developer of the original code is David A. Hinds * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds diff --git a/include/ppc405.h b/include/ppc405.h index 243a22de53a..a0dbbc3d961 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -25,8 +25,8 @@ /*--------------------------------------------------------------------- */ /* Special Purpose Registers */ /*--------------------------------------------------------------------- */ - #define srr2 0x3de /* save/restore register 2 */ - #define srr3 0x3df /* save/restore register 3 */ + #define srr2 0x3de /* save/restore register 2 */ + #define srr3 0x3df /* save/restore register 3 */ #define dbsr 0x3f0 /* debug status register */ #define dbcr0 0x3f2 /* debug control register 0 */ #define dbcr1 0x3bd /* debug control register 1 */ @@ -44,9 +44,9 @@ #define tsr 0x3d8 /* timer status register */ #define tcr 0x3da /* timer control register */ #define pit 0x3db /* programmable interval timer */ - #define sgr 0x3b9 /* storage guarded reg */ - #define dcwr 0x3ba /* data cache write-thru reg*/ - #define sler 0x3bb /* storage little-endian reg */ + #define sgr 0x3b9 /* storage guarded reg */ + #define dcwr 0x3ba /* data cache write-thru reg*/ + #define sler 0x3bb /* storage little-endian reg */ #define cdbcr 0x3d7 /* cache debug cntrl reg */ #define icdbdr 0x3d3 /* instr cache dbug data reg*/ #define ccr0 0x3b3 /* core configuration register */ @@ -56,8 +56,8 @@ #define su0r 0x3bc /* storage user-defined register 0 */ #define zpr 0x3b0 /* zone protection regsiter */ - #define tbl 0x11c /* time base lower - privileged write */ - #define tbu 0x11d /* time base upper - privileged write */ + #define tbl 0x11c /* time base lower - privileged write */ + #define tbu 0x11d /* time base upper - privileged write */ #define sprg4r 0x104 /* Special purpose general 4 - read only */ #define sprg5r 0x105 /* Special purpose general 5 - read only */ @@ -448,30 +448,30 @@ *------------------------------------------------------------------------------- */ #define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) #define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) #define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) + PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) #define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \ - PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) #define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) + PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) #define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ - PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) #define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) + PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) #define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) /* * PLL Voltage Controlled Oscillator (VCO) definitions @@ -672,4 +672,3 @@ typedef struct line aligned data. */ #endif /* __PPC405_H__ */ - diff --git a/include/ppc440.h b/include/ppc440.h index 32c5b52d3e5..76930a5df7f 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -551,4 +551,3 @@ typedef struct line aligned data. */ #endif /* __PPC440_H__ */ - diff --git a/include/ppc4xx.h b/include/ppc4xx.h index 5750902b50f..67759c7336a 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -30,4 +30,3 @@ #endif #endif /* __PPC4XX_H__ */ - diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl index f99d7b2fb98..0e0bde5b99d 100644 --- a/include/ppc_asm.tmpl +++ b/include/ppc_asm.tmpl @@ -248,31 +248,31 @@ * code except that it uses SRR2 and SRR3 instead of SRR0 and SRR1. */ #define CRITICAL_EXCEPTION_PROLOG \ - mtspr SPRG0,r20; \ - mtspr SPRG1,r21; \ - mfcr r20; \ - subi r21,r1,INT_FRAME_SIZE+STACK_UNDERHEAD; /* alloc exc. frame */\ - stw r20,_CCR(r21); /* save registers */ \ - stw r22,GPR22(r21); \ - stw r23,GPR23(r21); \ - mfspr r20,SPRG0; \ - stw r20,GPR20(r21); \ - mfspr r22,SPRG1; \ - stw r22,GPR21(r21); \ - mflr r20; \ - stw r20,_LINK(r21); \ - mfctr r22; \ - stw r22,_CTR(r21); \ - mfspr r20,XER; \ - stw r20,_XER(r21); \ - mfspr r22,990; /* SRR2 */ \ - mfspr r23,991; /* SRR3 */ \ - stw r0,GPR0(r21); \ - stw r1,GPR1(r21); \ - stw r2,GPR2(r21); \ - stw r1,0(r21); \ - mr r1,r21; /* set new kernel sp */ \ - SAVE_4GPRS(3, r21); + mtspr SPRG0,r20; \ + mtspr SPRG1,r21; \ + mfcr r20; \ + subi r21,r1,INT_FRAME_SIZE+STACK_UNDERHEAD; /* alloc exc. frame */\ + stw r20,_CCR(r21); /* save registers */ \ + stw r22,GPR22(r21); \ + stw r23,GPR23(r21); \ + mfspr r20,SPRG0; \ + stw r20,GPR20(r21); \ + mfspr r22,SPRG1; \ + stw r22,GPR21(r21); \ + mflr r20; \ + stw r20,_LINK(r21); \ + mfctr r22; \ + stw r22,_CTR(r21); \ + mfspr r20,XER; \ + stw r20,_XER(r21); \ + mfspr r22,990; /* SRR2 */ \ + mfspr r23,991; /* SRR3 */ \ + stw r0,GPR0(r21); \ + stw r1,GPR1(r21); \ + stw r2,GPR2(r21); \ + stw r1,0(r21); \ + mr r1,r21; /* set new kernel sp */ \ + SAVE_4GPRS(3, r21); /* * Note: code which follows this uses cr0.eq (set if from kernel), * r21, r22 (SRR2), and r23 (SRR3). @@ -301,17 +301,17 @@ label: \ #define CRIT_EXCEPTION(n, label, hdlr) \ - . = n; \ + . = n; \ label: \ - CRITICAL_EXCEPTION_PROLOG; \ - lwz r3,GOT(transfer_to_handler); \ - mtlr r3; \ - addi r3,r1,STACK_FRAME_OVERHEAD; \ - li r20,MSR_KERNEL; \ - rlwimi r20,r23,0,25,25; \ - blrl ; \ + CRITICAL_EXCEPTION_PROLOG; \ + lwz r3,GOT(transfer_to_handler); \ + mtlr r3; \ + addi r3,r1,STACK_FRAME_OVERHEAD; \ + li r20,MSR_KERNEL; \ + rlwimi r20,r23,0,25,25; \ + blrl ; \ .L_ ## label : \ - .long hdlr - _start + EXC_OFF_SYS_RESET; \ - .long crit_return - _start + EXC_OFF_SYS_RESET + .long hdlr - _start + EXC_OFF_SYS_RESET; \ + .long crit_return - _start + EXC_OFF_SYS_RESET #endif /* __PPC_ASM_TMPL__ */ diff --git a/include/s3c2400.h b/include/s3c2400.h index 6269117b0f1..bc1f1e94bff 100644 --- a/include/s3c2400.h +++ b/include/s3c2400.h @@ -465,7 +465,6 @@ static inline S3C2400_MMC * const S3C2400_GetBase_MMC(void) #define rMMDAT (*(volatile unsigned *)0x15a0003C) - /* ISR */ #define pISR_RESET (*(unsigned *)(_ISR_STARTADDRESS+0x0)) #define pISR_UNDEF (*(unsigned *)(_ISR_STARTADDRESS+0x4)) diff --git a/include/s3c24x0.h b/include/s3c24x0.h index 78a79811f5b..71f35a51742 100644 --- a/include/s3c24x0.h +++ b/include/s3c24x0.h @@ -371,7 +371,7 @@ typedef struct { #ifdef CONFIG_S3C2400 S3C24X0_REG32 PACON; S3C24X0_REG32 PADAT; - + S3C24X0_REG32 PBCON; S3C24X0_REG32 PBDAT; S3C24X0_REG32 PBUP; diff --git a/include/scsi.h b/include/scsi.h index 8929318925c..2be4d4014af 100644 --- a/include/scsi.h +++ b/include/scsi.h @@ -187,7 +187,6 @@ void scsi_low_level_init(int busdevfunc); void scsi_init(void); - #define SCSI_IDENTIFY 0xC0 /* not used */ /* Hardware errors */ @@ -199,7 +198,6 @@ void scsi_init(void); #define SCSI_INT_STATE 0x00010000 /* unknown Interrupt number is stored in 16 LSB */ - #ifndef TRUE #define TRUE 1 #endif @@ -207,9 +205,4 @@ void scsi_init(void); #define FALSE 0 #endif - - - - #endif /* _SCSI_H */ - diff --git a/include/sed13806.h b/include/sed13806.h index 70e8e87449c..216e7880af3 100644 --- a/include/sed13806.h +++ b/include/sed13806.h @@ -35,7 +35,7 @@ #define DEFAULT_VIDEO_MEMORY_SIZE 0x140000 /* Video Memory Size */ #define HWCURSORSIZE 1024 /* Size of memory reserved - for HW cursor*/ + for HW cursor*/ /* Offset of chipset registers */ #define BLT_CTRL0 (0x0100) @@ -87,7 +87,6 @@ typedef struct } S1D_REGS; - /* Board specific functions */ unsigned int board_video_init (void); void board_validate_screen (unsigned int base); diff --git a/include/smiLynxEM.h b/include/smiLynxEM.h index cdd2f2417d9..017964b3e7b 100644 --- a/include/smiLynxEM.h +++ b/include/smiLynxEM.h @@ -44,9 +44,9 @@ */ #define VIDEO_MODES 7 #define DUAL_800_600 0 /* SMI710:VGA1:75Hz (pitch=1600) */ - /* VGA2:60/120Hz (pitch=1600) */ - /* SMI810:VGA1:75Hz (pitch=1600) */ - /* VGA2:75Hz (pitch=1600) */ + /* VGA2:60/120Hz (pitch=1600) */ + /* SMI810:VGA1:75Hz (pitch=1600) */ + /* VGA2:75Hz (pitch=1600) */ #define DUAL_1024_768 1 /* VGA1:75Hz VGA2:73Hz (pitch=2048) */ #define SINGLE_800_600 2 /* VGA1:75Hz (pitch=800) */ #define SINGLE_1024_768 3 /* VGA1:75Hz (pitch=1024) */ diff --git a/include/spartan2.h b/include/spartan2.h index a04aacae414..9725d4b3e7e 100644 --- a/include/spartan2.h +++ b/include/spartan2.h @@ -89,4 +89,3 @@ typedef struct { { Xilinx_Spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie } #endif /* _SPARTAN2_H_ */ - diff --git a/include/spd_sdram.h b/include/spd_sdram.h index feb1bbd4c50..4e754ec9e33 100644 --- a/include/spd_sdram.h +++ b/include/spd_sdram.h @@ -3,4 +3,4 @@ long int spd_sdram(int(read_spd)(uint addr)); -#endif +#endif diff --git a/include/status_led.h b/include/status_led.h index e8ba9fd42d4..47f7c355afe 100644 --- a/include/status_led.h +++ b/include/status_led.h @@ -258,8 +258,8 @@ void status_led_set (int led, int state); /***** CMI ********************************************************/ #elif defined(CONFIG_CMI) -# define STATUS_LED_DIR im_mios.mios_mpiosm32ddr -# define STATUS_LED_DAT im_mios.mios_mpiosm32dr +# define STATUS_LED_DIR im_mios.mios_mpiosm32ddr +# define STATUS_LED_DAT im_mios.mios_mpiosm32dr # define STATUS_LED_BIT 0x2000 /* Select one of the 16 possible*/ /* MIOS outputs */ diff --git a/include/sym53c8xx.h b/include/sym53c8xx.h index 821e1f85a4d..0734fe4f0c0 100644 --- a/include/sym53c8xx.h +++ b/include/sym53c8xx.h @@ -172,7 +172,7 @@ #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */ #define STD 0x04 /* cmd: start dma mode */ #define IRQD 0x02 /* mod: irq disable */ - #define NOCOM 0x01 /* cmd: protect sfbr while reselect */ + #define NOCOM 0x01 /* cmd: protect sfbr while reselect */ /* bits 0-1 rsvd for C1010 */ #define ADDER 0x3c @@ -231,8 +231,6 @@ #define SBDL 0x58 /* Lowlevel: data from scsi data */ - - /*----------------------------------------------------------- ** ** Utility macros for the script. @@ -356,8 +354,6 @@ #define SCR_ATN 0x00000008 - - /*----------------------------------------------------------- ** ** Memory to memory move @@ -408,13 +404,13 @@ #define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul)) /* + ((ofs) & 0x80)) */ #define SCR_SFBR_REG(reg,op,data) \ - (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) + (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) #define SCR_REG_SFBR(reg,op,data) \ - (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) + (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) #define SCR_REG_REG(reg,op,data) \ - (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) + (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) #define SCR_LOAD 0x00000000 @@ -455,7 +451,7 @@ SCR_REG_REG(reg,SCR_LOAD,data) #define SCR_LOAD_SFBR(data) \ - (SCR_REG_SFBR (gpreg, SCR_LOAD, data)) + (SCR_REG_SFBR (gpreg, SCR_LOAD, data)) /*----------------------------------------------------------- ** @@ -480,10 +476,10 @@ #define SCR_DSA_REL2 0x10000000 #define SCR_LOAD_R(reg, how, n) \ - (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) + (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) #define SCR_STORE_R(reg, how, n) \ - (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) + (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) #define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n) #define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n) @@ -554,7 +550,6 @@ #define CARRYSET (0x00200000) - #define SIR_COMPLETE 0x10000000 /* script errors */ #define SIR_SEL_ATN_NO_MSG_OUT 0x00000001 diff --git a/include/usb.h b/include/usb.h index c3cc8903ad5..edb61201a75 100644 --- a/include/usb.h +++ b/include/usb.h @@ -59,7 +59,6 @@ struct devrequest { } __attribute__ ((packed)); - /* All standard descriptors have these 2 fields in common */ struct usb_descriptor_header { unsigned char bLength; @@ -141,7 +140,7 @@ struct usb_device { int maxpacketsize; /* Maximum packet size; encoded as 0,1,2,3 = 8,16,32,64 */ unsigned int toggle[2]; /* one bit for each endpoint ([0] = IN, [1] = OUT) */ unsigned int halted[2]; /* endpoint halts; one bit per endpoint # & direction; */ - /* [0] = IN, [1] = OUT */ + /* [0] = IN, [1] = OUT */ int epmaxpacketin[16]; /* INput endpoint specific maximums */ int epmaxpacketout[16]; /* OUTput endpoint specific maximums */ diff --git a/include/usb_defs.h b/include/usb_defs.h index 00a31e905af..33d1e46f2d8 100644 --- a/include/usb_defs.h +++ b/include/usb_defs.h @@ -189,7 +189,6 @@ #define USB_ST_NOT_PROC 0x80000000L /* Not yet processed */ - /************************************************************************* * Hub defines */ diff --git a/include/version.h b/include/version.h index 3f228c8b81d..fee1b692b2f 100644 --- a/include/version.h +++ b/include/version.h @@ -24,6 +24,6 @@ #ifndef __VERSION_H__ #define __VERSION_H__ -#define U_BOOT_VERSION "U-Boot 0.4.0" +#define U_BOOT_VERSION "U-Boot 0.4.1" #endif /* __VERSION_H__ */ diff --git a/include/video_ad7176.h b/include/video_ad7176.h index 88007ce8d92..5b8b0103120 100644 --- a/include/video_ad7176.h +++ b/include/video_ad7176.h @@ -49,56 +49,56 @@ static unsigned char video_encoder_data[] = { #ifdef VIDEO_MODE_NTSC - 0x04, /* Mode Register 0 */ + 0x04, /* Mode Register 0 */ #ifdef VIDEO_DEBUG_COLORBARS 0x82, #else - 0x02, /* Mode Register 1 */ + 0x02, /* Mode Register 1 */ #endif - 0x16, /* Subcarrier Freq 0 */ - 0x7c, /* Subcarrier Freq 1 */ - 0xf0, /* Subcarrier Freq 2 */ - 0x21, /* Subcarrier Freq 3 */ - 0x00, /* Subcarrier phase */ - 0x02, /* Timing Register 0 */ - 0x00, /* Extended Captioning 0 */ - 0x00, /* Extended Captioning 1 */ - 0x00, /* Closed Captioning 0 */ - 0x00, /* Closed Captioning 1 */ - 0x00, /* Timing Register 1 */ - 0x08, /* Mode Register 2 */ - 0x00, /* Pedestal Register 0 */ - 0x00, /* Pedestal Register 1 */ - 0x00, /* Pedestal Register 2 */ - 0x00, /* Pedestal Register 3 */ - 0x00 /* Mode Register 3 */ + 0x16, /* Subcarrier Freq 0 */ + 0x7c, /* Subcarrier Freq 1 */ + 0xf0, /* Subcarrier Freq 2 */ + 0x21, /* Subcarrier Freq 3 */ + 0x00, /* Subcarrier phase */ + 0x02, /* Timing Register 0 */ + 0x00, /* Extended Captioning 0 */ + 0x00, /* Extended Captioning 1 */ + 0x00, /* Closed Captioning 0 */ + 0x00, /* Closed Captioning 1 */ + 0x00, /* Timing Register 1 */ + 0x08, /* Mode Register 2 */ + 0x00, /* Pedestal Register 0 */ + 0x00, /* Pedestal Register 1 */ + 0x00, /* Pedestal Register 2 */ + 0x00, /* Pedestal Register 3 */ + 0x00 /* Mode Register 3 */ #endif /* VIDEO_MODE_NTSC */ #ifdef VIDEO_MODE_PAL - 0x05, /* Mode Register 0 */ + 0x05, /* Mode Register 0 */ #ifdef VIDEO_DEBUG_COLORBARS 0x82, #else - 0x02, /* Mode Register 1 (2) */ + 0x02, /* Mode Register 1 (2) */ #endif - 0xcb, /* Subcarrier Freq 0 */ - 0x8a, /* Subcarrier Freq 1 */ - 0x09, /* Subcarrier Freq 2 */ - 0x2a, /* Subcarrier Freq 3 */ - 0x00, /* Subcarrier phase */ - 0x0a, /* Timing Register 0 (a) */ - 0x00, /* Extended Captioning 0 */ - 0x00, /* Extended Captioning 1 */ - 0x00, /* Closed Captioning 0 */ - 0x00, /* Closed Captioning 1 */ - 0x00, /* Timing Register 1 */ - 0x08, /* Mode Register 2 (8) */ - 0x00, /* Pedestal Register 0 */ - 0x00, /* Pedestal Register 1 */ - 0x00, /* Pedestal Register 2 */ - 0x00, /* Pedestal Register 3 */ - 0x00 /* Mode Register 3 */ + 0xcb, /* Subcarrier Freq 0 */ + 0x8a, /* Subcarrier Freq 1 */ + 0x09, /* Subcarrier Freq 2 */ + 0x2a, /* Subcarrier Freq 3 */ + 0x00, /* Subcarrier phase */ + 0x0a, /* Timing Register 0 (a) */ + 0x00, /* Extended Captioning 0 */ + 0x00, /* Extended Captioning 1 */ + 0x00, /* Closed Captioning 0 */ + 0x00, /* Closed Captioning 1 */ + 0x00, /* Timing Register 1 */ + 0x08, /* Mode Register 2 (8) */ + 0x00, /* Pedestal Register 0 */ + 0x00, /* Pedestal Register 1 */ + 0x00, /* Pedestal Register 2 */ + 0x00, /* Pedestal Register 3 */ + 0x00 /* Mode Register 3 */ #endif /* VIDEO_MODE_PAL */ } ; diff --git a/include/video_ad7177.h b/include/video_ad7177.h index 68a6b8df648..3f35f335d53 100644 --- a/include/video_ad7177.h +++ b/include/video_ad7177.h @@ -52,95 +52,95 @@ static unsigned char video_encoder_data[] = { #ifdef VIDEO_MODE_NTSC - 0x04, /* Mode Register 0 */ + 0x04, /* Mode Register 0 */ #ifdef VIDEO_DEBUG_COLORBARS 0xc2, #else - 0x42, /* Mode Register 1 */ + 0x42, /* Mode Register 1 */ #endif - 0x16, /* Subcarrier Freq 0 */ - 0x7c, /* Subcarrier Freq 1 */ - 0xf0, /* Subcarrier Freq 2 */ - 0x21, /* Subcarrier Freq 3 */ - 0x00, /* Subcarrier phase */ - 0x02, /* Timing Register 0 */ - 0x00, /* Extended Captioning 0 */ - 0x00, /* Extended Captioning 1 */ - 0x00, /* Closed Captioning 0 */ - 0x00, /* Closed Captioning 1 */ - 0x00, /* Timing Register 1 */ - 0x08, /* Mode Register 2 */ - 0x00, /* Pedestal Register 0 */ - 0x00, /* Pedestal Register 1 */ - 0x00, /* Pedestal Register 2 */ - 0x00, /* Pedestal Register 3 */ - 0x08 /* Mode Register 3 */ + 0x16, /* Subcarrier Freq 0 */ + 0x7c, /* Subcarrier Freq 1 */ + 0xf0, /* Subcarrier Freq 2 */ + 0x21, /* Subcarrier Freq 3 */ + 0x00, /* Subcarrier phase */ + 0x02, /* Timing Register 0 */ + 0x00, /* Extended Captioning 0 */ + 0x00, /* Extended Captioning 1 */ + 0x00, /* Closed Captioning 0 */ + 0x00, /* Closed Captioning 1 */ + 0x00, /* Timing Register 1 */ + 0x08, /* Mode Register 2 */ + 0x00, /* Pedestal Register 0 */ + 0x00, /* Pedestal Register 1 */ + 0x00, /* Pedestal Register 2 */ + 0x00, /* Pedestal Register 3 */ + 0x08 /* Mode Register 3 */ #endif #ifdef VIDEO_MODE_PAL #ifdef VIDEO_MODE_RGB_OUT - 0x69, /* Mode Register 0 */ + 0x69, /* Mode Register 0 */ #ifdef VIDEO_DEBUG_COLORBARS 0xc0, /* Mode Register 1 (c0) */ #else 0x40, /* Mode Register 1 (c0) */ #endif - 0xcb, /* Subcarrier Freq 0 */ - 0x8a, /* Subcarrier Freq 1 */ - 0x09, /* Subcarrier Freq 2 */ - 0x2a, /* Subcarrier Freq 3 */ - 0x00, /* Subcarrier phase */ - 0x02, /* Timing Register 0 */ - 0x00, /* Extended Captioning 0 */ - 0x00, /* Extended Captioning 1 */ - 0x00, /* Closed Captioning 0 */ - 0x00, /* Closed Captioning 1 */ - 0x00, /* Timing Register 1 */ - 0x28, /* Mode Register 2 */ - 0x00, /* Pedestal Register 0 */ - 0x00, /* Pedestal Register 1 */ - 0x00, /* Pedestal Register 2 */ - 0x00, /* Pedestal Register 3 */ - 0x08 /* Mode Register 3 */ + 0xcb, /* Subcarrier Freq 0 */ + 0x8a, /* Subcarrier Freq 1 */ + 0x09, /* Subcarrier Freq 2 */ + 0x2a, /* Subcarrier Freq 3 */ + 0x00, /* Subcarrier phase */ + 0x02, /* Timing Register 0 */ + 0x00, /* Extended Captioning 0 */ + 0x00, /* Extended Captioning 1 */ + 0x00, /* Closed Captioning 0 */ + 0x00, /* Closed Captioning 1 */ + 0x00, /* Timing Register 1 */ + 0x28, /* Mode Register 2 */ + 0x00, /* Pedestal Register 0 */ + 0x00, /* Pedestal Register 1 */ + 0x00, /* Pedestal Register 2 */ + 0x00, /* Pedestal Register 3 */ + 0x08 /* Mode Register 3 */ #else - 0x09, /* Mode Register 0 (was 01) */ + 0x09, /* Mode Register 0 (was 01) */ #ifdef VIDEO_DEBUG_COLORBARS 0xd8, /* */ #else - 0x59, /* Mode Register 1 (was 58) */ + 0x59, /* Mode Register 1 (was 58) */ #endif - 0xcb, /* Subcarrier Freq 0 */ - 0x8a, /* Subcarrier Freq 1 */ - 0x09, /* Subcarrier Freq 2 */ - 0x2a, /* Subcarrier Freq 3 */ - 0x00, /* Subcarrier phase */ - 0x02, /* Timing Register 0 (was a) */ - 0x00, /* Extended Captioning 0 */ - 0x00, /* Extended Captioning 1 */ - 0x00, /* Closed Captioning 0 */ - 0x00, /* Closed Captioning 1 */ - 0x00, /* Timing Register 1 */ + 0xcb, /* Subcarrier Freq 0 */ + 0x8a, /* Subcarrier Freq 1 */ + 0x09, /* Subcarrier Freq 2 */ + 0x2a, /* Subcarrier Freq 3 */ + 0x00, /* Subcarrier phase */ + 0x02, /* Timing Register 0 (was a) */ + 0x00, /* Extended Captioning 0 */ + 0x00, /* Extended Captioning 1 */ + 0x00, /* Closed Captioning 0 */ + 0x00, /* Closed Captioning 1 */ + 0x00, /* Timing Register 1 */ #ifdef VIDEO_DEBUG_LOWPOWER #ifdef VIDEO_DEBUG_DISABLE_COLORS - 0x98, /* Mode Register 2 */ + 0x98, /* Mode Register 2 */ #else - 0x88, /* Mode Register 2 */ + 0x88, /* Mode Register 2 */ #endif #else #ifdef VIDEO_DEBUG_DISABLE_COLORS - 0x18, /* Mode Register 2 */ + 0x18, /* Mode Register 2 */ #else - 0x08, /* Mode Register 2 */ + 0x08, /* Mode Register 2 */ #endif #endif - 0x00, /* Pedestal Register 0 */ - 0x00, /* Pedestal Register 1 */ - 0x00, /* Pedestal Register 2 */ - 0x00, /* Pedestal Register 3 */ - 0x08 /* Mode Register 3 */ + 0x00, /* Pedestal Register 0 */ + 0x00, /* Pedestal Register 1 */ + 0x00, /* Pedestal Register 2 */ + 0x00, /* Pedestal Register 3 */ + 0x08 /* Mode Register 3 */ #endif #endif } ; diff --git a/include/video_fb.h b/include/video_fb.h index a9e427593e1..9825f0c4c2e 100644 --- a/include/video_fb.h +++ b/include/video_fb.h @@ -1,4 +1,4 @@ - /* + /* * (C) Copyright 1997-2002 ELTEC Elektronik AG * Frank Gottschling <fgottschling@eltec.de> * diff --git a/include/watchdog.h b/include/watchdog.h index dc26e6ad06d..b9ae916a1d2 100644 --- a/include/watchdog.h +++ b/include/watchdog.h @@ -98,4 +98,3 @@ reset_8260_watchdog(volatile immap_t *immr) #endif /* CONFIG_MPC8260 && !__ASSEMBLY__ */ #endif /* _WATCHDOG_H_ */ - diff --git a/include/zlib.h b/include/zlib.h index 6958ab8e77d..e441494d0d7 100644 --- a/include/zlib.h +++ b/include/zlib.h @@ -93,7 +93,7 @@ #endif /* The memory requirements for deflate are (in bytes): - 1 << (windowBits+2) + 1 << (memLevel+9) + 1 << (windowBits+2) + 1 << (memLevel+9) that is: 128K for windowBits=15 + 128K for memLevel = 8 (default values) plus a few kilobytes for small objects. For example, if you want to reduce the default memory requirements from 256K to 128K, compile with @@ -105,7 +105,7 @@ for small objects. */ - /* Type declarations */ + /* Type declarations */ #ifndef OF /* function prototypes */ # ifdef STDC @@ -214,7 +214,7 @@ typedef struct z_stream_s { a single step). */ - /* constants */ + /* constants */ #define Z_NO_FLUSH 0 #define Z_PARTIAL_FLUSH 1 @@ -255,7 +255,7 @@ extern char *zlib_version; not compatible with the zlib.h header file used by the application. */ - /* basic functions */ + /* basic functions */ extern int inflateInit OF((z_stream *strm)); /* @@ -333,10 +333,10 @@ extern int inflateEnd OF((z_stream *strm)); static string (which must not be deallocated). */ - /* advanced functions */ + /* advanced functions */ extern int inflateInit2 OF((z_stream *strm, - int windowBits)); + int windowBits)); /* This is another version of inflateInit with more compression options. The fields next_out, zalloc and zfree must be initialized before by the caller. @@ -402,7 +402,7 @@ extern int inflateIncomp OF((z_stream *strm)); containing the data at next_in (except that the data is not output). */ - /* checksum functions */ + /* checksum functions */ /* This function is not related to compression but is exported |