diff options
| author | Shivamurthy Shastri <sshivamurthy@micron.com> | 2020-07-07 22:04:11 +0200 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2020-07-20 22:28:33 +0530 |
| commit | 720fcb27e0be500a718fffd9c1910f8ed94e7745 (patch) | |
| tree | 318d2f24a27faf9100ec8968c7adef3472b44563 /include | |
| parent | 5cf049c00ac0c5c9542ce968d9f79451ce870b2c (diff) | |
mtd: spinand: micron: identify SPI NAND device with Continuous Read mode
Add SPINAND_HAS_CR_FEAT_BIT flag to identify the SPI NAND device with
the Continuous Read mode.
Some of the Micron SPI NAND devices have the "Continuous Read" feature
enabled by default, which does not fit the subsystem needs.
In this mode, the READ CACHE command doesn't require the starting column
address. The device always output the data starting from the first
column of the cache register, and once the end of the cache register
reached, the data output continues through the next page. With the
continuous read mode, it is possible to read out the entire block using
a single READ command, and once the end of the block reached, the output
pins become High-Z state. However, during this mode the read command
doesn't output the OOB area.
Hence, we disable the feature at probe time.
Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/mtd/spinand.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 83eafb184e6..88bacde91e5 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -246,6 +246,7 @@ struct spinand_ecc_info { }; #define SPINAND_HAS_QE_BIT BIT(0) +#define SPINAND_HAS_CR_FEAT_BIT BIT(1) /** * struct spinand_info - Structure used to describe SPI NAND chips |