Merge branch 'master' of git://git.denx.de/u-boot-arm into master

Conflicts: arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg Signed-off-by: Stefano Babic <sbabic@denx.de>
author: Stefano Babic <sbabic@denx.de> 2014-04-04 11:35:30 +0200
committer: Stefano Babic <sbabic@denx.de> 2014-04-04 11:35:30 +0200
commit: 1cad23c5f471d695bed1e3907e30caee3c2a3056 (patch)
tree: 34e035df5db9b327aeae36eff9d0645a915e3177 /include
parent: 5dd73bc0a40a4b318195eab871a1f535aad6b43b (diff)
parent: 00b132bf34c5be86a108ac7fe8231ad9e97f6de4 (diff)
178 files changed, 3530 insertions, 1745 deletions
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
index 0de0beaa8bd..707400e8479 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -21,6 +21,8 @@
  */
 
 #ifndef __ASSEMBLY__
+#include <linux/list.h>
+
 typedef struct global_data {
 	bd_t *bd;
 	unsigned long flags;
@@ -61,6 +63,12 @@ typedef struct global_data {
 	unsigned long start_addr_sp;	/* start_addr_stackpointer */
 	unsigned long reloc_off;
 	struct global_data *new_gd;	/* relocated global data */
+
+#ifdef CONFIG_DM
+	struct device	*dm_root;	/* Root instance for Driver Model */
+	struct list_head uclass_root;	/* Head of core tree */
+#endif
+
 	const void *fdt_blob;	/* Our device tree, NULL if none */
 	void *new_fdt;		/* Relocated FDT */
 	unsigned long fdt_size;	/* Space reserved for relocated FDT */
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index f54103980c3..e325df40d93 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -78,4 +78,108 @@ int gpio_get_value(unsigned gpio);
  * @return 0 if ok, -1 on error
  */
 int gpio_set_value(unsigned gpio, int value);
+
+/* State of a GPIO, as reported by get_state() */
+enum {
+	GPIOF_INPUT = 0,
+	GPIOF_OUTPUT,
+	GPIOF_UNKNOWN,
+};
+
+struct device;
+
+/**
+ * struct struct dm_gpio_ops - Driver model GPIO operations
+ *
+ * Refer to functions above for description. These function largely copy
+ * the old API.
+ *
+ * This is trying to be close to Linux GPIO API. Once the U-Boot uses the
+ * new DM GPIO API, this should be really easy to flip over to the Linux
+ * GPIO API-alike interface.
+ *
+ * Akso it would be useful to standardise additional functions like
+ * pullup, slew rate and drive strength.
+ *
+ * gpio_request)( and gpio_free() are optional - if NULL then they will
+ * not be called.
+ *
+ * Note that @offset is the offset from the base GPIO of the device. So
+ * offset 0 is the device's first GPIO and offset o-1 is the last GPIO,
+ * where o is the number of GPIO lines controlled by the device. A device
+ * is typically used to control a single bank of GPIOs. Within complex
+ * SoCs there may be many banks and therefore many devices all referring
+ * to the different IO addresses within the SoC.
+ *
+ * The uclass combines all GPIO devices togther to provide a consistent
+ * numbering from 0 to n-1, where n is the number of GPIOs in total across
+ * all devices. Be careful not to confuse offset with gpio in the parameters.
+ */
+struct dm_gpio_ops {
+	int (*request)(struct device *dev, unsigned offset, const char *label);
+	int (*free)(struct device *dev, unsigned offset);
+	int (*direction_input)(struct device *dev, unsigned offset);
+	int (*direction_output)(struct device *dev, unsigned offset,
+				int value);
+	int (*get_value)(struct device *dev, unsigned offset);
+	int (*set_value)(struct device *dev, unsigned offset, int value);
+	int (*get_function)(struct device *dev, unsigned offset);
+	int (*get_state)(struct device *dev, unsigned offset, char *state,
+			 int maxlen);
+};
+
+/**
+ * struct gpio_dev_priv - information about a device used by the uclass
+ *
+ * The uclass combines all active GPIO devices into a unified numbering
+ * scheme. To do this it maintains some private information aobut each
+ * device.
+ *
+ * To implement driver model support in your GPIO driver, add a probe
+ * handler, and set @gpio_count and @bank_name correctly in that handler.
+ * This tells the uclass the name of the GPIO bank and the number of GPIOs
+ * it contains.
+ *
+ * @bank_name: Name of the GPIO device (e.g 'a' means GPIOs will be called
+ * 'A0', 'A1', etc.
+ * @gpio_count: Number of GPIOs in this device
+ * @gpio_base: Base GPIO number for this device. For the first active device
+ * this will be 0; the numbering for others will follow sequentially so that
+ * @gpio_base for device 1 will equal the number of GPIOs in device 0.
+ */
+struct gpio_dev_priv {
+	const char *bank_name;
+	unsigned gpio_count;
+	unsigned gpio_base;
+};
+
+/* Access the GPIO operations for a device */
+#define gpio_get_ops(dev)	((struct dm_gpio_ops *)(dev)->driver->ops)
+
+/**
+ * gpio_get_bank_info - Return information about a GPIO bank/device
+ *
+ * This looks up a device and returns both its GPIO base name and the number
+ * of GPIOs it controls.
+ *
+ * @dev: Device to look up
+ * @offset_count: Returns number of GPIOs within this bank
+ * @return bank name of this device
+ */
+const char *gpio_get_bank_info(struct device *dev, int *offset_count);
+
+/**
+ * gpio_lookup_name - Look up a GPIO name and return its details
+ *
+ * This is used to convert a named GPIO into a device, offset and GPIO
+ * number.
+ *
+ * @name: GPIO name to look up
+ * @devp: Returns pointer to device which contains this GPIO
+ * @offsetp: Returns the offset number within this device
+ * @gpiop: Returns the absolute GPIO number, numbered from 0
+ */
+int gpio_lookup_name(const char *name, struct device **devp,
+		     unsigned int *offsetp, unsigned int *gpiop);
+
 #endif	/* _ASM_GENERIC_GPIO_H_ */
diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h
index 43872010c7f..e78196797bd 100644
--- a/include/asm-generic/u-boot.h
+++ b/include/asm-generic/u-boot.h
@@ -37,7 +37,7 @@ typedef struct bd_info {
 	unsigned long	bi_dsp_freq; /* dsp core frequency */
 	unsigned long	bi_ddr_freq; /* ddr frequency */
 #endif
-#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \
+#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_MPC8260) \
 	|| defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
 	unsigned long	bi_immr_base;	/* base of IMMR register */
 #endif
diff --git a/include/command.h b/include/command.h
index f782779d8bd..d3f700fc3c8 100644
--- a/include/command.h
+++ b/include/command.h
@@ -64,6 +64,15 @@ extern int var_complete(int argc, char * const argv[], char last_char, int maxv,
 extern int cmd_auto_complete(const char *const prompt, char *buf, int *np, int *colp);
 #endif
 
+/**
+ * cmd_process_error() - report and process a possible error
+ *
+ * @cmdtp: Command which caused the error
+ * @err: Error code (0 if none, -ve for error, like -EIO)
+ * @return 0 if there is not error, 1 (CMD_RET_FAILURE) if an error is found
+ */
+int cmd_process_error(cmd_tbl_t *cmdtp, int err);
+
 /*
  * Monitor Command
  *
diff --git a/include/common.h b/include/common.h
index 96a45a6cf70..5c9bd08f45f 100644
--- a/include/common.h
+++ b/include/common.h
@@ -52,16 +52,13 @@ typedef volatile unsigned char	vu_char;
 #include <mpc5xxx.h>
 #elif defined(CONFIG_MPC512X)
 #include <asm/immap_512x.h>
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
 #if   defined(CONFIG_MPC8247) \
    || defined(CONFIG_MPC8248) \
    || defined(CONFIG_MPC8271) \
    || defined(CONFIG_MPC8272)
 #define CONFIG_MPC8272_FAMILY	1
 #endif
-#if defined(CONFIG_MPC8272_FAMILY)
-#define CONFIG_MPC8260	1
-#endif
 #include <asm/immap_8260.h>
 #endif
 #ifdef CONFIG_MPC86xx
@@ -96,6 +93,10 @@ typedef volatile unsigned char	vu_char;
 #include <flash.h>
 #include <image.h>
 
+#ifdef __LP64__
+#define CONFIG_SYS_SUPPORT_64BIT_DATA
+#endif
+
 #ifdef DEBUG
 #define _DEBUG	1
 #else
@@ -313,6 +314,7 @@ static inline int print_cpuinfo(void)
 }
 #endif
 int update_flash_size(int flash_size);
+int arch_early_init_r(void);
 
 /**
  * Show the DRAM size in a board-specific way
@@ -359,6 +361,11 @@ int do_ext2load(cmd_tbl_t *, int, int, char * const []);
 int	env_init     (void);
 void	env_relocate (void);
 int	envmatch     (uchar *, int);
+
+/* Avoid unfortunate conflict with libc's getenv() */
+#ifdef CONFIG_SANDBOX
+#define getenv uboot_getenv
+#endif
 char	*getenv	     (const char *);
 int	getenv_f     (const char *name, char *buf, unsigned len);
 ulong getenv_ulong(const char *name, int base, ulong default_val);
@@ -665,7 +672,7 @@ int	get_clocks (void);
 int	get_clocks_866 (void);
 int	sdram_adjust_866 (void);
 int	adjust_sdram_tbs_8xx (void);
-#if defined(CONFIG_8260)
+#if defined(CONFIG_MPC8260)
 int	prt_8260_clks (void);
 #elif defined(CONFIG_MPC5xxx)
 int	prt_mpc5xxx_clks (void);
@@ -733,7 +740,7 @@ void	get_sys_info  ( sys_info_t * );
 #endif
 
 /* $(CPU)/cpu_init.c */
-#if defined(CONFIG_8xx) || defined(CONFIG_8260)
+#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260)
 void	cpu_init_f    (volatile immap_t *immr);
 #endif
 #if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2) ||defined(CONFIG_MPC86xx)
@@ -741,7 +748,7 @@ void	cpu_init_f    (void);
 #endif
 
 int	cpu_init_r    (void);
-#if defined(CONFIG_8260)
+#if defined(CONFIG_MPC8260)
 int	prt_8260_rsr  (void);
 #elif defined(CONFIG_MPC83xx)
 int	prt_83xx_rsr  (void);
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 64acc88b7a7..b2483026870 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -16,8 +16,8 @@
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
 #define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
-#define CONFIG_SYS_FSL_PBL_PBI	$(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
-#define CONFIG_SYS_FSL_PBL_RCW	$(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
+#define CONFIG_SYS_FSL_PBL_PBI	board/freescale/b4860qds/b4_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW	board/freescale/b4860qds/b4_rcw.cfg
 #endif
 
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h
index a033a3a1e52..7be83b07876 100644
--- a/include/configs/CPU86.h
+++ b/include/configs/CPU86.h
@@ -17,7 +17,6 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU		*/
 #define CONFIG_CPU86		1	/* ...on a CPU86 board	*/
 #define CONFIG_CPM2		1	/* Has a CPM2 */
 
diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h
index 06876746a7b..d3a59e8ba7e 100644
--- a/include/configs/CPU87.h
+++ b/include/configs/CPU87.h
@@ -17,7 +17,6 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU		*/
 #define CONFIG_CPU87		1	/* ...on a CPU87 board	*/
 #define CONFIG_PCI
 #define CONFIG_CPM2		1	/* Has a CPM2 */
diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h
index 7aaa7768fde..8ccb0ff9d89 100644
--- a/include/configs/IDS8247.h
+++ b/include/configs/IDS8247.h
@@ -17,7 +17,6 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC8260		1	/* This is a MPC8260 CPU		*/
 #define CONFIG_MPC8272_FAMILY	1
 #define CONFIG_IDS8247		1
 #define CPU_ID_STR		"MPC8247"
diff --git a/include/configs/IPHASE4539.h b/include/configs/IPHASE4539.h
index a543855a566..e402075d377 100644
--- a/include/configs/IPHASE4539.h
+++ b/include/configs/IPHASE4539.h
@@ -19,7 +19,6 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU   */
 #define CONFIG_IPHASE4539	1	/* ...on a Interphase 4539 PMC */
 
 #define	CONFIG_SYS_TEXT_BASE	0xffb00000
diff --git a/include/configs/ISPAN.h b/include/configs/ISPAN.h
index a5cea8bc3c5..a2fdfd3274f 100644
--- a/include/configs/ISPAN.h
+++ b/include/configs/ISPAN.h
@@ -13,7 +13,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_MPC8260			/* This is an MPC8260 CPU               */
 #define CONFIG_ISPAN			/* ...on one of Interphase iSPAN boards */
 #define CONFIG_CPM2		1	/* Has a CPM2 */
 
diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h
deleted file mode 100644
index a9531b0bf3b..00000000000
--- a/include/configs/M5271EVB.h
+++ /dev/null
@@ -1,234 +0,0 @@
-/*
- * Configuation settings for the Freescale M5271EVB
- *
- * Based on MC5272C3 and r5200 board configs
- * (C) Copyright 2006 Lab X Technologies <zachary.landau@labxtechnologies.com>
- * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef _M5271EVB_H
-#define _M5271EVB_H
-
-/*
- * High Level Configuration Options (easy to change)
- */
-#define CONFIG_MCF52x2		/* define processor family */
-#define CONFIG_M5271		/* define processor type */
-#define CONFIG_M5271EVB		/* define board type */
-
-#define CONFIG_MCFTMR
-
-#define CONFIG_MCFUART
-#define CONFIG_SYS_UART_PORT		(0)
-#define CONFIG_BAUDRATE		115200
-
-#undef CONFIG_WATCHDOG		/* disable watchdog */
-
-/* Configuration for environment
- * Environment is embedded in u-boot in the second sector of the flash
- */
-#ifndef CONFIG_MONITOR_IS_IN_RAM
-#define CONFIG_ENV_OFFSET		0x4000
-#else
-#define CONFIG_ENV_ADDR		0xffe04000
-#endif
-#define CONFIG_ENV_SECT_SIZE	0x2000
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_MISC
-
-#undef CONFIG_CMD_LOADS
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMDLINE_EDITING	1 /* enables command line history */
-#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
-
-#define CONFIG_MCFFEC
-#ifdef CONFIG_MCFFEC
-#	define CONFIG_MII		1
-#	define CONFIG_MII_INIT		1
-#	define CONFIG_SYS_DISCOVER_PHY
-#	define CONFIG_SYS_RX_ETH_BUFFER	8
-#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-
-#	define CONFIG_SYS_FEC0_PINMUX		0
-#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
-#	define MCFFEC_TOUT_LOOP		50000
-/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
-#	ifndef CONFIG_SYS_DISCOVER_PHY
-#		define FECDUPLEX	FULL
-#		define FECSPEED		_100BASET
-#	else
-#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-#		endif
-#	endif			/* CONFIG_SYS_DISCOVER_PHY */
-#endif
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED	80000
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x00000300
-#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
-
-#define CONFIG_BOOTDELAY	1	/* autoboot after 1 seconds */
-#define CONFIG_BOOTFILE		"u-boot.bin"
-#ifdef CONFIG_MCFFEC
-#	define CONFIG_NET_RETRY_COUNT	5
-#	define CONFIG_ETHADDR	00:e0:0c:bc:e5:60
-#	define CONFIG_IPADDR	192.162.1.2
-#	define CONFIG_NETMASK	255.255.255.0
-#	define CONFIG_SERVERIP	192.162.1.1
-#	define CONFIG_GATEWAYIP	192.162.1.1
-#	define CONFIG_OVERWRITE_ETHADDR_ONCE
-#endif				/* FEC_ENET */
-
-#define CONFIG_HOSTNAME		M5271EVB
-#define CONFIG_EXTRA_ENV_SETTINGS		\
-	"netdev=eth0\0"				\
-	"loadaddr=10000\0"			\
-	"uboot=u-boot.bin\0"		\
-	"load=tftp $loadaddr $uboot\0"	\
-	"upd=run load; run prog\0"		\
-	"prog=prot off ffe00000 ffe3ffff;"	\
-	"era ffe00000 ffe3ffff;"		\
-	"cp.b $loadaddr ffe00000 $filesize;"	\
-	"save\0"				\
-	""
-
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size      */
-#else
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size      */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args   */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
-
-#define CONFIG_SYS_LOAD_ADDR		0x00100000
-
-#define CONFIG_SYS_MEMTEST_START	0x400
-#define CONFIG_SYS_MEMTEST_END		0x380000
-
-#define CONFIG_SYS_HZ			1000000
-
-/* Clock configuration
- * The external oscillator is a 25.000 MHz
- * CONFIG_SYS_CLK for ColdFire V2 sets cpu_clk (not bus_clk)
- * bus_clk = (cpu_clk/2) (fixed ratio)
- *
- * If CONFIG_SYS_CLK is changed. the CONFIG_SYS_MCF_SYNCR must be updated to
- * match the new clock speed. Max cpu_clk is 150 MHz.
- */
-#define CONFIG_SYS_CLK			100000000
-#define CONFIG_SYS_MCF_SYNCR 	(MCF_SYNCR_MFD_4X | MCF_SYNCR_RFD_DIV1)
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#define CONFIG_SYS_MBAR		0x40000000	/* Register Base Addrs */
-
-/*
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM    */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
-#define CONFIG_SYS_FLASH_BASE		0xffe00000
-
-#ifdef	CONFIG_MONITOR_IS_IN_RAM
-#define CONFIG_SYS_MONITOR_BASE	0x20000
-#else
-#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN		0x40000
-#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
-#define CONFIG_SYS_BOOTPARAMS_LEN	(64*1024)
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization ??
- */
-#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
-
-/* FLASH organization */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks           */
-#define CONFIG_SYS_MAX_FLASH_SECT	11	/* max number of sectors on one chip    */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	1000
-
-#define CONFIG_SYS_FLASH_CFI		1
-#define CONFIG_FLASH_CFI_DRIVER	1
-#define CONFIG_SYS_FLASH_SIZE		0x200000
-
-/* Cache Configuration */
-#define CONFIG_SYS_CACHELINE_SIZE	16
-
-#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
-#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
-					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
-					 CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
-					 CF_CACR_DISD | CF_CACR_INVI | \
-					 CF_CACR_CEIB | CF_CACR_DCM | \
-					 CF_CACR_EUSP)
-
-/* Chip Select 0  : Boot Flash */
-#define CONFIG_SYS_CS0_BASE	0xFFE00000
-#define CONFIG_SYS_CS0_MASK	0x001F0001
-#define CONFIG_SYS_CS0_CTRL	0x00001980
-
-/* Chip Select 1 : External SRAM */
-#define CONFIG_SYS_CS1_BASE	0x30000000
-#define CONFIG_SYS_CS1_MASK	0x00070001
-#define CONFIG_SYS_CS1_CTRL	0x00001900
-
-#endif				/* _M5271EVB_H */
diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h
index 3def26929b6..39f7564b74d 100644
--- a/include/configs/MPC8260ADS.h
+++ b/include/configs/MPC8260ADS.h
@@ -64,8 +64,6 @@
  * details. :-(
  */
 #define CONFIG_MPC8272		1
-#else
-#define CONFIG_MPC8260		1
 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
 
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h
index 39c90aa2b0e..8d9c8fb45c9 100644
--- a/include/configs/MPC8266ADS.h
+++ b/include/configs/MPC8266ADS.h
@@ -33,7 +33,6 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU	*/
 #define CONFIG_MPC8266ADS	1	/* ...on motorola ADS board	*/
 #define CONFIG_CPM2		1	/* Has a CPM2 */
 
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 47c638422f5..b3880f190f9 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -18,9 +18,8 @@
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
 #define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
-#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg
-#define CONFIG_SYS_FSL_PBL_RCW \
-			$(SRCTREE)/board/freescale/corenet_ds/rcw_p2041rdb.cfg
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg
 #endif
 
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
diff --git a/include/configs/PM826.h b/include/configs/PM826.h
index 5aeba4dc4e6..6416ad52270 100644
--- a/include/configs/PM826.h
+++ b/include/configs/PM826.h
@@ -19,7 +19,6 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC8260		1	/* This is a MPC8260 CPU	*/
 #define CONFIG_PM826		1	/* ...on a PM8260 module	*/
 #define CONFIG_CPM2		1	/* Has a CPM2 */
 
diff --git a/include/configs/PM828.h b/include/configs/PM828.h
index 49b4571e1ac..e17fbfbbf84 100644
--- a/include/configs/PM828.h
+++ b/include/configs/PM828.h
@@ -19,7 +19,6 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC8260		1	/* This is a MPC8260 CPU	*/
 #define CONFIG_PM828		1	/* ...on a PM828 module */
 #define CONFIG_CPM2		1	/* Has a CPM2 */
 
diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h
index fd39109dafe..c5e2f164ce0 100644
--- a/include/configs/PMC440.h
+++ b/include/configs/PMC440.h
@@ -95,12 +95,7 @@
 /*-----------------------------------------------------------------------
  * Environment
  *----------------------------------------------------------------------*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CONFIG_ENV_IS_IN_EEPROM	1	/* use FLASH for environment vars */
-#else
-#define CONFIG_ENV_IS_IN_NAND	1	/* use NAND for environment vars */
-#define CONFIG_ENV_IS_EMBEDDED	1	/* use embedded environment */
-#endif
 
 /*-----------------------------------------------------------------------
  * RTC
@@ -142,69 +137,10 @@
 #define CONFIG_ENV_SIZE		0x1000	/* 4096 bytes may be used for env vars */
 #endif
 
-/*
- * IPL (Initial Program Loader, integrated inside CPU)
- * Will load first 4k from NAND (SPL) into cache and execute it from there.
- *
- * SPL (Secondary Program Loader)
- * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
- * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
- * controller and the NAND controller so that the special U-Boot image can be
- * loaded from NAND to SDRAM.
- *
- * NUB (NAND U-Boot)
- * This NAND U-Boot (NUB) is a special U-Boot version which can be started
- * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
- *
- * On 440EPx the SPL is copied to SDRAM before the NAND controller is
- * set up. While still running from cache, I experienced problems accessing
- * the NAND controller.	sr - 2006-08-25
- */
-#if defined (CONFIG_NAND_U_BOOT)
-#define CONFIG_SYS_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location                 */
-#define CONFIG_SYS_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size                     */
-#define CONFIG_SYS_NAND_BOOT_SPL_DST	(CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here    */
-#define CONFIG_SYS_NAND_U_BOOT_DST	0x01000000	/* Load NUB to this addr        */
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */
-#define CONFIG_SYS_NAND_BOOT_SPL_DELTA	(CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
-
-/*
- * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
- */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	(16 << 10)	/* Offset to RAM U-Boot image   */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(384 << 10)	/* Size of RAM U-Boot image     */
-
-/*
- * Now the NAND chip has to be defined (no autodetection used!)
- */
-#define CONFIG_SYS_NAND_PAGE_SIZE	512	/* NAND chip page size          */
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 << 10) /* NAND chip block size      */
-#define CONFIG_SYS_NAND_PAGE_COUNT	32	/* NAND chip page count         */
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS	5	/* Location of bad block marker */
-#undef CONFIG_SYS_NAND_4_ADDR_CYCLE		/* No fourth addr used (<=32MB) */
-
-#define CONFIG_SYS_NAND_ECCSIZE	256
-#define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_SYS_NAND_OOBSIZE	16
-#define CONFIG_SYS_NAND_ECCPOS		{0, 1, 2, 3, 6, 7}
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_NAND
-/*
- * For NAND booting the environment is embedded in the U-Boot image. Please take
- * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
- */
-#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET		(CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#endif
-
 /*-----------------------------------------------------------------------
  * DDR SDRAM
  *----------------------------------------------------------------------*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CONFIG_DDR_DATA_EYE	/* use DDR2 optimization        */
-#endif
 #define CONFIG_SYS_MEM_TOP_HIDE	(4 << 10) /* don't use last 4kbytes */
 						  /* 440EPx errata CHIP 11 */
 
@@ -448,7 +384,6 @@
 /*
  * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
  */
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CONFIG_SYS_NAND_CS		2	/* NAND chip connected to CSx   */
 
 /* Memory Bank 0 (NOR-FLASH) initialization */
@@ -458,16 +393,6 @@
 /* Memory Bank 2 (NAND-FLASH) initialization */
 #define CONFIG_SYS_EBC_PB2AP		0x018003c0
 #define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_NAND_ADDR | 0x1c000)
-#else
-#define CONFIG_SYS_NAND_CS		0	/* NAND chip connected to CSx   */
-/* Memory Bank 2 (NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB2AP		0x03017200
-#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_FLASH_BASE | 0xda000)
-
-/* Memory Bank 0 (NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP		0x018003c0
-#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_NAND_ADDR | 0x1c000)
-#endif
 
 /* Memory Bank 1 (RESET) initialization */
 #define CONFIG_SYS_EBC_PB1AP		0x7f817200 /* 0x03017200 */
diff --git a/include/configs/RPXsuper.h b/include/configs/RPXsuper.h
index 28884295e79..f5e09680119 100644
--- a/include/configs/RPXsuper.h
+++ b/include/configs/RPXsuper.h
@@ -184,7 +184,6 @@
  *
  *****************************************************************************/
 
-#define CONFIG_MPC8260          1       /* This is an MPC8260 CPU   */
 #define CONFIG_RPXSUPER         1       /* on an Embedded Planet RPX Super Board  */
 #define CONFIG_CPM2		1	/* Has a CPM2 */
 
diff --git a/include/configs/Rattler.h b/include/configs/Rattler.h
index 1cdd18c0ba6..a1e2ae97532 100644
--- a/include/configs/Rattler.h
+++ b/include/configs/Rattler.h
@@ -13,7 +13,6 @@
 #ifdef CONFIG_MPC8248
 #define CPU_ID_STR		"MPC8248"
 #else
-#define CONFIG_MPC8260
 #define CPU_ID_STR		"MPC8250"
 #endif /* CONFIG_MPC8248 */
 
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index da6e76002e3..993f9ae5336 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -32,8 +32,8 @@
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
 #define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
-#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t1040qds/t1040_pbi.cfg
-#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t1040qds/t1040_rcw.cfg
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg
 #endif
 
 /* High Level Configuration Options */
@@ -375,7 +375,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
 
 /* Serial Port - controlled on board with jumper J8
  * open - index 2
@@ -401,6 +401,25 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 
+/* Video */
+#define CONFIG_FSL_DIU_FB
+#ifdef CONFIG_FSL_DIU_FB
+#define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_CCSRBAR + 0x180000)
+#define CONFIG_VIDEO
+#define CONFIG_CMD_BMP
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+/*
+ * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
+ * disable empty flash sector detection, which is I/O-intensive.
+ */
+#undef CONFIG_SYS_FLASH_EMPTY_INFO
+#endif
+
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT
 #define CONFIG_OF_BOARD_SETUP
@@ -426,6 +445,11 @@ unsigned long get_board_ddr_clk(void);
 
 /* I2C bus multiplexer */
 #define I2C_MUX_CH_DEFAULT      0x8
+#define I2C_MUX_CH_DIU		0xC
+
+/* LDI/DVI Encoder for display */
+#define CONFIG_SYS_I2C_LDI_ADDR         0x38
+#define CONFIG_SYS_I2C_DVI_ADDR         0x75
 
 /*
  * RTC configuration
@@ -703,6 +727,7 @@ unsigned long get_board_ddr_clk(void);
 	"bank_intlv=cs0_cs1;"					\
 	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 	"netdev=eth0\0"						\
+	"video-mode=fslfb:1024x768-32@60,monitor=dvi\0"		\
 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
 	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
 	"tftpflash=tftpboot $loadaddr $uboot && "		\
diff --git a/include/configs/T1040RDB.h b/include/configs/T1040RDB.h
index fd010c057c3..395845bd68d 100644
--- a/include/configs/T1040RDB.h
+++ b/include/configs/T1040RDB.h
@@ -147,7 +147,7 @@
 
 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
-#define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 
 #define CONFIG_DDR_SPD
 #define CONFIG_SYS_DDR_RAW_TIMING
diff --git a/include/configs/T1042RDB_PI.h b/include/configs/T1042RDB_PI.h
index 6d07805ffd0..68656e6ef15 100644
--- a/include/configs/T1042RDB_PI.h
+++ b/include/configs/T1042RDB_PI.h
@@ -147,7 +147,7 @@
 
 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
-#define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 
 #define CONFIG_DDR_SPD
 #define CONFIG_SYS_DDR_RAW_TIMING
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 5b22d644673..399ddbb791c 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -48,11 +48,11 @@
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
 #define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
-#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t208xqds/t208x_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
 #if defined(CONFIG_PPC_T2080)
-#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t208xqds/t2080_rcw.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_rcw.cfg
 #elif defined(CONFIG_PPC_T2081)
-#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t208xqds/t2081_rcw.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_rcw.cfg
 #endif
 #endif
 
@@ -242,7 +242,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
 					FTIM1_GPCM_TRAD(0x3f))
 #define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
-					FTIM2_GPCM_TCH(0x0) | \
+					FTIM2_GPCM_TCH(0x8) | \
 					FTIM2_GPCM_TWP(0x1f))
 #define CONFIG_SYS_CS3_FTIM3		0x0
 
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
new file mode 100644
index 00000000000..743eee3161c
--- /dev/null
+++ b/include/configs/T208xRDB.h
@@ -0,0 +1,779 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/*
+ * T2080 RDB/PCIe board configuration file
+ */
+
+#ifndef __T2080RDB_H
+#define __T2080RDB_H
+
+#define CONFIG_T2080RDB
+#define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
+#define CONFIG_MMC
+#define CONFIG_SPI_FLASH
+#define CONFIG_USB_EHCI
+#define CONFIG_FSL_SATA_V2
+
+/* High Level Configuration Options */
+#define CONFIG_PHYS_64BIT
+#define CONFIG_BOOKE
+#define CONFIG_E500		/* BOOKE e500 family */
+#define CONFIG_E500MC		/* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV	/* Category E.HV supported */
+#define CONFIG_MP		/* support multiple processors */
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP 1
+#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_FSL_CPC	/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC	CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_IFC		/* Enable IFC Support */
+#define CONFIG_FSL_LAW		/* Use common FSL init code */
+#define CONFIG_ENV_OVERWRITE
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_rcw.cfg
+#endif
+
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+/* Set 1M boot space */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xeff40000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BTB		/* toggle branch predition */
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#endif
+
+#ifdef CONFIG_SYS_NO_FLASH
+#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+#else
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS	0
+#define CONFIG_ENV_SPI_CS	0
+#define CONFIG_ENV_SPI_MAX_HZ	10000000
+#define CONFIG_ENV_SPI_MODE	0
+#define CONFIG_ENV_SIZE		0x2000	   /* 8KB */
+#define CONFIG_ENV_OFFSET	0x100000   /* 1MB */
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV	0
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_OFFSET	(512 * 1658)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET	(2 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_IS_IN_REMOTE
+#define CONFIG_ENV_ADDR		0xffe20000
+#define CONFIG_ENV_SIZE		0x2000
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE		0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	66660000
+#define CONFIG_DDR_CLK_FREQ	133330000
+
+/*
+ * Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR	 CONFIG_RAMBOOT_TEXT_BASE
+
+#define CONFIG_SYS_DCSRBAR	0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS	0xf00000000ull
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_FSL_DDR3
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define CONFIG_SYS_SDRAM_SIZE	2048	/* for fixed parameter use */
+#define SPD_EEPROM_ADDRESS1	0x51
+#define SPD_EEPROM_ADDRESS2	0x52
+#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
+#define CTRL_INTLV_PREFERED	cacheline
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE		0xe8000000
+#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
+
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1A) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS }
+
+/* CPLD on IFC */
+#define CONFIG_SYS_CPLD_BASE	0xffdf0000
+#define CONFIG_SYS_CPLD_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_CPLD_BASE)
+#define CONFIG_SYS_CSPR2_EXT	(0xf)
+#define CONFIG_SYS_CSPR2	(CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+#define CONFIG_SYS_AMASK2	IFC_AMASK(64*1024)
+#define CONFIG_SYS_CSOR2	0x0
+
+/* CPLD Timing parameters for IFC CS2 */
+#define CONFIG_SYS_CS2_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS2_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
+					FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_CS2_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+					FTIM2_GPCM_TCH(0x0) | \
+					FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS2_FTIM3		0x0
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	 /* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */	    \
+				| CSOR_NAND_RAL_3	/* RAL = 2Byes */   \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */\
+				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */\
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+					FTIM0_NAND_TWP(0x18)    | \
+					FTIM0_NAND_TWCHT(0x07)  | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)   | \
+					FTIM1_NAND_TRR(0x0e)    | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f)  | \
+					FTIM2_NAND_TREH(0x0a)   | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(512 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_MONITOR_BASE	 CONFIG_SYS_TEXT_BASE
+#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe0ec000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+			((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+			CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+						GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
+#define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
+#define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
+#define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
+#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
+#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
+#define CONFIG_SYS_FSL_I2C_SPEED   100000
+#define CONFIG_SYS_FSL_I2C2_SPEED  100000
+#define CONFIG_SYS_FSL_I2C3_SPEED  100000
+#define CONFIG_SYS_FSL_I2C4_SPEED  100000
+#define I2C_MUX_PCA_ADDR_PRI	0x77 /* I2C bus multiplexer,primary */
+#define I2C_MUX_PCA_ADDR_SEC1	0x75 /* I2C bus multiplexer,secondary 1 */
+#define I2C_MUX_PCA_ADDR_SEC2	0x76 /* I2C bus multiplexer,secondary 2 */
+#define I2C_MUX_CH_DEFAULT	0x8
+
+
+/*
+ * RapidIO
+ */
+#define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
+#define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000 /* 256M */
+/*
+ * for slave u-boot IMAGE instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x80000 /* 512K */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+/*
+ * for slave UCODE and ENV instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000	/* 256K */
+
+/* slave core release by master*/
+#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+
+/*
+ * SRIO_PCIE_BOOT - SLAVE
+ */
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+#endif
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#ifdef CONFIG_SPI_FLASH
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED	 10000000
+#define CONFIG_SF_DEFAULT_MODE	  0
+#endif
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_PCI		/* Enable PCI/PCIE */
+#define CONFIG_PCIE1		/* PCIE controler 1 */
+#define CONFIG_PCIE2		/* PCIE controler 2 */
+#define CONFIG_PCIE3		/* PCIE controler 3 */
+#define CONFIG_PCIE4		/* PCIE controler 4 */
+#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xb0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc30000000ull
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 4, Base address 203000 */
+#define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
+#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc40000000ull
+#define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
+#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata LSZ ADD */
+#define CONFIG_NET_MULTI
+#define CONFIG_E1000
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS	18
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_QMAN_NUM_PORTALS	18
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+#define CONFIG_SYS_PMAN
+#define CONFIG_SYS_DPAA_DCE
+#define CONFIG_SYS_DPAA_RMAN		/* RMan */
+#define CONFIG_SYS_INTERLAKEN
+
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0x110000
+#define CONFIG_CORTINA_FW_ADDR		0x120000
+
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 825KB (1650 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	(512 * 1680)
+#define CONFIG_CORTINA_FW_ADDR		(512 * 1808)
+
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	(6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_CORTINA_FW_ADDR		(7 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0xFFE00000
+#define CONFIG_CORTINA_FW_ADDR		0xFFE10000
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0xEFF00000
+#define CONFIG_CORTINA_FW_ADDR		0xEFE00000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_CORTINA
+#define CONFIG_PHY_AQ1202
+#define CONFIG_PHY_REALTEK
+#define CONFIG_CORTINA_FW_LENGTH	0x40000
+#define RGMII_PHY1_ADDR		0x01  /* RealTek RTL8211E */
+#define RGMII_PHY2_ADDR		0x02
+#define CORTINA_PHY_ADDR1	0x0c  /* Cortina CS4315 */
+#define CORTINA_PHY_ADDR2	0x0d
+#define FM1_10GEC3_PHY_ADDR	0x00  /* Aquantia AQ1202 10G Base-T */
+#define FM1_10GEC4_PHY_ADDR	0x01
+#endif
+
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_MII		/* MII PHY management */
+#define CONFIG_ETHPRIME		"FM1@DTSEC3"
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * SATA
+ */
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
+ * USB
+ */
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+#define CONFIG_HAS_FSL_DR_USB
+#endif
+
+/*
+ * SDHC
+ */
+#ifdef CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * Environment
+ */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_BDI
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT	"=> "	  /* Monitor Command Prompt */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE	1024	  /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256	  /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH	 "/opt/nfsroot"
+#define CONFIG_BOOTFILE	 "uImage"
+#define CONFIG_UBOOTPATH "u-boot.bin"	/* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
+#define __USB_PHY_TYPE		utmi
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hwconfig=fsl_ddr:"					\
+	"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","	\
+	"bank_intlv=auto;"					\
+	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
+	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
+	"tftpflash=tftpboot $loadaddr $uboot && "		\
+	"protect off $ubootaddr +$filesize && "			\
+	"erase $ubootaddr +$filesize && "			\
+	"cp.b $loadaddr $ubootaddr $filesize && "		\
+	"protect on $ubootaddr +$filesize && "			\
+	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
+	"consoledev=ttyS0\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=t2080rdb/ramdisk.uboot\0"			\
+	"fdtaddr=c00000\0"					\
+	"fdtfile=t2080rdb/t2080rdb.dtb\0"			\
+	"bdev=sda3\0"						\
+	"c=ffe\0"
+
+/*
+ * For emulation this causes u-boot to jump to the start of the
+ * proof point app code automatically
+ */
+#define CONFIG_PROOF_POINTS				\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"cpu 1 release 0x29000000 - - -;"		\
+	"cpu 2 release 0x29000000 - - -;"		\
+	"cpu 3 release 0x29000000 - - -;"		\
+	"cpu 4 release 0x29000000 - - -;"		\
+	"cpu 5 release 0x29000000 - - -;"		\
+	"cpu 6 release 0x29000000 - - -;"		\
+	"cpu 7 release 0x29000000 - - -;"		\
+	"go 0x29000000"
+
+#define CONFIG_HVBOOT				\
+	"setenv bootargs config-addr=0x60000000; "	\
+	"bootm 0x01000000 - 0x00f00000"
+
+#define CONFIG_ALU				\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"cpu 1 release 0x01000000 - - -;"		\
+	"cpu 2 release 0x01000000 - - -;"		\
+	"cpu 3 release 0x01000000 - - -;"		\
+	"cpu 4 release 0x01000000 - - -;"		\
+	"cpu 5 release 0x01000000 - - -;"		\
+	"cpu 6 release 0x01000000 - - -;"		\
+	"cpu 7 release 0x01000000 - - -;"		\
+	"go 0x01000000"
+
+#define CONFIG_LINUX				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"setenv ramdiskaddr 0x02000000;"		\
+	"setenv fdtaddr 0x00c00000;"			\
+	"setenv loadaddr 0x1000000;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_HDBOOT					\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND			\
+	"setenv bootargs root=/dev/nfs rw "	\
+	"nfsroot=$serverip:$rootpath "		\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $ramdiskaddr $ramdiskfile;"		\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_LINUX
+
+#ifdef CONFIG_SECURE_BOOT
+#include <asm/fsl_secure_boot.h>
+#undef CONFIG_CMD_USB
+#endif
+
+#endif	/* __T2080RDB_H */
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index 0d43c27916a..56e1293720c 100644
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -21,8 +21,8 @@
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
 #define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
-#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4qds/t4_pbi.cfg
-#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4qds/t4_rcw.cfg
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_rcw.cfg
 #endif
 
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
diff --git a/include/configs/TQM8260.h b/include/configs/TQM8260.h
index b34b0a865be..7fd12d3fbc6 100644
--- a/include/configs/TQM8260.h
+++ b/include/configs/TQM8260.h
@@ -30,7 +30,6 @@
 
 #define	CONFIG_SYS_TEXT_BASE	0x40000000
 
-#define CONFIG_MPC8260		1	/* This is a MPC8260 CPU		*/
 
 #if 0
 #define CONFIG_TQM8260		100	/* ...on a TQM8260 module Rev.100	*/
diff --git a/include/configs/TQM8272.h b/include/configs/TQM8272.h
index 78e8b03cd1a..9c7e16305d1 100644
--- a/include/configs/TQM8272.h
+++ b/include/configs/TQM8272.h
@@ -17,7 +17,6 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC8260		1	/* This is a MPC8260 CPU		*/
 #define CONFIG_MPC8272_FAMILY   1
 #define CONFIG_TQM8272		1
 
diff --git a/include/configs/ZPC1900.h b/include/configs/ZPC1900.h
index 01cb2c85c02..d76a1407285 100644
--- a/include/configs/ZPC1900.h
+++ b/include/configs/ZPC1900.h
@@ -11,7 +11,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU      */
 #define CONFIG_ZPC1900		1	/* ...on Zephyr ZPC.1900 board */
 
 #define	CONFIG_SYS_TEXT_BASE	0xFE000000
diff --git a/include/configs/acadia.h b/include/configs/acadia.h
index 5f3b5f936f1..4dd5720d2f5 100644
--- a/include/configs/acadia.h
+++ b/include/configs/acadia.h
@@ -82,17 +82,11 @@
 /*-----------------------------------------------------------------------
  * Environment
  *----------------------------------------------------------------------*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
-#else
-#define CONFIG_ENV_IS_IN_NAND	1	/* use NAND for environment vars	*/
-#define CONFIG_ENV_IS_EMBEDDED	1	/* use embedded environment */
-#endif
 
 /*-----------------------------------------------------------------------
  * FLASH related
  *----------------------------------------------------------------------*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
 #define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
 
@@ -106,16 +100,6 @@
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
 #define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
-#else
-/*
- * No NOR-flash on Acadia when NAND-booting. We need to undef the
- * NOR device-tree fixup code as well, since flash_info is not defined
- * in this case.
- */
-#define	CONFIG_SYS_NO_FLASH		1
-#undef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
-#endif
-
 #ifdef CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	0x40000 /* size of one complete sector	*/
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
@@ -126,61 +110,6 @@
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 #endif
 
-/*
- * IPL (Initial Program Loader, integrated inside CPU)
- * Will load first 4k from NAND (SPL) into cache and execute it from there.
- *
- * SPL (Secondary Program Loader)
- * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
- * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
- * controller and the NAND controller so that the special U-Boot image can be
- * loaded from NAND to SDRAM.
- *
- * NUB (NAND U-Boot)
- * This NAND U-Boot (NUB) is a special U-Boot version which can be started
- * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
- *
- * On 440EPx the SPL is copied to SDRAM before the NAND controller is
- * set up. While still running from cache, I experienced problems accessing
- * the NAND controller.	sr - 2006-08-25
- */
-#define CONFIG_SYS_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location			*/
-#define CONFIG_SYS_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size			*/
-#define CONFIG_SYS_NAND_BOOT_SPL_DST	(CONFIG_SYS_OCM_DATA_ADDR + (16 << 10)) /* Copy SPL here*/
-#define CONFIG_SYS_NAND_U_BOOT_DST	0x01000000	/* Load NUB to this addr	*/
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr	*/
-#define CONFIG_SYS_NAND_BOOT_SPL_DELTA	(CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
-
-/*
- * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
- */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	(16 << 10)	/* Offset to RAM U-Boot image	*/
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(384 << 10)	/* Size of RAM U-Boot image	*/
-
-/*
- * Now the NAND chip has to be defined (no autodetection used!)
- */
-#define CONFIG_SYS_NAND_PAGE_SIZE	512		/* NAND chip page size		*/
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 << 10)	/* NAND chip block size		*/
-#define CONFIG_SYS_NAND_PAGE_COUNT	32		/* NAND chip page count		*/
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS	5		/* Location of bad block marker	*/
-#undef CONFIG_SYS_NAND_4_ADDR_CYCLE			/* No fourth addr used (<=32MB)	*/
-
-#define CONFIG_SYS_NAND_ECCSIZE	256
-#define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_SYS_NAND_OOBSIZE	16
-#define CONFIG_SYS_NAND_ECCPOS		{0, 1, 2, 3, 6, 7}
-
-#ifdef CONFIG_ENV_IS_IN_NAND
-/*
- * For NAND booting the environment is embedded in the U-Boot image. Please take
- * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
- */
-#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET		(CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#endif
-
 /*-----------------------------------------------------------------------
  * RAM (CRAM)
  *----------------------------------------------------------------------*/
@@ -219,7 +148,6 @@
 	CONFIG_AMCC_DEF_ENV_POWERPC					\
 	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
 	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
-	CONFIG_AMCC_DEF_ENV_NAND_UPD					\
 	"kernel_addr=fff10000\0"					\
 	"ramdisk_addr=fff20000\0"					\
 	"kozio=bootm ffc60000\0"					\
@@ -242,14 +170,6 @@
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_USB
 
-/*
- * No NOR on Acadia when NAND-booting
- */
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
-#endif
-
 /*-----------------------------------------------------------------------
  * NAND FLASH
  *----------------------------------------------------------------------*/
@@ -260,7 +180,6 @@
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  *----------------------------------------------------------------------*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CONFIG_SYS_NAND_CS		3
 /* Memory Bank 0 (Flash) initialization						*/
 #define CONFIG_SYS_EBC_PB0AP		0x03337200
@@ -278,24 +197,6 @@
 /* Memory Bank 2 (CRAM) initialization						*/
 #define CONFIG_SYS_EBC_PB2AP		0x030400c0
 #define CONFIG_SYS_EBC_PB2CR		0x020bc000
-#else
-#define CONFIG_SYS_NAND_CS		0		/* NAND chip connected to CSx	*/
-/* Memory Bank 0 (NAND-FLASH) initialization					*/
-#define CONFIG_SYS_EBC_PB0AP		0x018003c0
-#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_NAND_ADDR | 0x1c000)
-
-/*
- * When NAND-booting the CRAM EBC setup must be done in sync mode, since the
- * NAND-SPL already initialized the CRAM and EBC to sync mode.
- */
-/* Memory Bank 1 (CRAM) initialization						*/
-#define CONFIG_SYS_EBC_PB1AP		0x9C0201C0
-#define CONFIG_SYS_EBC_PB1CR		0x000bc000
-
-/* Memory Bank 2 (CRAM) initialization						*/
-#define CONFIG_SYS_EBC_PB2AP		0x9C0201C0
-#define CONFIG_SYS_EBC_PB2CR		0x020bc000
-#endif
 
 /* Memory Bank 4 (CPLD) initialization						*/
 #define CONFIG_SYS_EBC_PB4AP		0x04006000
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 23c056c82cb..fd6f52c6b10 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -403,7 +403,6 @@
 /* NAND support */
 #ifdef CONFIG_NAND
 #define CONFIG_CMD_NAND
-#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
 #if !defined(CONFIG_SPI_BOOT) && !defined(CONFIG_NOR_BOOT)
 #define MTDIDS_DEFAULT			"nand0=omap2-nand.0"
 #define MTDPARTS_DEFAULT		"mtdparts=omap2-nand.0:128k(SPL)," \
@@ -443,6 +442,8 @@
 #define CONFIG_SYS_FLASH_BASE		(0x08000000)
 #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+/* Reduce SPL size by removing unlikey targets */
+#undef CONFIG_SPL_SPI_SUPPORT
 #ifdef CONFIG_NOR_BOOT
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE		(128 << 10)	/* 128 KiB */
diff --git a/include/configs/am335x_igep0033.h b/include/configs/am335x_igep0033.h
index e72ee05ec8c..c17327fef48 100644
--- a/include/configs/am335x_igep0033.h
+++ b/include/configs/am335x_igep0033.h
@@ -187,7 +187,6 @@
 #define CONFIG_NAND
 #define CONFIG_NAND_OMAP_GPMC
 #define CONFIG_NAND_OMAP_ELM
-#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
 #define CONFIG_SYS_NAND_BASE		(0x08000000)	/* phys address CS0 */
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_SYS_NAND_ONFI_DETECTION	1
diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h
index 468fb43ea8e..4407b454dd1 100644
--- a/include/configs/am3517_crane.h
+++ b/include/configs/am3517_crane.h
@@ -268,7 +268,6 @@
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 
 #define CONFIG_NAND_OMAP_GPMC
-#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
 #define CONFIG_ENV_IS_IN_NAND		1
 #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
 
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index b8b99c806fa..0102ff5b7f9 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -277,7 +277,6 @@
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 
 #define CONFIG_NAND_OMAP_GPMC
-#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
 #define CONFIG_ENV_IS_IN_NAND		1
 #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
 
diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h
index 0f38c92fa06..2aea89937a2 100644
--- a/include/configs/amcc-common.h
+++ b/include/configs/amcc-common.h
@@ -253,10 +253,4 @@
 		"cp.b ${fileaddr} " __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
 	"upd=run load update\0"						\
 
-#define CONFIG_AMCC_DEF_ENV_NAND_UPD					\
-	"u-boot-nand=" __stringify(CONFIG_HOSTNAME) "/u-boot-nand.bin\0"\
-	"nload=tftp 200000 ${u-boot-nand}\0"				\
-	"nupdate=nand erase 0 100000;nand write 200000 0 100000\0"	\
-	"nupd=run nload nupdate\0"
-
 #endif /* __AMCC_COMMON_H */
diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h
index 5d96c31f99c..a30c016b41c 100644
--- a/include/configs/at91rm9200ek.h
+++ b/include/configs/at91rm9200ek.h
@@ -14,7 +14,7 @@
 #ifndef __AT91RM9200EK_CONFIG_H__
 #define __AT91RM9200EK_CONFIG_H__
 
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 
 /*
  * set some initial configurations depending on configure target
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index b9aa0360396..48c12ea8801 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -103,6 +103,7 @@
 #define CONFIG_CMD_PING		1
 #define CONFIG_CMD_DHCP		1
 #define CONFIG_CMD_NAND		1
+#define CONFIG_CMD_MMC
 #define CONFIG_CMD_USB		1
 
 /* SDRAM */
@@ -123,6 +124,18 @@
 #define DATAFLASH_TCSS			(0x1a << 16)
 #define DATAFLASH_TCHS			(0x1 << 24)
 
+/* MMC */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#endif
+
+/* FAT */
+#ifdef CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
 /* NOR flash, if populated */
 #ifdef CONFIG_SYS_USE_NORFLASH
 #define CONFIG_SYS_FLASH_CFI			1
diff --git a/include/configs/atc.h b/include/configs/atc.h
index fa391b62802..77fa79a185d 100644
--- a/include/configs/atc.h
+++ b/include/configs/atc.h
@@ -17,7 +17,6 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU		*/
 #define CONFIG_ATC		1	/* ...on a ATC board	*/
 #define CONFIG_CPM2		1	/* Has a CPM2 */
 
diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h
index 97da1e9078a..6ba4aaf8cb7 100644
--- a/include/configs/bamboo.h
+++ b/include/configs/bamboo.h
@@ -86,12 +86,7 @@
 /*-----------------------------------------------------------------------
  * Environment
  *----------------------------------------------------------------------*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
-#else
-#define CONFIG_ENV_IS_IN_NAND	1	/* use NAND for environment vars	*/
-#define CONFIG_ENV_IS_EMBEDDED	1	/* use embedded environment */
-#endif
 
 /*-----------------------------------------------------------------------
  * FLASH related
@@ -120,61 +115,6 @@
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 #endif /* CONFIG_ENV_IS_IN_FLASH */
 
-/*
- * IPL (Initial Program Loader, integrated inside CPU)
- * Will load first 4k from NAND (SPL) into cache and execute it from there.
- *
- * SPL (Secondary Program Loader)
- * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
- * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
- * controller and the NAND controller so that the special U-Boot image can be
- * loaded from NAND to SDRAM.
- *
- * NUB (NAND U-Boot)
- * This NAND U-Boot (NUB) is a special U-Boot version which can be started
- * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
- *
- * On 440EPx the SPL is copied to SDRAM before the NAND controller is
- * set up. While still running from cache, I experienced problems accessing
- * the NAND controller.	sr - 2006-08-25
- */
-#define CONFIG_SYS_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location			*/
-#define CONFIG_SYS_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size			*/
-#define CONFIG_SYS_NAND_BOOT_SPL_DST	0x00800000	/* Copy SPL here		*/
-#define CONFIG_SYS_NAND_U_BOOT_DST	0x01000000	/* Load NUB to this addr	*/
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr	*/
-#define CONFIG_SYS_NAND_BOOT_SPL_DELTA	(CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
-
-/*
- * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
- */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	(16 << 10)	/* Offset to RAM U-Boot image	*/
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(384 << 10)	/* Size of RAM U-Boot image	*/
-
-/*
- * Now the NAND chip has to be defined (no autodetection used!)
- */
-#define CONFIG_SYS_NAND_PAGE_SIZE	512		/* NAND chip page size		*/
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 << 10)	/* NAND chip block size		*/
-#define CONFIG_SYS_NAND_PAGE_COUNT	32		/* NAND chip page count		*/
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS	5		/* Location of bad block marker	*/
-#define CONFIG_SYS_NAND_4_ADDR_CYCLE	1		/* Fourth addr used (>32MB)	*/
-
-#define CONFIG_SYS_NAND_ECCSIZE	256
-#define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_SYS_NAND_OOBSIZE	16
-#define CONFIG_SYS_NAND_ECCPOS		{0, 1, 2, 3, 6, 7}
-
-#ifdef CONFIG_ENV_IS_IN_NAND
-/*
- * For NAND booting the environment is embedded in the U-Boot image. Please take
- * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
- */
-#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET		(CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#endif
-
 /*-----------------------------------------------------------------------
  * NAND FLASH
  *----------------------------------------------------------------------*/
@@ -182,15 +122,7 @@
 #define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_ADDR + 2 }
 #define CONFIG_SYS_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips	*/
-
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CONFIG_SYS_NAND_CS		1
-#else
-#define CONFIG_SYS_NAND_CS		0		/* NAND chip connected to CSx	*/
-/* Memory Bank 0 (NAND-FLASH) initialization					*/
-#define CONFIG_SYS_EBC_PB0AP		0x018003c0
-#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_NAND_ADDR | 0x1c000)
-#endif
 
 /*-----------------------------------------------------------------------
  * DDR SDRAM
@@ -226,7 +158,6 @@
 	CONFIG_AMCC_DEF_ENV_POWERPC					\
 	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
 	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
-	CONFIG_AMCC_DEF_ENV_NAND_UPD					\
 	"kernel_addr=fff00000\0"					\
 	"ramdisk_addr=fff10000\0"					\
 	""
diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h
index 8e1c81fc13a..e93b855f8f6 100644
--- a/include/configs/bcm28155_ap.h
+++ b/include/configs/bcm28155_ap.h
@@ -7,7 +7,7 @@
 #ifndef __BCM28155_AP_H
 #define __BCM28155_AP_H
 
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 #include <asm/arch/sysmap.h>
 
 /* Architecture, CPU, chip, mach, etc */
diff --git a/include/configs/bct-brettl2.h b/include/configs/bct-brettl2.h
index 5b09b45b563..06f095cc41b 100644
--- a/include/configs/bct-brettl2.h
+++ b/include/configs/bct-brettl2.h
@@ -136,7 +136,7 @@
 #define CONFIG_MTD_DEVICE
 #define CONFIG_MTD_PARTITIONS
 #define CONFIG_SYS_HUSH_PARSER
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/beaver.h b/include/configs/beaver.h
index 801caca24f1..df9a98bca6e 100644
--- a/include/configs/beaver.h
+++ b/include/configs/beaver.h
@@ -17,7 +17,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 
 #include "tegra30-common.h"
 
diff --git a/include/configs/bf518f-ezbrd.h b/include/configs/bf518f-ezbrd.h
index a97972b81ca..9eb85ebf3df 100644
--- a/include/configs/bf518f-ezbrd.h
+++ b/include/configs/bf518f-ezbrd.h
@@ -155,7 +155,7 @@
 #define CONFIG_MISC_INIT_R
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	0
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h
index 003109329a2..3065d22f0bd 100644
--- a/include/configs/bf526-ezbrd.h
+++ b/include/configs/bf526-ezbrd.h
@@ -153,6 +153,7 @@
 #define CONFIG_MISC_INIT_R
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	1
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /* define to enable run status via led */
 /* #define CONFIG_STATUS_LED */
diff --git a/include/configs/bf527-ad7160-eval.h b/include/configs/bf527-ad7160-eval.h
index fa05103e5aa..c0dfe2685bf 100644
--- a/include/configs/bf527-ad7160-eval.h
+++ b/include/configs/bf527-ad7160-eval.h
@@ -136,7 +136,7 @@
  */
 #define CONFIG_MISC_INIT_R
 #define CONFIG_UART_CONSOLE	0
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h
index db1b6136f3a..748ddb3b157 100644
--- a/include/configs/bf527-ezkit.h
+++ b/include/configs/bf527-ezkit.h
@@ -179,7 +179,7 @@
 #define CONFIG_MISC_INIT_R
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	1
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bf527-sdp.h b/include/configs/bf527-sdp.h
index c0e8b5adc88..458868af726 100644
--- a/include/configs/bf527-sdp.h
+++ b/include/configs/bf527-sdp.h
@@ -112,7 +112,7 @@
  */
 #define CONFIG_MISC_INIT_R
 #define CONFIG_UART_CONSOLE	0
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h
index beab1271a49..b50352823e7 100644
--- a/include/configs/bf533-ezkit.h
+++ b/include/configs/bf533-ezkit.h
@@ -110,7 +110,7 @@
 #define CONFIG_MISC_INIT_R
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	0
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h
index f5b96582943..d82c5b203dc 100644
--- a/include/configs/bf533-stamp.h
+++ b/include/configs/bf533-stamp.h
@@ -185,6 +185,7 @@
  */
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	0
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /* FLASH/ETHERNET uses the same async bank */
 #define SHARED_RESOURCES 	1
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
index 02945bee798..e1705cadaee 100644
--- a/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h
@@ -254,6 +254,7 @@
 #define CONFIG_MISC_INIT_R
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	0
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /* Define if want to do post memory test */
 #undef CONFIG_POST
diff --git a/include/configs/bf538f-ezkit.h b/include/configs/bf538f-ezkit.h
index ffb0caf9476..742c299d23a 100644
--- a/include/configs/bf538f-ezkit.h
+++ b/include/configs/bf538f-ezkit.h
@@ -134,7 +134,7 @@
  */
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	0
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h
index da5f0294351..1a245a2b818 100644
--- a/include/configs/bf548-ezkit.h
+++ b/include/configs/bf548-ezkit.h
@@ -181,6 +181,7 @@
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	1
 #define CONFIG_BFIN_SPI_IMG_SIZE 0x50000
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 #define CONFIG_ADI_GPIO2
 
diff --git a/include/configs/bf561-acvilon.h b/include/configs/bf561-acvilon.h
index 15ca1af2305..3db917e37bc 100644
--- a/include/configs/bf561-acvilon.h
+++ b/include/configs/bf561-acvilon.h
@@ -160,7 +160,7 @@
 #define CONFIG_UART_CONSOLE			0
 #define CONFIG_BAUDRATE				57600
 #define CONFIG_SYS_PROMPT "Acvilon> "
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h
index fb6f94873af..0a309d92694 100644
--- a/include/configs/bf561-ezkit.h
+++ b/include/configs/bf561-ezkit.h
@@ -102,6 +102,7 @@
  * Misc Settings
  */
 #define CONFIG_UART_CONSOLE	0
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Run core 1 from L1 SRAM start address when init uboot on core 0
diff --git a/include/configs/br4.h b/include/configs/br4.h
index ef3752dcd53..f8d3158d475 100644
--- a/include/configs/br4.h
+++ b/include/configs/br4.h
@@ -135,7 +135,7 @@
 #define CONFIG_BOOTCOMMAND	"run nandboot"
 #define CONFIG_BOOTDELAY	2
 #define CONFIG_LOADADDR		0x2000000
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h
index 7bbe5964ae8..7adc8c0fd79 100644
--- a/include/configs/bur_am335x_common.h
+++ b/include/configs/bur_am335x_common.h
@@ -22,7 +22,7 @@
 /* Timer information */
 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
 #define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
-
+#define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC	/* enable 32kHz OSC at bootime */
 #define CONFIG_SPL_POWER_SUPPORT
 #define CONFIG_POWER_TPS65217
 
diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
index 620a0f5c571..8eeb15c0e10 100644
--- a/include/configs/canyonlands.h
+++ b/include/configs/canyonlands.h
@@ -125,78 +125,9 @@
 /*
  * Define here the location of the environment variables (FLASH).
  */
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define	CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
 #define CONFIG_SYS_NOR_CS		0	/* NOR chip connected to CSx */
 #define CONFIG_SYS_NAND_CS		3	/* NAND chip connected to CSx */
-#else
-#define	CONFIG_ENV_IS_IN_NAND	1	/* use NAND for environment vars  */
-#define CONFIG_SYS_NOR_CS		3	/* NOR chip connected to CSx */
-#define CONFIG_SYS_NAND_CS		0	/* NAND chip connected to CSx */
-#define CONFIG_ENV_IS_EMBEDDED	1	/* use embedded environment */
-#endif
-
-/*
- * IPL (Initial Program Loader, integrated inside CPU)
- * Will load first 4k from NAND (SPL) into cache and execute it from there.
- *
- * SPL (Secondary Program Loader)
- * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
- * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
- * controller and the NAND controller so that the special U-Boot image can be
- * loaded from NAND to SDRAM.
- *
- * NUB (NAND U-Boot)
- * This NAND U-Boot (NUB) is a special U-Boot version which can be started
- * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
- *
- * On 440EPx the SPL is copied to SDRAM before the NAND controller is
- * set up. While still running from cache, I experienced problems accessing
- * the NAND controller.	sr - 2006-08-25
- *
- * This is the first official implementation of booting from 2k page sized
- * NAND devices (e.g. Micron 29F2G08AA 256Mbit * 8)
- */
-#define CONFIG_SYS_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location		      */
-#define CONFIG_SYS_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size		      */
-#define CONFIG_SYS_NAND_BOOT_SPL_DST	(CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here  */
-#define CONFIG_SYS_NAND_U_BOOT_DST	0x01000000	/* Load NUB to this addr      */
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST	/* Start NUB from     */
-							/*   this addr	      */
-#define CONFIG_SYS_NAND_BOOT_SPL_DELTA	(CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
-
-/*
- * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
- */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	(128 << 10)	/* Offset to RAM U-Boot image */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(1 << 20)	/* Size of RAM U-Boot image   */
-
-/*
- * Now the NAND chip has to be defined (no autodetection used!)
- */
-#define CONFIG_SYS_NAND_PAGE_SIZE	(2 << 10)	/* NAND chip page size	      */
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 << 10)	/* NAND chip block size	      */
-#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE)
-						/* NAND chip page count	      */
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0		/* Location of bad block marker*/
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE			/* Fifth addr used (<=128MB)  */
-
-#define CONFIG_SYS_NAND_ECCSIZE	256
-#define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_SYS_NAND_OOBSIZE	64
-#define CONFIG_SYS_NAND_ECCPOS		{40, 41, 42, 43, 44, 45, 46, 47, \
-				 48, 49, 50, 51, 52, 53, 54, 55, \
-				 56, 57, 58, 59, 60, 61, 62, 63}
-
-#ifdef CONFIG_ENV_IS_IN_NAND
-/*
- * For NAND booting the environment is embedded in the U-Boot image. Please take
- * look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
- */
-#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET		(CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#endif
 
 /*-----------------------------------------------------------------------
  * FLASH related
@@ -235,7 +166,6 @@
 /*------------------------------------------------------------------------------
  * DDR SDRAM
  *----------------------------------------------------------------------------*/
-#if !defined(CONFIG_NAND_U_BOOT)
 #if !defined(CONFIG_ARCHES)
 /*
  * NAND booting U-Boot version uses a fixed initialization, since the whole
@@ -308,7 +238,6 @@
 #define CONFIG_SYS_SDRAM0_MMODE		0x00000432
 #define CONFIG_SYS_SDRAM0_MEMODE	0x00000004
 #endif	/* !defined(CONFIG_ARCHES) */
-#endif	/* !defined(CONFIG_NAND_U_BOOT) */
 
 #define CONFIG_SYS_MBYTES_SDRAM	512	/* 512MB			*/
 
@@ -421,7 +350,6 @@
 	CONFIG_AMCC_DEF_ENV						\
 	CONFIG_AMCC_DEF_ENV_POWERPC					\
 	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
-	CONFIG_AMCC_DEF_ENV_NAND_UPD					\
 	"kernel_addr=fc000000\0"					\
 	"fdt_addr=fc1e0000\0"						\
 	"ramdisk_addr=fc200000\0"					\
@@ -556,15 +484,6 @@
  * 0xfe00.0000 -> 4.ce00.0000
  */
 
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
-/* Memory Bank 3 (NOR-FLASH) initialization					*/
-#define CONFIG_SYS_EBC_PB3AP		0x10055e00
-#define CONFIG_SYS_EBC_PB3CR		(CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
-
-/* Memory Bank 0 (NAND-FLASH) initialization						*/
-#define CONFIG_SYS_EBC_PB0AP		0x018003c0
-#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
-#else
 /* Memory Bank 0 (NOR-FLASH) initialization					*/
 #define CONFIG_SYS_EBC_PB0AP		0x10055e00
 #define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
@@ -574,7 +493,6 @@
 #define CONFIG_SYS_EBC_PB3AP		0x018003c0
 #define CONFIG_SYS_EBC_PB3CR		(CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
 #endif
-#endif	/*defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
 
 #if !defined(CONFIG_ARCHES)
 /* Memory Bank 2 (CPLD) initialization						*/
diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h
index e80d1a6fa3a..e15b52737b2 100644
--- a/include/configs/cardhu.h
+++ b/include/configs/cardhu.h
@@ -17,7 +17,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 
 #include "tegra30-common.h"
 
diff --git a/include/configs/cm-bf527.h b/include/configs/cm-bf527.h
index b15a1eb7a2e..384d8715adc 100644
--- a/include/configs/cm-bf527.h
+++ b/include/configs/cm-bf527.h
@@ -128,7 +128,7 @@
 #define FLASHBOOT_ENV_SETTINGS \
 	"flashboot=flread 20040000 1000000 300000;" \
 	"bootm 0x1000000\0"
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/cm-bf533.h b/include/configs/cm-bf533.h
index e2b954c0633..8bd499a7d2c 100644
--- a/include/configs/cm-bf533.h
+++ b/include/configs/cm-bf533.h
@@ -97,7 +97,7 @@
 #define CONFIG_UART_CONSOLE	0
 #define CONFIG_BOOTCOMMAND	"run flashboot"
 #define FLASHBOOT_ENV_SETTINGS	"flashboot=bootm 0x20040000\0"
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h
index 2838012e205..67cf801a3fe 100644
--- a/include/configs/cm-bf537e.h
+++ b/include/configs/cm-bf537e.h
@@ -146,6 +146,7 @@
 	"flashboot=flread 20040000 1000000 3c0000;" \
 	"bootm 0x1000000\0"
 #define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024))
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h
index da4cc6718d8..34ce75baebd 100644
--- a/include/configs/cm-bf537u.h
+++ b/include/configs/cm-bf537u.h
@@ -143,7 +143,7 @@
 	"flashboot=flread 20040000 1000000 300000;" \
 	"bootm 0x1000000\0"
 #define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024))
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/cm-bf548.h b/include/configs/cm-bf548.h
index 7f27eda416d..346e27f3ebd 100644
--- a/include/configs/cm-bf548.h
+++ b/include/configs/cm-bf548.h
@@ -117,6 +117,7 @@
 #define CONFIG_UART_CONSOLE	1
 #define CONFIG_BOOTCOMMAND	"run flashboot"
 #define FLASHBOOT_ENV_SETTINGS	"flashboot=bootm 0x20040000\0"
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 #define CONFIG_ADI_GPIO2
 
diff --git a/include/configs/cm-bf561.h b/include/configs/cm-bf561.h
index 93e3c8677e6..5265e5f6ef0 100644
--- a/include/configs/cm-bf561.h
+++ b/include/configs/cm-bf561.h
@@ -99,7 +99,7 @@
 #define CONFIG_UART_CONSOLE	0
 #define CONFIG_BOOTCOMMAND	"run flashboot"
 #define FLASHBOOT_ENV_SETTINGS	"flashboot=bootm 0x20040000\0"
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index 08c67f588c1..aae05e03330 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -156,10 +156,10 @@
 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
 							/* to access nand at */
 							/* CS0 */
-#define GPMC_NAND_ECC_LP_x8_LAYOUT
-
 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
 							/* devices */
+#define GPMC_NAND_ECC_LP_x8_LAYOUT
+
 /* Environment information */
 #define CONFIG_BOOTDELAY		3
 #define CONFIG_ZERO_BOOTDELAY_CHECK
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 72432e4bde5..1e4bfc49fc9 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -15,19 +15,15 @@
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
 #define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
-#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
 #if defined(CONFIG_P3041DS)
-#define CONFIG_SYS_FSL_PBL_RCW \
-			$(SRCTREE)/board/freescale/corenet_ds/rcw_p3041ds.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg
 #elif defined(CONFIG_P4080DS)
-#define CONFIG_SYS_FSL_PBL_RCW \
-			$(SRCTREE)/board/freescale/corenet_ds/rcw_p4080ds.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg
 #elif defined(CONFIG_P5020DS)
-#define CONFIG_SYS_FSL_PBL_RCW \
-			$(SRCTREE)/board/freescale/corenet_ds/rcw_p5020ds.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg
 #elif defined(CONFIG_P5040DS)
-#define CONFIG_SYS_FSL_PBL_RCW \
-			$(SRCTREE)/board/freescale/corenet_ds/rcw_p5040ds.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg
 #endif
 #endif
 
diff --git a/include/configs/cpuat91.h b/include/configs/cpuat91.h
index 49cfabdc6bd..ce521012f22 100644
--- a/include/configs/cpuat91.h
+++ b/include/configs/cpuat91.h
@@ -10,7 +10,7 @@
 #ifndef _CONFIG_CPUAT91_H
 #define _CONFIG_CPUAT91_H
 
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 
 #ifdef CONFIG_RAMBOOT
 #define CONFIG_SKIP_LOWLEVEL_INIT
diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h
index bdf012b2b8e..fd774a3314f 100644
--- a/include/configs/dalmore.h
+++ b/include/configs/dalmore.h
@@ -17,7 +17,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 
 #include "tegra114-common.h"
 
diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h
index da4ff8e61d7..e0bf3dc61e6 100644
--- a/include/configs/dbau1x00.h
+++ b/include/configs/dbau1x00.h
@@ -12,7 +12,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_MIPS32		1  /* MIPS32 CPU core	*/
 #define CONFIG_DBAU1X00		1
 #define CONFIG_SOC_AU1X00	1  /* alchemy series cpu */
 
diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h
index 3d39b106584..bd96a7d3f45 100644
--- a/include/configs/devkit3250.h
+++ b/include/configs/devkit3250.h
@@ -10,7 +10,7 @@
 #define __CONFIG_DEVKIT3250_H__
 
 /* SoC and board defines */
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 #include <asm/arch/cpu.h>
 
 /*
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index 4f43ba98822..16a00ebe867 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -116,8 +116,6 @@
 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
 							/* to access nand at */
 							/* CS0 */
-#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
-
 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
 							/* devices */
 #define CONFIG_JFFS2_NAND
diff --git a/include/configs/dig297.h b/include/configs/dig297.h
index 5049afca7a7..af6f56bb348 100644
--- a/include/configs/dig297.h
+++ b/include/configs/dig297.h
@@ -143,8 +143,6 @@
 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
 							/* to access nand at */
 							/* CS0 */
-#define GPMC_NAND_ECC_LP_x16_LAYOUT
-
 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
 
 #if defined(CONFIG_CMD_NET)
diff --git a/include/configs/ep8260.h b/include/configs/ep8260.h
index 56b4ecf272d..9cd3054a15f 100644
--- a/include/configs/ep8260.h
+++ b/include/configs/ep8260.h
@@ -325,7 +325,6 @@
  *
  *****************************************************************************/
 
-#define CONFIG_MPC8260          1       /* This is an MPC8260 CPU   */
 #define CONFIG_EP8260           11      /* on an Embedded Planet EP8260 Board, Rev. 11 */
 
 #define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h
index 18e4dafc5c3..cf31f0f1417 100644
--- a/include/configs/ep82xxm.h
+++ b/include/configs/ep82xxm.h
@@ -9,7 +9,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_MPC8260
 #define CPU_ID_STR		"MPC8270"
 
 #define CONFIG_EP82XXM	/* Embedded Planet EP82xxM H 1.0 board */
diff --git a/include/configs/exynos4-dt.h b/include/configs/exynos4-dt.h
new file mode 100644
index 00000000000..2040bf7784d
--- /dev/null
+++ b/include/configs/exynos4-dt.h
@@ -0,0 +1,138 @@
+/*
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG EXYNOS5 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_SAMSUNG			/* in a SAMSUNG core */
+#define CONFIG_S5P			/* S5P Family */
+#define CONFIG_EXYNOS4			/* which is in a Exynos4 Family */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_COMMON
+
+/* Enable fdt support */
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
+/* input clock of PLL: EXYNOS4 boards have 24MHz input clock */
+#define CONFIG_SYS_CLK_FREQ		24000000
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_EDITING
+
+#include <linux/sizes.h>
+
+/* SD/MMC configuration */
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_S5P_SDHCI
+#define CONFIG_SDHCI
+#define CONFIG_MMC_SDMA
+#define CONFIG_MMC_DEFAULT_DEV	0
+
+/* PWM */
+#define CONFIG_PWM
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Command definition*/
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_MISC
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_XIMG
+#undef CONFIG_CMD_CACHE
+#undef CONFIG_CMD_ONENAND
+#undef CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_DFU
+#define CONFIG_CMD_GPT
+#define CONFIG_CMD_PMIC
+#define CONFIG_CMD_SETEXPR
+
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+/* FAT */
+#define CONFIG_CMD_FAT
+#define CONFIG_FAT_WRITE
+
+/* EXT4 */
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+
+/* USB Composite download gadget - g_dnl */
+#define CONFIG_USBDOWNLOAD_GADGET
+
+/* TIZEN THOR downloader support */
+#define CONFIG_CMD_THOR_DOWNLOAD
+#define CONFIG_THOR_FUNCTION
+
+#define CONFIG_DFU_FUNCTION
+#define CONFIG_DFU_MMC
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
+#define DFU_DEFAULT_POLL_TIMEOUT 300
+
+/* USB Samsung's IDs */
+#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
+#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
+#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
+#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D
+#define CONFIG_G_DNL_MANUFACTURER "Samsung"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		384	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_CMD_PART
+#define CONFIG_PARTITION_UUIDS
+
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_S3C_UDC_OTG
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW	2
+#define CONFIG_USB_CABLE_CHECK
+
+#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USB_GADGET_MASS_STORAGE
+
+/* Enable devicetree support */
+#define CONFIG_OF_LIBFDT
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h
index 615df64dc17..b7ff47236b7 100644
--- a/include/configs/exynos5250-dt.h
+++ b/include/configs/exynos5250-dt.h
@@ -51,6 +51,7 @@
 #define CONFIG_CMD_SOUND
 #ifdef CONFIG_CMD_SOUND
 #define CONFIG_SOUND
+#define CONFIG_I2S_SAMSUNG
 #define CONFIG_I2S
 #define CONFIG_SOUND_MAX98095
 #define CONFIG_SOUND_WM8994
diff --git a/include/configs/gw8260.h b/include/configs/gw8260.h
index 3416fe3cec4..262c9e9e9aa 100644
--- a/include/configs/gw8260.h
+++ b/include/configs/gw8260.h
@@ -325,7 +325,6 @@
  *
  *****************************************************************************/
 
-#define CONFIG_MPC8260      1   /* This is an MPC8260 CPU   */
 #define CONFIG_GW8260       1   /* on an GW8260 Board  */
 #define CONFIG_CPM2		1	/* Has a CPM2 */
 
diff --git a/include/configs/harmony.h b/include/configs/harmony.h
index d733be9cd5b..3ec0e418c1e 100644
--- a/include/configs/harmony.h
+++ b/include/configs/harmony.h
@@ -8,7 +8,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 #include "tegra20-common.h"
 
 /* Enable fdt support for Harmony. Flash the image in u-boot-dtb.bin */
@@ -61,8 +61,9 @@
 
 /* USB networking support */
 #define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_SMSC95XX
 #define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
+#define CONFIG_USB_ETHER_SMSC95XX
 
 /* General networking support */
 #define CONFIG_CMD_NET
diff --git a/include/configs/hummingboard.h b/include/configs/hummingboard.h
index 6bf3408dd00..28955233449 100644
--- a/include/configs/hummingboard.h
+++ b/include/configs/hummingboard.h
@@ -14,7 +14,7 @@
 #include "mx6_common.h"
 #include <asm/arch/imx-regs.h>
 #include <asm/imx-common/gpio.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 
 #define CONFIG_MX6
 #define CONFIG_DISPLAY_CPUINFO
diff --git a/include/configs/hymod.h b/include/configs/hymod.h
index cc250649eab..c973365e12c 100644
--- a/include/configs/hymod.h
+++ b/include/configs/hymod.h
@@ -17,7 +17,6 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU	*/
 #define CONFIG_HYMOD		1	/* ...on a Hymod board		*/
 #define CONFIG_CPM2		1	/* Has a CPM2 */
 
diff --git a/include/configs/idmr.h b/include/configs/idmr.h
deleted file mode 100644
index b882cf06992..00000000000
--- a/include/configs/idmr.h
+++ /dev/null
@@ -1,240 +0,0 @@
-/*
- * Configuration settings for the iDMR board
- *
- * Based on MC5272C3, r5200  and M5271EVB board configs
- * (C) Copyright 2006 Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * (C) Copyright 2006 Lab X Technologies <zachary.landau@labxtechnologies.com>
- * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _IDMR_H
-#define _IDMR_H
-
-
-/*
- * High Level Configuration Options (easy to change)
- */
-
-#define CONFIG_MCF52x2		/* define processor family */
-#define CONFIG_M5271		/* define processor type */
-#define CONFIG_IDMR		/* define board type */
-
-#undef CONFIG_WATCHDOG		/* disable watchdog */
-
-/*
- * Default environment settings
- */
-#define CONFIG_BOOTCOMMAND	"run net_nfs"
-#define CONFIG_BOOTDELAY	5
-#define CONFIG_MCFUART
-#define CONFIG_SYS_UART_PORT		(0)
-#define CONFIG_BAUDRATE		19200
-#define CONFIG_ETHADDR		00:06:3b:01:41:55
-#define CONFIG_ETHPRIME
-#define CONFIG_IPADDR		192.168.30.1
-#define CONFIG_SERVERIP		192.168.1.1
-#define CONFIG_ROOTPATH		""
-#define CONFIG_GATEWAYIP	192.168.1.1
-#define CONFIG_NETMASK		255.255.0.0
-#define CONFIG_HOSTNAME		idmr
-#define CONFIG_BOOTFILE		"/tftpboot/idmr/uImage"
-#define CONFIG_PREBOOT		"echo;echo Type \\\"run flash_nfs\\\" to mount root " \
-				"filesystem over NFS; echo"
-
-#define CONFIG_MCFTMR
-
-#define CONFIG_EXTRA_ENV_SETTINGS					\
-	"netdev=eth0\0"							\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs $(bootargs) "				\
-		"ip=$(ipaddr):$(serverip):$(gatewayip):"		\
-		"$(netmask):$(hostname):$(netdev):off panic=1\0"	\
-	"flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0"		\
-	"flash_self=run ramargs addip;bootm $(kernel_addr) "		\
-		"$(ramdisk_addr)\0"					\
-	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=$(serverip):$(rootpath)\0"			\
-	"ethact=FEC\0	"						\
-	"update=prot off ff800000 ff81ffff; era ff800000 ff81ffff; "	\
-		"cp.b 200000 ff800000 $(filesize);"			\
-		"prot on ff800000 ff81ffff\0"				\
-	"load=tftp 200000 $(u-boot)\0"					\
-	"u-boot=/tftpboot/idmr/u-boot.bin\0"				\
-	""
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_NET
-
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_LOADB
-
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*
- * Configuration for environment, which occupies third sector in flash.
- */
-#ifndef CONFIG_MONITOR_IS_IN_RAM
-#define CONFIG_ENV_ADDR		0xff820000
-#define CONFIG_ENV_SECT_SIZE	0x10000
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_IS_IN_FLASH
-#else /* CONFIG_MONITOR_IS_IN_RAM */
-#define CONFIG_ENV_OFFSET		0x4000
-#define CONFIG_ENV_SECT_SIZE	0x2000
-#define CONFIG_ENV_IS_IN_FLASH
-#endif /* !CONFIG_MONITOR_IS_IN_RAM */
-
-#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
-
-#define CONFIG_SYS_LONGHELP				/* undef to save memory */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size */
-#endif
-
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_LOAD_ADDR		0x00100000
-
-#define CONFIG_SYS_MEMTEST_START	0x400
-#define CONFIG_SYS_MEMTEST_END		0x380000
-
-#define CONFIG_SYS_HZ			(50000000 / 64)
-#define CONFIG_SYS_CLK			100000000
-
-#define CONFIG_SYS_MBAR		0x40000000	/* Register Base Addrs */
-
-/*
- * Ethernet
- */
-#define CONFIG_MCFFEC
-#ifdef CONFIG_MCFFEC
-#	define CONFIG_MII		1
-#	define CONFIG_MII_INIT		1
-#	define CONFIG_SYS_DISCOVER_PHY
-#	define CONFIG_SYS_RX_ETH_BUFFER	8
-#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-
-#	define CONFIG_SYS_FEC0_PINMUX		0
-#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
-#	define MCFFEC_TOUT_LOOP		50000
-/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
-#	ifndef CONFIG_SYS_DISCOVER_PHY
-#		define FECDUPLEX	FULL
-#		define FECSPEED		_100BASET
-#	else
-#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-#		endif
-#	endif			/* CONFIG_SYS_DISCOVER_PHY */
-#endif
-
-/*
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
-#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_SDRAM_SIZE		16		/* SDRAM size in MB */
-#define CONFIG_SYS_FLASH_BASE		0xff800000
-
-#ifdef CONFIG_MONITOR_IS_IN_RAM
-#define CONFIG_SYS_MONITOR_BASE	0x20000
-#else /* !CONFIG_MONITOR_IS_IN_RAM */
-#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
-#endif /* CONFIG_MONITOR_IS_IN_RAM */
-
-#define CONFIG_SYS_MONITOR_LEN		0x20000
-#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
-#define CONFIG_SYS_BOOTPARAMS_LEN	(64*1024)
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization ??
- */
-#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
-
-/* FLASH organization */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	1000
-
-#define CONFIG_SYS_FLASH_SIZE		0x800000
-/*
- * #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
- */
-
-/* Cache Configuration */
-#define CONFIG_SYS_CACHELINE_SIZE	16
-
-#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
-#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
-					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
-					 CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
-					 CF_CACR_DISD | CF_CACR_INVI | \
-					 CF_CACR_CEIB | CF_CACR_DCM | \
-					 CF_CACR_EUSP)
-
-/* Port configuration */
-#define CONFIG_SYS_FECI2C		0xF0
-
-
-/* Dynamic MTD partition support */
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
-#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT		"nor0=idmr-0"
-
-#define MTDPARTS_DEFAULT	"mtdparts=idmr-0:128k(u-boot),"	\
-						"64k(env),"	\
-						"640k(kernel),"	\
-						"2m(rootfs),"	\
-						"-(user)";
-
-#if defined(CONFIG_CMD_MII)
-#error "MII commands don't work on iDMR board and should not be enabled."
-#endif
-
-#endif /* _IDMR_H */
diff --git a/include/configs/incaip.h b/include/configs/incaip.h
index 7d2715d094b..e11d1843b9b 100644
--- a/include/configs/incaip.h
+++ b/include/configs/incaip.h
@@ -12,7 +12,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_MIPS32		1	/* MIPS 4Kc CPU core	*/
 #define CONFIG_INCA_IP		1	/* on a INCA-IP Board	*/
 
 #define CONFIG_XWAY_SWAP_BYTES
diff --git a/include/configs/ip04.h b/include/configs/ip04.h
index d36ae43664e..0efa2b7b9f2 100644
--- a/include/configs/ip04.h
+++ b/include/configs/ip04.h
@@ -132,6 +132,7 @@
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_MISC_INIT_R	/* needed for MAC address */
 #define CONFIG_UART_CONSOLE	0
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 #undef CONFIG_SHOW_BOOT_PROGRESS
 /* Enable this if bootretry required; currently it's disabled */
diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h
index 0695d2d37b1..1990b2df150 100644
--- a/include/configs/kilauea.h
+++ b/include/configs/kilauea.h
@@ -118,12 +118,7 @@
 /*-----------------------------------------------------------------------
  * Environment
  *----------------------------------------------------------------------*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
-#else
-#define CONFIG_ENV_IS_IN_NAND	1	/* use NAND for environment vars	*/
-#define CONFIG_ENV_IS_EMBEDDED	1	/* use embedded environment */
-#endif
 
 /*-----------------------------------------------------------------------
  * FLASH related
@@ -151,61 +146,6 @@
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 #endif /* CONFIG_ENV_IS_IN_FLASH */
 
-/*
- * IPL (Initial Program Loader, integrated inside CPU)
- * Will load first 4k from NAND (SPL) into cache and execute it from there.
- *
- * SPL (Secondary Program Loader)
- * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
- * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
- * controller and the NAND controller so that the special U-Boot image can be
- * loaded from NAND to SDRAM.
- *
- * NUB (NAND U-Boot)
- * This NAND U-Boot (NUB) is a special U-Boot version which can be started
- * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
- *
- * On 405EX the SPL is copied to SDRAM before the NAND controller is
- * set up. While still running from location 0xfffff000...0xffffffff the
- * NAND controller cannot be accessed since it is attached to CS0 too.
- */
-#define CONFIG_SYS_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location			*/
-#define CONFIG_SYS_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size			*/
-#define CONFIG_SYS_NAND_BOOT_SPL_DST	0x00800000	/* Copy SPL here		*/
-#define CONFIG_SYS_NAND_U_BOOT_DST	0x01000000	/* Load NUB to this addr	*/
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr	*/
-#define CONFIG_SYS_NAND_BOOT_SPL_DELTA	(CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
-
-/*
- * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
- */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	(16 << 10)	/* Offset to RAM U-Boot image	*/
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(384 << 10)	/* Size of RAM U-Boot image	*/
-
-/*
- * Now the NAND chip has to be defined (no autodetection used!)
- */
-#define CONFIG_SYS_NAND_PAGE_SIZE	512		/* NAND chip page size		*/
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 << 10)	/* NAND chip block size		*/
-#define CONFIG_SYS_NAND_PAGE_COUNT	32		/* NAND chip page count		*/
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS	5		/* Location of bad block marker	*/
-#define CONFIG_SYS_NAND_4_ADDR_CYCLE	1		/* Fourth addr used (>32MB)	*/
-
-#define CONFIG_SYS_NAND_ECCSIZE	256
-#define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_SYS_NAND_OOBSIZE	16
-#define CONFIG_SYS_NAND_ECCPOS		{0, 1, 2, 3, 6, 7}
-
-#ifdef CONFIG_ENV_IS_IN_NAND
-/*
- * For NAND booting the environment is embedded in the U-Boot image. Please take
- * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
- */
-#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET		(CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#endif
-
 /*-----------------------------------------------------------------------
  * NAND FLASH
  *----------------------------------------------------------------------*/
@@ -230,11 +170,9 @@
  *
  * DDR Autocalibration Method_B is the default.
  */
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define	CONFIG_PPC4xx_DDR_AUTOCALIBRATION	/* IBM DDR autocalibration */
 #define	DEBUG_PPC4xx_DDR_AUTOCALIBRATION	/* dynamic DDR autocal debug */
 #undef	CONFIG_PPC4xx_DDR_METHOD_A
-#endif
 
 #define	CONFIG_SYS_SDRAM0_MB0CF_BASE	((  0 << 20) + CONFIG_SYS_SDRAM_BASE)
 
@@ -416,7 +354,6 @@
 	CONFIG_AMCC_DEF_ENV_POWERPC					\
 	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
 	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
-	CONFIG_AMCC_DEF_ENV_NAND_UPD					\
 	"logversion=2\0"						\
 	"kernel_addr=fc000000\0"					\
 	"fdt_addr=fc1e0000\0"						\
@@ -434,16 +371,7 @@
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_SNTP
 
-/*
- * Don't run the memory POST on the NAND-booting version. It will
- * overwrite part of the U-Boot image which is already loaded from NAND
- * to SDRAM.
- */
-#if defined(CONFIG_NAND_U_BOOT)
-#define CONFIG_SYS_POST_MEMORY_ON	0
-#else
 #define CONFIG_SYS_POST_MEMORY_ON	CONFIG_SYS_POST_MEMORY
-#endif
 
 /* POST support */
 #define CONFIG_POST		(CONFIG_SYS_POST_CACHE		| \
@@ -494,18 +422,6 @@
 /*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  *----------------------------------------------------------------------*/
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
-/* booting from NAND, so NAND chips select has to be on CS 0 */
-#define CONFIG_SYS_NAND_CS		0		/* NAND chip connected to CSx	*/
-
-/* Memory Bank 1 (NOR-FLASH) initialization					*/
-#define CONFIG_SYS_EBC_PB1AP		0x05806500
-#define CONFIG_SYS_EBC_PB1CR           0xFC0DA000  /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
-
-/* Memory Bank 0 (NAND-FLASH) initialization					*/
-#define CONFIG_SYS_EBC_PB0AP		0x018003c0
-#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_NAND_ADDR | 0x1e000)
-#else
 #define CONFIG_SYS_NAND_CS		1		/* NAND chip connected to CSx	*/
 
 /* Memory Bank 0 (NOR-FLASH) initialization					*/
@@ -515,7 +431,6 @@
 /* Memory Bank 1 (NAND-FLASH) initialization					*/
 #define CONFIG_SYS_EBC_PB1AP		0x018003c0
 #define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_NAND_ADDR | 0x1e000)
-#endif
 
 /* Memory Bank 2 (FPGA) initialization					*/
 #define CONFIG_SYS_EBC_PB2AP		(EBC_BXAP_BME_ENABLED |		\
diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h
index 0d24f78d423..582978afe20 100644
--- a/include/configs/km/kmp204x-common.h
+++ b/include/configs/km/kmp204x-common.h
@@ -28,8 +28,8 @@
 #define CONFIG_RAMBOOT_PBL
 #define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
 #define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
-#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/keymile/kmp204x/pbi.cfg
-#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/keymile/kmp204x/rcw_kmp204x.cfg
+#define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg
 
 /* High Level Configuration Options */
 #define CONFIG_BOOKE
diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h
index 2cde1770cdc..9eb1ad33978 100644
--- a/include/configs/km_kirkwood.h
+++ b/include/configs/km_kirkwood.h
@@ -40,8 +40,7 @@
 #define CONFIG_IDENT_STRING		"\nKeymile Kirkwood 128M16"
 #define CONFIG_HOSTNAME			km_kirkwood_128m16
 #undef CONFIG_SYS_KWD_CONFIG
-#define CONFIG_SYS_KWD_CONFIG \
-		$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
 #define CONFIG_KM_DISABLE_PCIE
 #define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
 
@@ -59,8 +58,7 @@
 #endif
 
 #undef CONFIG_SYS_KWD_CONFIG
-#define CONFIG_SYS_KWD_CONFIG \
-		$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
 #define CONFIG_KM_ENV_IS_IN_SPI_NOR
 #define CONFIG_KM_FPGA_CONFIG
 #define CONFIG_KM_PIGGY4_88E6352
@@ -73,8 +71,7 @@
 #define CONFIG_HOSTNAME			mgcoge3un
 #define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
 #undef CONFIG_SYS_KWD_CONFIG
-#define CONFIG_SYS_KWD_CONFIG \
-		$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-memphis.cfg
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-memphis.cfg
 #define CONFIG_KM_BOARD_EXTRA_ENV	"waitforne=true\0"
 #define CONFIG_PIGGY_MAC_ADRESS_OFFSET  3
 #define CONFIG_KM_DISABLE_PCIE
@@ -85,8 +82,7 @@
 #define CONFIG_IDENT_STRING		"\nKeymile COGE5UN"
 #define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
 #undef	CONFIG_SYS_KWD_CONFIG
-#define CONFIG_SYS_KWD_CONFIG \
-		$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_256M8_1.cfg
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_256M8_1.cfg
 #define CONFIG_KM_ENV_IS_IN_SPI_NOR
 #define CONFIG_PIGGY_MAC_ADRESS_OFFSET	3
 #define CONFIG_HOSTNAME			kmcoge5un
@@ -106,8 +102,7 @@
 #define CONFIG_IDENT_STRING		"\nKeymile SUV31"
 #define CONFIG_HOSTNAME			kmsuv31
 #undef CONFIG_SYS_KWD_CONFIG
-#define CONFIG_SYS_KWD_CONFIG \
-		$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
 #define CONFIG_KM_ENV_IS_IN_SPI_NOR
 #define CONFIG_KM_FPGA_CONFIG
 
diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h
index f6e79ba350b..2d2e23a2a9c 100644
--- a/include/configs/lacie_kw.h
+++ b/include/configs/lacie_kw.h
@@ -80,9 +80,9 @@
  * from the Network Space v2
  */
 #if defined(CONFIG_INETSPACE_V2)
-#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-is2.cfg
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-is2.cfg
 #elif defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
-#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-ns2l.cfg
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-ns2l.cfg
 #endif
 
 /*
diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h
index 92865df12ac..2ae8a2700d2 100644
--- a/include/configs/lsxl.h
+++ b/include/configs/lsxl.h
@@ -13,12 +13,12 @@
  */
 #if defined(CONFIG_LSCHLV2)
 #define CONFIG_IDENT_STRING " LS-CHLv2"
-#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-lschl.cfg
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lschl.cfg
 #define CONFIG_MACH_TYPE 3006
 #define CONFIG_SYS_TCLK 166666667 /* 166 MHz */
 #elif defined(CONFIG_LSXHL)
 #define CONFIG_IDENT_STRING " LS-XHL"
-#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-lsxhl.cfg
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lsxhl.cfg
 #define CONFIG_MACH_TYPE 2663
 /* CONFIG_SYS_TCLK is 200000000 by default */
 #else
diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h
index 7c0d3db1e33..f4014702515 100644
--- a/include/configs/m53evk.h
+++ b/include/configs/m53evk.h
@@ -185,6 +185,7 @@
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
 #define CONFIG_USB_ETHER_SMSC95XX
 #define CONFIG_MXC_USB_PORT		1
 #define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
diff --git a/include/configs/mcx.h b/include/configs/mcx.h
index 7c5c2f4d1c5..47244c00343 100644
--- a/include/configs/mcx.h
+++ b/include/configs/mcx.h
@@ -321,7 +321,6 @@
 #define PISMO1_NAND_SIZE		GPMC_SIZE_128M
 
 #define CONFIG_NAND_OMAP_GPMC
-#define GPMC_NAND_ECC_LP_x16_LAYOUT
 #define CONFIG_ENV_IS_IN_NAND
 #define SMNAND_ENV_OFFSET		0x180000 /* environment starts here */
 
diff --git a/include/configs/muas3001.h b/include/configs/muas3001.h
index 87c06389b44..7343c947ca3 100644
--- a/include/configs/muas3001.h
+++ b/include/configs/muas3001.h
@@ -13,8 +13,6 @@
  * (easy to change)
  */
 
-#define CONFIG_8260		1
-#define CONFIG_MPC8260		1
 #define CONFIG_MUAS3001		1
 
 #define	CONFIG_SYS_TEXT_BASE	0xFF000000
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index 4ca5bef9fc5..5859f360e00 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -65,6 +65,7 @@
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
 #define CONFIG_USB_ETHER_SMSC95XX
 #define CONFIG_MXC_USB_PORT	1
 #define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index 4efcebf4ff8..7a2c172d4a8 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -12,7 +12,7 @@
 #define CONFIG_MX6
 
 #include "mx6_common.h"
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index e5bdcc2c0d7..1876dbf35ad 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -10,7 +10,7 @@
 #define __CONFIG_H
 
 #include <asm/arch/imx-regs.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 #include "mx6_common.h"
 
 #define CONFIG_MX6
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index 5bac1009ef7..f7e7315a9b6 100644
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h
@@ -115,6 +115,7 @@
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
 #define CONFIG_USB_ETHER_SMSC95XX
 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET	/* For OTG port */
diff --git a/include/configs/omap1510.h b/include/configs/omap1510.h
index a578edd0d82..41f7973f2b8 100644
--- a/include/configs/omap1510.h
+++ b/include/configs/omap1510.h
@@ -10,7 +10,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 
 /*
   There are 2 sets of general I/O -->
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index c58bc91a50c..0b574215375 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -120,8 +120,9 @@
 
 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
 #define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_SMSC95XX
 #define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
+#define CONFIG_USB_ETHER_SMSC95XX
 
 /* GPIO banks */
 #define CONFIG_OMAP3_GPIO_5		/* GPIO128..159 is in GPIO bank 5 */
@@ -183,8 +184,6 @@
 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
 							/* to access nand at */
 							/* CS0 */
-#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
-
 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
 							/* devices */
 
diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h
index 43616e2b029..7f3424b4f0e 100644
--- a/include/configs/omap3_evm_common.h
+++ b/include/configs/omap3_evm_common.h
@@ -208,7 +208,6 @@
 #define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
 
 #define CONFIG_NAND_OMAP_GPMC
-#define GPMC_NAND_ECC_LP_x16_LAYOUT
 #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
 #elif defined(CONFIG_CMD_ONENAND)
 #define CONFIG_SYS_FLASH_BASE		PISMO1_ONEN_BASE
diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h
index 20fbbecdfbd..d56d5b00cc7 100644
--- a/include/configs/omap3_igep00x0.h
+++ b/include/configs/omap3_igep00x0.h
@@ -37,6 +37,11 @@
 #define CONFIG_SHOW_BOOT_PROGRESS
 #endif
 
+/* GPIO banks */
+#define CONFIG_OMAP3_GPIO_3		/* GPIO64 .. 95 is in GPIO bank 3 */
+#define CONFIG_OMAP3_GPIO_5		/* GPIO128..159 is in GPIO bank 5 */
+#define CONFIG_OMAP3_GPIO_6		/* GPIO160..191 is in GPIO bank 6 */
+
 /* USB */
 #define CONFIG_MUSB_UDC			1
 #define CONFIG_USB_OMAP3		1
@@ -154,7 +159,6 @@
 
 #ifdef CONFIG_NAND
 #define PISMO1_NAND_SIZE		GPMC_SIZE_128M /* Configure the PISMO */
-#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
 #define CONFIG_ENV_OFFSET		0x260000 /* environment starts here */
 #define CONFIG_ENV_IS_IN_NAND	        1
 #define CONFIG_ENV_SIZE			(512 << 10) /* Total Size Environment */
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
index bedd6f9cb39..0d03c75ce30 100644
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h
@@ -295,7 +295,6 @@
 
 #if defined(CONFIG_CMD_NAND)
 #define CONFIG_NAND_OMAP_GPMC
-#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
 #endif
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index e0f026269fc..007e27f9f11 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -119,8 +119,6 @@
 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
 							/* to access nand */
 							/* at CS0 */
-#define GPMC_NAND_ECC_LP_x16_LAYOUT
-
 #define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND */
 						/* devices */
 #define CONFIG_JFFS2_NAND
diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h
index eacdfaaa53b..da67787e69e 100644
--- a/include/configs/omap3_pandora.h
+++ b/include/configs/omap3_pandora.h
@@ -131,8 +131,6 @@
 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
 							/* to access nand */
 							/* at CS0 */
-#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
-
 #define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND */
 						/* devices */
 
diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h
index 6f1304dc943..a3e8a599728 100644
--- a/include/configs/omap3_sdp3430.h
+++ b/include/configs/omap3_sdp3430.h
@@ -16,7 +16,7 @@
 /* TODO: REMOVE THE FOLLOWING
  * Retained the following till size.h is removed in u-boot
  */
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 /*
  * High Level Configuration Options
  */
diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
index 1dd53fa1330..f0fa96efcb8 100644
--- a/include/configs/omap3_zoom1.h
+++ b/include/configs/omap3_zoom1.h
@@ -138,8 +138,6 @@
 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
 							/* to access nand at */
 							/* CS0 */
-#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
-
 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
 							/* devices */
 #define CONFIG_JFFS2_NAND
diff --git a/include/configs/origen.h b/include/configs/origen.h
index f46b833b531..82583382f7a 100644
--- a/include/configs/origen.h
+++ b/include/configs/origen.h
@@ -6,115 +6,71 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_ORIGEN_H
+#define __CONFIG_ORIGEN_H
+
+#include <configs/exynos4-dt.h>
+
+#define CONFIG_SYS_PROMPT		"ORIGEN # "
+
+#undef CONFIG_DEFAULT_DEVICE_TREE
+#define CONFIG_DEFAULT_DEVICE_TREE	exynos4210-origen
 
 /* High Level Configuration Options */
-#define CONFIG_SAMSUNG			1	/* SAMSUNG core */
-#define CONFIG_S5P			1	/* S5P Family */
 #define CONFIG_EXYNOS4210		1	/* which is a EXYNOS4210 SoC */
 #define CONFIG_ORIGEN			1	/* working with ORIGEN*/
 
-#include <asm/arch/cpu.h>		/* get chip and board defs */
-
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_BOARD_EARLY_INIT_F
-
 #define CONFIG_SYS_DCACHE_OFF		1
 
+/* ORIGEN has 4 bank of DRAM */
+#define CONFIG_NR_DRAM_BANKS		4
 #define CONFIG_SYS_SDRAM_BASE		0x40000000
-#define CONFIG_SYS_TEXT_BASE		0x43E00000
+#define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
+#define SDRAM_BANK_SIZE			(256 << 20)	/* 256 MB */
 
-/* input clock of PLL: ORIGEN has 24MHz input clock */
-#define CONFIG_SYS_CLK_FREQ		24000000
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x6000000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
 
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_INITRD_TAG
-#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_TEXT_BASE		0x43E00000
 
 #define CONFIG_MACH_TYPE		MACH_TYPE_ORIGEN
 
-/* Power Down Modes */
-#define S5P_CHECK_SLEEP			0x00000BAD
-#define S5P_CHECK_DIDLE			0xBAD00000
-#define S5P_CHECK_LPA			0xABAD0000
-
 /* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (80 * SZ_1M))
 
 /* select serial console configuration */
-#define CONFIG_SERIAL2			1	/* use SERIAL 2 */
+#define CONFIG_SERIAL2
 #define CONFIG_BAUDRATE			115200
-#define EXYNOS4_DEFAULT_UART_OFFSET	0x020000
 
-#define CONFIG_SKIP_LOWLEVEL_INIT
+/* Console configuration */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
 
-/* SD/MMC configuration */
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
-#define CONFIG_SDHCI
-#define CONFIG_S5P_SDHCI
+#define CONFIG_SYS_MEM_TOP_HIDE	(1 << 20)	/* ram console */
 
-/* PWM */
-#define CONFIG_PWM			1
+#define CONFIG_SYS_MONITOR_BASE	0x00000000
 
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/* Command definition*/
-#include <config_cmd_default.h>
+/* Power Down Modes */
+#define S5P_CHECK_SLEEP			0x00000BAD
+#define S5P_CHECK_DIDLE			0xBAD00000
+#define S5P_CHECK_LPA			0xABAD0000
 
 #undef CONFIG_CMD_PING
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_DHCP
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_FAT
 #undef CONFIG_CMD_NET
 #undef CONFIG_CMD_NFS
 
-#define CONFIG_BOOTDELAY		3
-#define CONFIG_ZERO_BOOTDELAY_CHECK
 /* MMC SPL */
 #define CONFIG_SPL
 #define COPY_BL2_FNPTR_ADDR	0x02020030
-
 #define CONFIG_SPL_TEXT_BASE	0x02021410
 
 #define CONFIG_BOOTCOMMAND	"fatload mmc 0 40007000 uImage; bootm 40007000"
 
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
-#define CONFIG_SYS_PROMPT		"ORIGEN # "
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size*/
-#define CONFIG_SYS_PBSIZE		384	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
-#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC2,115200n8\0"
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-/* memtest works on */
-#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x6000000)
-#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
-
-/* ORIGEN has 4 bank of DRAM */
-#define CONFIG_NR_DRAM_BANKS	4
-#define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */
-#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
-#define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
-#define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE
-
-/* FLASH and environment organization */
-#define CONFIG_SYS_NO_FLASH		1
-#undef CONFIG_CMD_IMLS
 #define CONFIG_IDENT_STRING		" for ORIGEN"
 
 #define CONFIG_CLK_1000_400_200
@@ -122,13 +78,12 @@
 /* MIU (Memory Interleaving Unit) */
 #define CONFIG_MIU_2BIT_21_7_INTERLEAVED
 
-#define CONFIG_ENV_IS_IN_MMC		1
+#define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV		0
 #define CONFIG_ENV_SIZE			(16 << 10)	/* 16 KB */
 #define RESERVE_BLOCK_SIZE		(512)
 #define BL1_SIZE			(16 << 10) /*16 K reserved for BL1*/
 #define CONFIG_ENV_OFFSET		(RESERVE_BLOCK_SIZE + BL1_SIZE)
-#define CONFIG_DOS_PARTITION		1
 
 #define CONFIG_SPL_LDSCRIPT	"board/samsung/common/exynos-uboot-spl.lds"
 #define CONFIG_SPL_MAX_FOOTPRINT	(14 * 1024)
@@ -140,7 +95,4 @@
 #define BL2_START_OFFSET	((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512)
 #define BL2_SIZE_BLOC_COUNT	(COPY_BL2_SIZE/512)
 
-/* Enable devicetree support */
-#define CONFIG_OF_LIBFDT
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/paz00.h b/include/configs/paz00.h
index 9e2686ac449..dd0abf8de6b 100644
--- a/include/configs/paz00.h
+++ b/include/configs/paz00.h
@@ -17,7 +17,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 #include "tegra20-common.h"
 
 /* Enable fdt support for Paz00. Flash the image in u-boot-dtb.bin */
diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h
index e929b23f289..f92496571ba 100644
--- a/include/configs/pb1x00.h
+++ b/include/configs/pb1x00.h
@@ -12,7 +12,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_MIPS32		1  /* MIPS32 CPU core	*/
 #define CONFIG_PB1X00		1
 #define CONFIG_SOC_AU1X00	1  /* alchemy series cpu */
 
diff --git a/include/configs/ppmc8260.h b/include/configs/ppmc8260.h
index 760dcaca4b3..5dcd9cc0d03 100644
--- a/include/configs/ppmc8260.h
+++ b/include/configs/ppmc8260.h
@@ -293,7 +293,6 @@
  *
  *****************************************************************************/
 
-#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU   */
 #define CONFIG_PPMC8260		1	/* on an Wind River PPMC8260 Board  */
 #define CONFIG_CPM2		1	/* Has a CPM2 */
 
diff --git a/include/configs/pr1.h b/include/configs/pr1.h
index 03d4269584e..e96ed4b4f28 100644
--- a/include/configs/pr1.h
+++ b/include/configs/pr1.h
@@ -135,7 +135,7 @@
 #define CONFIG_BOOTCOMMAND	"run nandboot"
 #define CONFIG_BOOTDELAY	2
 #define CONFIG_LOADADDR		0x2000000
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index dd3babb5058..98ed8bc97f1 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -12,7 +12,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_MIPS32			/* MIPS32 CPU core */
 #define CONFIG_QEMU_MIPS
 #define CONFIG_MISC_INIT_R
 
diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
index a1422fca11b..e8f5a4c9e8b 100644
--- a/include/configs/qemu-mips64.h
+++ b/include/configs/qemu-mips64.h
@@ -12,7 +12,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_MIPS64			/* MIPS64 CPU core */
 #define CONFIG_QEMU_MIPS
 #define CONFIG_MISC_INIT_R
 
diff --git a/include/configs/redwood.h b/include/configs/redwood.h
index 84d1e584a03..622b7c79e64 100644
--- a/include/configs/redwood.h
+++ b/include/configs/redwood.h
@@ -120,7 +120,6 @@
 	CONFIG_AMCC_DEF_ENV						\
 	CONFIG_AMCC_DEF_ENV_POWERPC					\
 	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
-	CONFIG_AMCC_DEF_ENV_NAND_UPD					\
 	"kernel_addr=fc000000\0"					\
 	"fdt_addr=fc1e0000\0"						\
 	"ramdisk_addr=fc200000\0"					\
diff --git a/include/configs/rpi_b.h b/include/configs/rpi_b.h
index 6306d61bb27..ed8b4dfb51d 100644
--- a/include/configs/rpi_b.h
+++ b/include/configs/rpi_b.h
@@ -17,7 +17,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 
 /* Architecture, CPU, etc.*/
 #define CONFIG_ARM1176
diff --git a/include/configs/rsdproto.h b/include/configs/rsdproto.h
index 92318c33943..06211380d41 100644
--- a/include/configs/rsdproto.h
+++ b/include/configs/rsdproto.h
@@ -19,7 +19,6 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU	*/
 #define CONFIG_RSD_PROTO	1	/* on a R&S Protocol Board      */
 #define CONFIG_CPM2		1	/* Has a CPM2 */
 
diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h
index 67921e900be..2da887109d9 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -7,78 +7,56 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_UNIVERSAL_H
+#define __CONFIG_UNIVERSAL_H
 
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_SAMSUNG		1	/* in a SAMSUNG core */
-#define CONFIG_S5P		1	/* which is in a S5P Family */
-#define CONFIG_EXYNOS4210	1	/* which is in a EXYNOS4210 */
-#define CONFIG_UNIVERSAL	1	/* working with Universal */
-#define CONFIG_TIZEN		1	/* TIZEN lib */
+#include <configs/exynos4-dt.h>
+
+#define CONFIG_SYS_PROMPT	"Universal # "	/* Monitor Command Prompt */
 
-#include <asm/arch/cpu.h>		/* get chip and board defs */
+#undef CONFIG_DEFAULT_DEVICE_TREE
+#define CONFIG_DEFAULT_DEVICE_TREE	exynos4210-universal_c210
 
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_TIZEN			/* TIZEN lib */
 
 /* Keep L2 Cache Disabled */
 #define CONFIG_SYS_L2CACHE_OFF		1
 
+/* Universal has 2 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS		2
 #define CONFIG_SYS_SDRAM_BASE		0x40000000
-#define CONFIG_SYS_TEXT_BASE		0x44800000
-
-/* input clock of PLL: Universal has 24MHz input clock at EXYNOS4210 */
-#define CONFIG_SYS_CLK_FREQ_C210	24000000
-#define CONFIG_SYS_CLK_FREQ		CONFIG_SYS_CLK_FREQ_C210
+#define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
 
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_BOARD_EARLY_INIT_F
+#define SDRAM_BANK_SIZE			(256 << 20)	/* 256 MB */
 
 /* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (80 * SZ_1M))
 
 /* select serial console configuration */
-#define CONFIG_SERIAL2		1	/* use SERIAL 2 */
-#define CONFIG_BAUDRATE		115200
-
-/* MMC */
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
-#define CONFIG_SDHCI
-#define CONFIG_S5P_SDHCI
-
-/* PWM */
-#define CONFIG_PWM			1
-
-/* It should define before config_cmd_default.h */
-#define CONFIG_SYS_NO_FLASH		1
-
-/* Command definition */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_MISC
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_XIMG
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_ONENAND
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_FAT
-
-#define CONFIG_BOOTDELAY		1
-#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_SERIAL2
+#define CONFIG_BAUDRATE			115200
+
+/* Console configuration */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+#define CONFIG_BOOTARGS			"Please use defined boot"
+#define CONFIG_BOOTCOMMAND		"run mmcboot"
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
+
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR \
+					- GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MEM_TOP_HIDE	(1 << 20)	/* ram console */
+
+#define CONFIG_SYS_MONITOR_BASE	0x00000000
+
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5000000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x4800000)
+
+#define CONFIG_SYS_TEXT_BASE		0x44800000
 
 #define CONFIG_MTD_DEVICE
 #define CONFIG_MTD_PARTITIONS
@@ -106,24 +84,21 @@
 				",100M(swap)"\
 				",-(UMS)\0"
 
-#define CONFIG_BOOTARGS		"Please use defined boot"
-#define CONFIG_BOOTCOMMAND	"run mmcboot"
-#define CONFIG_DEFAULT_CONSOLE	"console=ttySAC2,115200n8\0"
-
 #define CONFIG_ENV_UBI_MTD	" ubi.mtd=${ubiblock} ubi.mtd=4 ubi.mtd=7"
 #define CONFIG_BOOTBLOCK	"10"
 #define CONFIG_UBIBLOCK		"9"
 
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		CONFIG_MMC_DEFAULT_DEV
+#define CONFIG_ENV_SIZE			4096
+#define CONFIG_ENV_OFFSET		((32 - 4) << 10) /* 32KiB - 4KiB */
+
 #define CONFIG_ENV_UBIFS_OPTION	" rootflags=bulk_read,no_chk_data_crc "
 #define CONFIG_ENV_FLASHBOOT	CONFIG_ENV_UBI_MTD CONFIG_ENV_UBIFS_OPTION \
 				"${mtdparts}"
 
 #define CONFIG_ENV_COMMON_BOOT	"${console} ${meminfo}"
 
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-
 #define CONFIG_ENV_VARS_UBOOT_CONFIG
 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 
@@ -187,47 +162,10 @@
 	"mmcrootpart=3\0" \
 	"opts=always_resume=1"
 
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
-#define CONFIG_SYS_PROMPT	"Universal # "
-#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE	384	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-/* memtest works on */
-#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5000000)
-#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x4800000)
-
-/* Universal has 2 banks of DRAM */
-#define CONFIG_NR_DRAM_BANKS	2
-#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE	/* LDDDR2 DMC 0 */
-#define PHYS_SDRAM_1_SIZE	(256 << 20)		/* 256 MB in CS 0 */
-#define PHYS_SDRAM_2		0x50000000		/* LPDDR2 DMC 1 */
-#define PHYS_SDRAM_2_SIZE	(256 << 20)		/* 256 MB in CS 0 */
-
-#define CONFIG_SYS_MEM_TOP_HIDE		(1 << 20)	/* ram console */
-
-#define CONFIG_SYS_MONITOR_BASE		0x00000000
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
-
 #define CONFIG_USE_ONENAND_BOARD_INIT
 #define CONFIG_SAMSUNG_ONENAND
 #define CONFIG_SYS_ONENAND_BASE		0x0C000000
 
-#define CONFIG_ENV_IS_IN_MMC		1
-#define CONFIG_SYS_MMC_ENV_DEV		0
-#define CONFIG_ENV_SIZE			4096
-#define CONFIG_ENV_OFFSET		((32 - 4) << 10)/* 32KiB - 4KiB */
-
-#define CONFIG_DOS_PARTITION		1
-
-#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_SYS_CACHELINE_SIZE       32
-
 #include <asm/arch/gpio.h>
 /*
  * I2C Settings
@@ -235,6 +173,8 @@
 #define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_get(1, b, 7)
 #define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_get(1, b, 6)
 
+#define CONFIG_CMD_I2C
+
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
 #define CONFIG_SYS_I2C_SOFT_SPEED	50000
@@ -307,8 +247,10 @@ int universal_spi_read(void);
 #define CONFIG_CMD_BMP
 #define CONFIG_BMP_16BPP
 #define CONFIG_LD9040
-#define CONFIG_EXYNOS_MIPI_DSIM
 #define CONFIG_VIDEO_BMP_GZIP
 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
 
+#define LCD_XRES	480
+#define LCD_YRES	800
+
 #endif	/* __CONFIG_H */
diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h
index 3750ad2c3d5..0a694fb1bed 100644
--- a/include/configs/sacsng.h
+++ b/include/configs/sacsng.h
@@ -524,7 +524,6 @@
  *
  *****************************************************************************/
 
-#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU   */
 #define CONFIG_SACSng		1	/* munged for the SACSng */
 #define CONFIG_CPM2		1	/* Has a CPM2 */
 
diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h
new file mode 100644
index 00000000000..91cc7d8e583
--- /dev/null
+++ b/include/configs/sama5d3_xplained.h
@@ -0,0 +1,203 @@
+/*
+ * Configuration settings for the SAMA5D3 Xplained board.
+ *
+ * Copyright (C) 2014 Atmel Corporation
+ *		      Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/hardware.h>
+
+#define CONFIG_SYS_TEXT_BASE		0x26f00000
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK      32768
+#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
+#define CONFIG_SYS_HZ		        1000
+
+#define CONFIG_AT91FAMILY
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_OF_LIBFDT		/* Device Tree support */
+
+/* general purpose I/O */
+#define CONFIG_AT91_GPIO
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define CONFIG_USART_ID			ATMEL_ID_DBGU
+
+/*
+ * This needs to be defined for the OHCI code to work but it is defined as
+ * ATMEL_ID_UHPHS in the CPU specific header files.
+ */
+#define ATMEL_ID_UHP			ATMEL_ID_UHPHS
+
+/*
+ * Specify the clock enable bit in the PMC_SCER register.
+ */
+#define ATMEL_PMC_UHP			AT91SAM926x_PMC_UHP
+
+#define CONFIG_BOOTDELAY		3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* No NOR flash */
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_LOADS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_DDRCS
+#define CONFIG_SYS_SDRAM_SIZE		0x10000000
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+/* NAND flash */
+#define CONFIG_CMD_NAND
+
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+/* PMECC & PMERRLOC */
+#define CONFIG_ATMEL_NAND_HWECC
+#define CONFIG_ATMEL_NAND_HW_PMECC
+#define CONFIG_PMECC_CAP		4
+#define CONFIG_PMECC_SECTOR_SIZE	512
+#define CONFIG_CMD_NAND_TRIMFFS
+#define CONFIG_CMD_MTDPARTS
+
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#endif
+
+/* Ethernet Hardware */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_MULTI
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_MACB_SEARCH_PHY
+#define CONFIG_RGMII
+#define CONFIG_CMD_MII
+#define CONFIG_PHYLIB
+
+/* MMC */
+#define CONFIG_CMD_MMC
+
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#define CONFIG_ATMEL_MCI_8BIT
+#endif
+
+/* USB */
+#define CONFIG_CMD_USB
+
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		ATMEL_BASE_OHCI
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"SAMA5D3 Xplained"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_DOS_PARTITION
+#define CONFIG_USB_STORAGE
+#endif
+
+#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
+#define CONFIG_CMD_FAT
+#define CONFIG_FAT_WRITE
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR			0x22000000 /* load address */
+
+#if CONFIG_SYS_USE_NANDFLASH
+/* bootstrap + u-boot + env in nandflash */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0xc0000
+#define CONFIG_ENV_OFFSET_REDUND	0x100000
+#define CONFIG_ENV_SIZE			0x20000
+#define CONFIG_BOOTCOMMAND	"nand read 0x21000000 0x180000 0x80000;" \
+				"nand read 0x22000000 0x200000 0x600000;" \
+				"bootz 0x22000000 - 0x21000000"
+#elif CONFIG_SYS_USE_MMC
+/* bootstrap + u-boot + env in sd card */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET	0x2000
+#define CONFIG_ENV_SIZE		0x1000
+#define CONFIG_BOOTCOMMAND	"fatload mmc 0:1 0x21000000 at91-sama5d3_xplained.dtb; " \
+				"fatload mmc 0:1 0x22000000 zImage; " \
+				"bootz 0x22000000 - 0x21000000"
+#define CONFIG_SYS_MMC_ENV_DEV	0
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#ifdef CONFIG_SYS_USE_MMC
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0,115200 earlyprintk "				\
+	"root=/dev/mmcblk0p2 rw rootwait"
+#else
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0,115200 earlyprintk "				\
+	"mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,"		\
+	"256K(env),256k(evn_redundent),256k(spare),"			\
+	"512k(dtb),6M(kernel)ro,-(rootfs) "				\
+	"rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs"
+#endif
+
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+#endif
diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h
index c34feb5081b..516be85fe08 100644
--- a/include/configs/sama5d3xek.h
+++ b/include/configs/sama5d3xek.h
@@ -258,6 +258,8 @@
 #define CONFIG_SPL_SERIAL_SUPPORT
 
 #define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SYS_MONITOR_LEN		(512 << 10)
+
 #ifdef CONFIG_SYS_USE_MMC
 #define CONFIG_SPL_LDSCRIPT		arch/arm/cpu/at91-common/u-boot-spl.lds
 #define CONFIG_SPL_MMC_SUPPORT
@@ -267,6 +269,27 @@
 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
 #define CONFIG_SPL_FAT_SUPPORT
 #define CONFIG_SPL_LIBDISK_SUPPORT
+
+#elif CONFIG_SYS_USE_NANDFLASH
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE	0x800
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	0x20000
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0x0
+
+#elif CONFIG_SYS_USE_SERIALFLASH
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS		0
+#define CONFIG_SPL_SPI_CS		0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x8400
+
 #endif
 
 #endif
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index e77d06bcd3e..04171bdfd6c 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -20,6 +20,14 @@
 
 #define CONFIG_BOOTSTAGE
 #define CONFIG_BOOTSTAGE_REPORT
+#define CONFIG_DM
+#define CONFIG_CMD_DEMO
+#define CONFIG_CMD_DM
+#define CONFIG_DM_DEMO
+#define CONFIG_DM_DEMO_SIMPLE
+#define CONFIG_DM_DEMO_SHAPE
+#define CONFIG_DM_GPIO
+#define CONFIG_DM_TEST
 
 /* Number of bits in a C 'long' on this architecture */
 #define CONFIG_SANDBOX_BITS_PER_LONG	64
@@ -32,6 +40,7 @@
 #define CONFIG_FIT_SIGNATURE
 #define CONFIG_RSA
 #define CONFIG_CMD_FDT
+#define CONFIG_DEFAULT_DEVICE_TREE	sandbox
 
 #define CONFIG_FS_FAT
 #define CONFIG_FS_EXT4
@@ -48,7 +57,7 @@
 
 #define CONFIG_CMD_GPIO
 #define CONFIG_SANDBOX_GPIO
-#define CONFIG_SANDBOX_GPIO_COUNT	20
+#define CONFIG_SANDBOX_GPIO_COUNT	128
 
 #define CONFIG_CMD_GPT
 #define CONFIG_PARTITION_UUIDS
@@ -57,7 +66,7 @@
 /*
  * Size of malloc() pool, although we don't actually use this yet.
  */
-#define CONFIG_SYS_MALLOC_LEN		(4 << 20)	/* 4MB  */
+#define CONFIG_SYS_MALLOC_LEN		(32 << 20)	/* 32MB  */
 
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_LONGHELP			/* #undef to save memory */
@@ -71,6 +80,7 @@
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_COMMAND_HISTORY
 #define CONFIG_AUTO_COMPLETE
+#define CONFIG_BOOTDELAY	3
 
 #define CONFIG_ENV_SIZE		8192
 #define CONFIG_ENV_IS_NOWHERE
@@ -81,6 +91,8 @@
 #define CONFIG_CMD_SF_TEST
 #define CONFIG_CMD_SPI
 #define CONFIG_SPI_FLASH
+#define CONFIG_OF_SPI
+#define CONFIG_OF_SPI_FLASH
 #define CONFIG_SPI_FLASH_SANDBOX
 #define CONFIG_SPI_FLASH_STMICRO
 #define CONFIG_SPI_FLASH_WINBOND
@@ -89,7 +101,9 @@
 #define CONFIG_SYS_LOAD_ADDR		0x00000000
 #define CONFIG_SYS_MEMTEST_START	0x00100000
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x1000)
-#define CONFIG_SYS_FDT_LOAD_ADDR	0x1000000
+#define CONFIG_SYS_FDT_LOAD_ADDR	        0x100
+
+#define CONFIG_PHYSMEM
 
 /* Size of our emulated memory */
 #define CONFIG_SYS_SDRAM_BASE		0
@@ -117,13 +131,36 @@
 #define CONFIG_SHA1
 #define CONFIG_SHA256
 
+#define CONFIG_TPM_TIS_SANDBOX
+
 #define CONFIG_CMD_SANDBOX
 
 #define CONFIG_BOOTARGS ""
 
-#define CONFIG_EXTRA_ENV_SETTINGS	"stdin=serial\0" \
-					"stdout=serial\0" \
-					"stderr=serial\0"
+#define CONFIG_CROS_EC
+#define CONFIG_CMD_CROS_EC
+#define CONFIG_CROS_EC_SANDBOX
+#define CONFIG_KEYBOARD
+#define CONFIG_CROS_EC_KEYB
+#define CONFIG_ARCH_EARLY_INIT_R
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SOUND
+#define CONFIG_SOUND_SANDBOX
+#define CONFIG_CMD_SOUND
+
+#define CONFIG_SANDBOX_SDL
+#define CONFIG_LCD
+#define CONFIG_VIDEO_SANDBOX_SDL
+#define CONFIG_CMD_BMP
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define LCD_BPP			LCD_COLOR16
+
+#define CONFIG_EXTRA_ENV_SETTINGS	"stdin=serial,cros-ec-keyb\0" \
+					"stdout=serial,lcd\0" \
+					"stderr=serial,lcd\0"
 
 #define CONFIG_GZIP_COMPRESSED
 #define CONFIG_BZIP2
diff --git a/include/configs/sbc35_a9g20.h b/include/configs/sbc35_a9g20.h
index 7e16c451c37..a1b5751d095 100644
--- a/include/configs/sbc35_a9g20.h
+++ b/include/configs/sbc35_a9g20.h
@@ -12,7 +12,7 @@
 
 /* SoC type is defined in boards.cfg */
 #include <asm/hardware.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 
 #if defined(CONFIG_SYS_USE_NANDFLASH)
 #define CONFIG_ENV_IS_IN_NAND
diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
index 2a24ef3c642..fc4f976d8d3 100644
--- a/include/configs/seaboard.h
+++ b/include/configs/seaboard.h
@@ -8,7 +8,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 
 /* LP0 suspend / resume */
 #define CONFIG_TEGRA_LP0
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index 0e21ee3dc08..b6a5e6a59c9 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -97,10 +97,7 @@
 /*
  * Environment
  */
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
-#define CONFIG_ENV_IS_IN_NAND		/* use NAND for environ vars	*/
-#define CONFIG_ENV_IS_EMBEDDED		/* use embedded environment	*/
-#elif defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT)
 #define CONFIG_ENV_IS_NOWHERE		/* Store env in memory only	*/
 #define CONFIG_ENV_SIZE		(8 << 10)
 /*
@@ -149,67 +146,10 @@
 #endif /* CONFIG_CMD_FLASH */
 
 /*
- * IPL (Initial Program Loader, integrated inside CPU)
- * Will load first 4k from NAND (SPL) into cache and execute it from there.
- *
- * SPL (Secondary Program Loader)
- * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
- * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
- * controller and the NAND controller so that the special U-Boot image can be
- * loaded from NAND to SDRAM.
- *
- * NUB (NAND U-Boot)
- * This NAND U-Boot (NUB) is a special U-Boot version which can be started
- * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
- *
- * On 440EPx the SPL is copied to SDRAM before the NAND controller is
- * set up. While still running from cache, I experienced problems accessing
- * the NAND controller.	sr - 2006-08-25
- */
-#define CONFIG_SYS_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location		      */
-#define CONFIG_SYS_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size		      */
-#define CONFIG_SYS_NAND_BOOT_SPL_DST	(CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here  */
-#define CONFIG_SYS_NAND_U_BOOT_DST	0x01000000	/* Load NUB to this addr      */
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST	/* Start NUB from     */
-							/*   this addr	      */
-#define CONFIG_SYS_NAND_BOOT_SPL_DELTA	(CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
-
-/*
- * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
- */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	(16 << 10)	/* Offset to RAM U-Boot image */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(512 << 10)	/* Size of RAM U-Boot image   */
-
-/*
- * Now the NAND chip has to be defined (no autodetection used!)
- */
-#define CONFIG_SYS_NAND_PAGE_SIZE	512		/* NAND chip page size	      */
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 << 10)	/* NAND chip block size	      */
-#define CONFIG_SYS_NAND_PAGE_COUNT	32		/* NAND chip page count	      */
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS	5	      /* Location of bad block marker */
-#undef CONFIG_SYS_NAND_4_ADDR_CYCLE		      /* No fourth addr used (<=32MB) */
-
-#define CONFIG_SYS_NAND_ECCSIZE	256
-#define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_SYS_NAND_OOBSIZE	16
-#define CONFIG_SYS_NAND_ECCPOS		{0, 1, 2, 3, 6, 7}
-
-#ifdef CONFIG_ENV_IS_IN_NAND
-/*
- * For NAND booting the environment is embedded in the U-Boot image. Please take
- * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
- */
-#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET		(CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#endif
-
-/*
  * DDR SDRAM
  */
 #define CONFIG_SYS_MBYTES_SDRAM        (256)	/* 256MB			*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
-    !defined(CONFIG_SYS_RAMBOOT)
+#if !defined(CONFIG_SYS_RAMBOOT)
 #define CONFIG_DDR_DATA_EYE		/* use DDR2 optimization	*/
 #endif
 #define CONFIG_SYS_MEM_TOP_HIDE	(4 << 10) /* don't use last 4kbytes	*/
@@ -247,7 +187,6 @@
 	CONFIG_AMCC_DEF_ENV_POWERPC					\
 	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
 	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
-	CONFIG_AMCC_DEF_ENV_NAND_UPD					\
 	"kernel_addr=FC000000\0"					\
 	"ramdisk_addr=FC180000\0"					\
 	""
@@ -321,7 +260,7 @@
  * overwrite part of the U-Boot image which is already loaded from NAND
  * to SDRAM.
  */
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT)
 #define CONFIG_SYS_POST_MEMORY_ON	0
 #else
 #define CONFIG_SYS_POST_MEMORY_ON	CONFIG_SYS_POST_MEMORY
@@ -370,8 +309,7 @@
 /*
  * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
  */
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
-    !defined(CONFIG_SYS_RAMBOOT)
+#if !defined(CONFIG_SYS_RAMBOOT)
 #define CONFIG_SYS_NAND_CS		3	/* NAND chip connected to CSx	*/
 /* Memory Bank 0 (NOR-FLASH) initialization				*/
 #define CONFIG_SYS_EBC_PB0AP		0x03017200
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index 286304295d1..98b6e7206d9 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -457,7 +457,6 @@
 
 #define CONFIG_NAND_OMAP_GPMC
 #define CONFIG_NAND_OMAP_ELM
-#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
 #define CONFIG_SYS_NAND_BASE		(0x08000000)	/* physical address */
 							/* to access nand at */
 							/* CS0 */
diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h
index 94a65c4d01c..1ebee714ba3 100644
--- a/include/configs/snapper9260.h
+++ b/include/configs/snapper9260.h
@@ -13,7 +13,7 @@
 
 /* SoC type is defined in boards.cfg */
 #include <asm/hardware.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 
 #define CONFIG_SYS_TEXT_BASE		0x20000000
 
diff --git a/include/configs/stamp9g20.h b/include/configs/stamp9g20.h
index 51339b1496e..01085dc5c11 100644
--- a/include/configs/stamp9g20.h
+++ b/include/configs/stamp9g20.h
@@ -140,7 +140,10 @@
  * can enable it here if your baseboard features ethernet.
  */
 
-/* #define CONFIG_MACB */
+#define CONFIG_MACB
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
 
 #ifdef CONFIG_MACB
 # define CONFIG_RMII			/* use reduced MII inteface */
diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h
index d44b5c036de..3522c1a07a7 100644
--- a/include/configs/tam3517-common.h
+++ b/include/configs/tam3517-common.h
@@ -186,7 +186,6 @@
 #define PISMO1_NAND_SIZE		GPMC_SIZE_128M
 
 #define CONFIG_NAND_OMAP_GPMC
-#define GPMC_NAND_ECC_LP_x16_LAYOUT
 #define CONFIG_ENV_IS_IN_NAND
 #define SMNAND_ENV_OFFSET		0x180000 /* environment starts here */
 
diff --git a/include/configs/tcm-bf518.h b/include/configs/tcm-bf518.h
index 241f21051ea..1ff34d517d8 100644
--- a/include/configs/tcm-bf518.h
+++ b/include/configs/tcm-bf518.h
@@ -116,7 +116,7 @@
 #define CONFIG_UART_CONSOLE	0
 #define CONFIG_BOOTCOMMAND	"run flashboot"
 #define FLASHBOOT_ENV_SETTINGS	"flashboot=bootm 0x20040000\0"
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h
index 58bcdc8f47c..370d97ffe03 100644
--- a/include/configs/tcm-bf537.h
+++ b/include/configs/tcm-bf537.h
@@ -145,7 +145,7 @@
 	"flashboot=flread 20040000 1000000 300000;" \
 	"bootm 0x1000000\0"
 #define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024))
-
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h
index e1a3bbc6263..76dad4e88cd 100644
--- a/include/configs/tegra-common-post.h
+++ b/include/configs/tegra-common-post.h
@@ -66,27 +66,63 @@
 #define BOOT_TARGETS_DHCP ""
 #endif
 
+#if defined(CONFIG_CMD_DHCP) && defined(CONFIG_CMD_PXE)
+#define BOOTCMDS_PXE \
+	"bootcmd_pxe=" \
+		BOOTCMD_INIT_USB \
+		"dhcp; " \
+		"if pxe get; then " \
+			"pxe boot; " \
+		"fi\0"
+#define BOOT_TARGETS_PXE "pxe"
+#else
+#define BOOTCMDS_PXE ""
+#define BOOT_TARGETS_PXE ""
+#endif
+
 #define BOOTCMDS_COMMON \
 	"rootpart=1\0" \
 	\
+	"do_script_boot="                                                 \
+		"load ${devtype} ${devnum}:${rootpart} "                  \
+			"${scriptaddr} ${prefix}${script}; "              \
+		"source ${scriptaddr}\0"                                  \
+	\
 	"script_boot="                                                    \
-		"if load ${devtype} ${devnum}:${rootpart} "               \
-				"${scriptaddr} ${prefix}${script}; then " \
-			"echo ${script} found! Executing ...;"            \
-			"source ${scriptaddr};"                           \
-		"fi;\0"                                                   \
+		"for script in ${boot_scripts}; do "                      \
+			"if test -e ${devtype} ${devnum}:${rootpart} "    \
+					"${prefix}${script}; then "       \
+				"echo Found U-Boot script "               \
+					"${prefix}${script}; "            \
+				"run do_script_boot; "                    \
+				"echo SCRIPT FAILED: continuing...; "     \
+			"fi; "                                            \
+		"done\0"                                                  \
+	\
+	"do_sysboot_boot="                                                \
+		"sysboot ${devtype} ${devnum}:${rootpart} any "           \
+			"${scriptaddr} ${prefix}extlinux.conf\0"          \
+	\
+	"sysboot_boot="                                                   \
+		"if test -e ${devtype} ${devnum}:${rootpart} "            \
+				"${prefix}extlinux.conf; then "           \
+			"echo Found extlinux config "                     \
+				"${prefix}extlinux.conf; "                \
+			"run do_sysboot_boot; "                           \
+			"echo SCRIPT FAILED: continuing...; "             \
+		"fi\0"                                                    \
 	\
 	"scan_boot="                                                      \
 		"echo Scanning ${devtype} ${devnum}...; "                 \
 		"for prefix in ${boot_prefixes}; do "                     \
-			"for script in ${boot_scripts}; do "              \
-				"run script_boot; "                       \
-			"done; "                                          \
-		"done;\0"                                                 \
+			"run sysboot_boot; "                              \
+			"run script_boot; "                               \
+		"done\0"                                                  \
 	\
 	"boot_targets=" \
 		BOOT_TARGETS_MMC " " \
 		BOOT_TARGETS_USB " " \
+		BOOT_TARGETS_PXE " " \
 		BOOT_TARGETS_DHCP " " \
 		"\0" \
 	\
@@ -96,7 +132,8 @@
 	\
 	BOOTCMDS_MMC \
 	BOOTCMDS_USB \
-	BOOTCMDS_DHCP
+	BOOTCMDS_DHCP \
+	BOOTCMDS_PXE
 
 #define CONFIG_BOOTCOMMAND \
 	"set usb_need_init; " \
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index 522cd4133d7..ae786cfd7a0 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -7,7 +7,7 @@
 
 #ifndef _TEGRA_COMMON_H_
 #define _TEGRA_COMMON_H_
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 #include <linux/stringify.h>
 
 /*
@@ -29,7 +29,6 @@
 #define CONFIG_DISPLAY_BOARDINFO
 
 #define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
-#define CONFIG_OF_LIBFDT		/* enable passing of devicetree */
 
 /* Environment */
 #define CONFIG_ENV_VARS_UBOOT_CONFIG
@@ -69,33 +68,20 @@
 #undef CONFIG_CMD_NET		/* network support */
 
 /* turn on command-line edit/hist/auto */
-#define CONFIG_CMDLINE_EDITING
 #define CONFIG_COMMAND_HISTORY
-#define CONFIG_AUTO_COMPLETE
 
 /* turn on commonly used storage-related commands */
-
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
 #define CONFIG_PARTITION_UUIDS
-#define CONFIG_FS_EXT4
-#define CONFIG_FS_FAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
 #define CONFIG_CMD_PART
 
 #define CONFIG_SYS_NO_FLASH
 
 #define CONFIG_CONSOLE_MUX
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_BOOTDELAY	2		/* -1 to disable auto boot */
 
 /*
  * Miscellaneous configurable options
  */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
 #define CONFIG_SYS_PROMPT		V_PROMPT
 /*
  * Increasing the size of the IO buffer as default nfsargs size is more
@@ -133,8 +119,6 @@
 #define CONFIG_TEGRA_GPIO
 #define CONFIG_CMD_GPIO
 #define CONFIG_CMD_ENTERRCM
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_SUPPORT_RAW_INITRD
 
 /* Defines for SPL */
 #define CONFIG_SPL
@@ -151,10 +135,18 @@
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_GPIO_SUPPORT
 
+#ifdef CONFIG_SPL_BUILD
+# define CONFIG_USE_PRIVATE_LIBGCC
+#endif
+
 #define CONFIG_SYS_GENERIC_BOARD
 
 /* Misc utility code */
 #define CONFIG_BOUNCE_BUFFER
 #define CONFIG_CRC32_VERIFY
 
+#ifndef CONFIG_SPL_BUILD
+#include <config_distro_defaults.h>
+#endif
+
 #endif /* _TEGRA_COMMON_H_ */
diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h
index a4e8a5f5eb5..555c237cbf1 100644
--- a/include/configs/tegra114-common.h
+++ b/include/configs/tegra114-common.h
@@ -26,11 +26,6 @@
  */
 #define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
 
-/*
- * High Level Configuration Options
- */
-#define CONFIG_TEGRA114			/* in a NVidia Tegra114 core */
-
 /* Environment information, boards can override if required */
 #define CONFIG_LOADADDR		0x80408000	/* def. location for kernel */
 
@@ -51,6 +46,9 @@
  * scriptaddr can be pretty much anywhere that doesn't conflict with something
  *   else. Put it above BOOTMAPSZ to eliminate conflicts.
  *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
  * kernel_addr_r must be within the first 128M of RAM in order for the
  *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
  *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
@@ -68,6 +66,7 @@
  */
 #define MEM_LAYOUT_ENV_SETTINGS \
 	"scriptaddr=0x90000000\0" \
+	"pxefile_addr_r=0x90100000\0" \
 	"kernel_addr_r=0x81000000\0" \
 	"fdt_addr_r=0x82000000\0" \
 	"ramdisk_addr_r=0x82100000\0"
@@ -83,5 +82,6 @@
 /* For USB EHCI controller */
 #define CONFIG_EHCI_IS_TDI
 #define CONFIG_USB_EHCI_TXFIFO_THRESH	0x10
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
 
 #endif /* _TEGRA114_COMMON_H_ */
diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h
index 0a4541bd20e..61e50265740 100644
--- a/include/configs/tegra124-common.h
+++ b/include/configs/tegra124-common.h
@@ -18,11 +18,6 @@
  */
 #define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
 
-/*
- * High Level Configuration Options
- */
-#define CONFIG_TEGRA124			/* is an NVIDIA Tegra124 core */
-
 /* Environment information, boards can override if required */
 #define CONFIG_LOADADDR		0x80408000	/* def. location for kernel */
 
@@ -79,5 +74,6 @@
 /* For USB EHCI controller */
 #define CONFIG_EHCI_IS_TDI
 #define CONFIG_USB_EHCI_TXFIFO_THRESH	0x10
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
 
 #endif /* _TEGRA124_COMMON_H_ */
diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h
index b009a316b14..21bf9771742 100644
--- a/include/configs/tegra20-common.h
+++ b/include/configs/tegra20-common.h
@@ -24,11 +24,6 @@
  */
 #define V_NS16550_CLK		216000000	/* 216MHz (pllp_out0) */
 
-/*
- * High Level Configuration Options
- */
-#define CONFIG_TEGRA20				/* in a NVidia Tegra20 core */
-
 /* Environment information, boards can override if required */
 #define CONFIG_LOADADDR		0x00408000	/* def. location for kernel */
 
@@ -49,6 +44,9 @@
  * scriptaddr can be pretty much anywhere that doesn't conflict with something
  *   else. Put it above BOOTMAPSZ to eliminate conflicts.
  *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
  * kernel_addr_r must be within the first 128M of RAM in order for the
  *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
  *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
@@ -66,6 +64,7 @@
  */
 #define MEM_LAYOUT_ENV_SETTINGS \
 	"scriptaddr=0x10000000\0" \
+	"pxefile_addr_r=0x10100000\0" \
 	"kernel_addr_r=0x01000000\0" \
 	"fdt_addr_r=0x02000000\0" \
 	"ramdisk_addr_r=0x02100000\0"
@@ -96,6 +95,7 @@
  */
 #define CONFIG_USB_EHCI_TXFIFO_THRESH	10
 #define CONFIG_EHCI_IS_TDI
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
 
 /* Total I2C ports on Tegra20 */
 #define TEGRA_I2C_NUM_CONTROLLERS	4
diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h
index b5550d7d099..443c842240e 100644
--- a/include/configs/tegra30-common.h
+++ b/include/configs/tegra30-common.h
@@ -23,11 +23,6 @@
  */
 #define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
 
-/*
- * High Level Configuration Options
- */
-#define CONFIG_TEGRA30			/* in a NVidia Tegra30 core */
-
 /* Environment information, boards can override if required */
 #define CONFIG_LOADADDR		0x80408000	/* def. location for kernel */
 
@@ -48,6 +43,9 @@
  * scriptaddr can be pretty much anywhere that doesn't conflict with something
  *   else. Put it above BOOTMAPSZ to eliminate conflicts.
  *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
  * kernel_addr_r must be within the first 128M of RAM in order for the
  *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
  *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
@@ -65,6 +63,7 @@
  */
 #define MEM_LAYOUT_ENV_SETTINGS \
 	"scriptaddr=0x90000000\0" \
+	"pxefile_addr_r=0x90100000\0" \
 	"kernel_addr_r=0x81000000\0" \
 	"fdt_addr_r=0x82000000\0" \
 	"ramdisk_addr_r=0x82100000\0"
@@ -80,5 +79,6 @@
 /* For USB EHCI controller */
 #define CONFIG_EHCI_IS_TDI
 #define CONFIG_USB_EHCI_TXFIFO_THRESH	0x10
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
 
 #endif /* _TEGRA30_COMMON_H_ */
diff --git a/include/configs/tnetv107x_evm.h b/include/configs/tnetv107x_evm.h
index 48fcb24c4fd..162826f7d35 100644
--- a/include/configs/tnetv107x_evm.h
+++ b/include/configs/tnetv107x_evm.h
@@ -11,7 +11,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/clock.h>
 
diff --git a/include/configs/trats.h b/include/configs/trats.h
index 718107ac9f0..84c71ced466 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -7,25 +7,19 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_TRATS_H
+#define __CONFIG_TRATS_H
 
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_SAMSUNG		/* in a SAMSUNG core */
-#define CONFIG_S5P		/* which is in a S5P Family */
-#define CONFIG_EXYNOS4		/* which is in a EXYNOS4XXX */
-#define CONFIG_EXYNOS4210	/* which is in a EXYNOS4210 */
-#define CONFIG_TRATS		/* working with TRATS */
-#define CONFIG_TIZEN		/* TIZEN lib */
+#include <configs/exynos4-dt.h>
+
+#define CONFIG_SYS_PROMPT	"Trats # "	/* Monitor Command Prompt */
+
+#define CONFIG_TRATS
 
-#include <asm/arch/cpu.h>	/* get chip and board defs */
+#undef CONFIG_DEFAULT_DEVICE_TREE
+#define CONFIG_DEFAULT_DEVICE_TREE	exynos4210-trats
 
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_TIZEN			/* TIZEN lib */
 
 #define CONFIG_SYS_L2CACHE_OFF
 #ifndef CONFIG_SYS_L2CACHE_OFF
@@ -33,130 +27,93 @@
 #define CONFIG_SYS_PL310_BASE	0x10502000
 #endif
 
+/* TRATS has 4 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS		4
 #define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_TEXT_BASE		0x63300000
+#define SDRAM_BANK_SIZE			(256 << 20)	/* 256 MB */
 
-/* input clock of PLL: TRATS has 24MHz input clock at EXYNOS4210 */
-#define CONFIG_SYS_CLK_FREQ_C210	24000000
-#define CONFIG_SYS_CLK_FREQ		CONFIG_SYS_CLK_FREQ_C210
-
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_REVISION_TAG
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_BOARD_EARLY_INIT_F
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5000000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x4800000)
 
-/* MACH_TYPE_TRATS macro will be removed once added to mach-types */
-#define MACH_TYPE_TRATS			3928
-#define CONFIG_MACH_TYPE		MACH_TYPE_TRATS
+#define CONFIG_SYS_TEXT_BASE		0x63300000
 
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (80 * SZ_1M))
 
 /* select serial console configuration */
-#define CONFIG_SERIAL2			/* use SERIAL 2 */
+#define CONFIG_SERIAL2
 #define CONFIG_BAUDRATE			115200
 
-/* MMC */
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
-#define CONFIG_S5P_SDHCI
-#define CONFIG_SDHCI
-#define CONFIG_MMC_SDMA
-
-/* PWM */
-#define CONFIG_PWM
-
-/* It should define before config_cmd_default.h */
-#define CONFIG_SYS_NO_FLASH
-
-/* Command definition */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_MISC
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_XIMG
-#undef CONFIG_CMD_CACHE
-#undef CONFIG_CMD_ONENAND
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_DFU
-#define CONFIG_CMD_GPT
-#define CONFIG_CMD_SETEXPR
-
-/* FAT */
-#define CONFIG_CMD_FAT
-#define CONFIG_FAT_WRITE
-
-/* USB Composite download gadget - g_dnl */
-#define CONFIG_USBDOWNLOAD_GADGET
-
-/* TIZEN THOR downloader support */
-#define CONFIG_CMD_THOR_DOWNLOAD
-#define CONFIG_THOR_FUNCTION
-
-#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
-#define DFU_DEFAULT_POLL_TIMEOUT 300
-#define CONFIG_DFU_FUNCTION
-#define CONFIG_DFU_MMC
-
-/* USB Samsung's IDs */
-#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
-#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
-#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
-#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D
-#define CONFIG_G_DNL_MANUFACTURER "Samsung"
-
-#define CONFIG_BOOTDELAY		1
-#define CONFIG_ZERO_BOOTDELAY_CHECK
+/* Console configuration */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/* MACH_TYPE_TRATS macro will be removed once added to mach-types */
+#define MACH_TYPE_TRATS			3928
+#define CONFIG_MACH_TYPE		MACH_TYPE_TRATS
+
 #define CONFIG_BOOTARGS			"Please use defined boot"
 #define CONFIG_BOOTCOMMAND		"run mmcboot"
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
+
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR \
+					- GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MEM_TOP_HIDE	(1 << 20)	/* ram console */
+
+#define CONFIG_SYS_MONITOR_BASE	0x00000000
 
-#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC2,115200n8\0"
 #define CONFIG_BOOTBLOCK		"10"
 #define CONFIG_ENV_COMMON_BOOT		"${console} ${meminfo}"
 
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		CONFIG_MMC_DEFAULT_DEV
+#define CONFIG_ENV_SIZE			4096
+#define CONFIG_ENV_OFFSET		((32 - 4) << 10) /* 32KiB - 4KiB */
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
 /* Tizen - partitions definitions */
 #define PARTS_CSA		"csa-mmc"
-#define PARTS_BOOTLOADER	"u-boot"
 #define PARTS_BOOT		"boot"
+#define PARTS_QBOOT		"qboot"
+#define PARTS_CSC		"csc"
 #define PARTS_ROOT		"platform"
 #define PARTS_DATA		"data"
-#define PARTS_CSC		"csc"
 #define PARTS_UMS		"ums"
 
 #define PARTS_DEFAULT \
 	"uuid_disk=${uuid_gpt_disk};" \
-	"name="PARTS_CSA",size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
-	"name="PARTS_BOOTLOADER",size=60MiB," \
-		"uuid=${uuid_gpt_"PARTS_BOOTLOADER"};" \
-	"name="PARTS_BOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
-	"name="PARTS_ROOT",size=1GiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
-	"name="PARTS_DATA",size=3GiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
+	"name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
+	"name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
+	"name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \
 	"name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
+	"name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
+	"name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
 	"name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
 
 #define CONFIG_DFU_ALT \
 	"u-boot mmc 80 400;" \
 	"uImage ext4 0 2;" \
+	"modem.bin ext4 0 2;" \
 	"exynos4210-trats.dtb ext4 0 2;" \
+	""PARTS_CSA" part 0 1;" \
 	""PARTS_BOOT" part 0 2;" \
+	""PARTS_QBOOT" part 0 3;" \
+	""PARTS_CSC" part 0 4;" \
 	""PARTS_ROOT" part 0 5;" \
 	""PARTS_DATA" part 0 6;" \
 	""PARTS_UMS" part 0 7;" \
 	"params.bin mmc 0x38 0x8\0"
 
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-
-#define CONFIG_ENV_VARS_UBOOT_CONFIG
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"bootk=" \
 		"run loaduimage;" \
@@ -226,59 +183,14 @@
 		   "setenv spl_addr_tmp;\0" \
 	"fdtaddr=40800000\0" \
 
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
-#define CONFIG_SYS_PROMPT		"TRATS # "
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE		384	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-/* memtest works on */
-#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5000000)
-#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x4800000)
-
-/* TRATS has 4 banks of DRAM */
-#define CONFIG_NR_DRAM_BANKS	4
-#define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */
-#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
-#define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
-#define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE
-
-#define CONFIG_SYS_MEM_TOP_HIDE		(1 << 20)	/* ram console */
-
-#define CONFIG_SYS_MONITOR_BASE		0x00000000
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
-
-#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV		0
-#define CONFIG_ENV_SIZE			4096
-#define CONFIG_ENV_OFFSET		((32 - 4) << 10) /* 32KiB - 4KiB */
-
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-
-/* EXT4 */
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
 /* Falcon mode definitions */
 #define CONFIG_CMD_SPL
-#define CONFIG_SYS_SPL_ARGS_ADDR        PHYS_SDRAM_1 + 0x100
+#define CONFIG_SYS_SPL_ARGS_ADDR        CONFIG_SYS_SDRAM_BASE + 0x100
 
-/* GPT */
-#define CONFIG_EFI_PARTITION
-#define CONFIG_PARTITION_UUIDS
+/* I2C */
+#include <asm/arch/gpio.h>
 
-#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_CACHELINE_SIZE       32
+#define CONFIG_CMD_I2C
 
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_S3C24X0
@@ -291,12 +203,11 @@
 #define CONFIG_SOFT_I2C_READ_REPEATED_START
 #define CONFIG_SYS_I2C_INIT_BOARD
 
-#include <asm/arch/gpio.h>
-
 /* I2C FG */
 #define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_get(2, y4, 1)
 #define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_get(2, y4, 0)
 
+/* POWER */
 #define CONFIG_POWER
 #define CONFIG_POWER_I2C
 #define CONFIG_POWER_MAX8997
@@ -307,11 +218,6 @@
 #define CONFIG_POWER_MUIC_MAX8997
 #define CONFIG_POWER_BATTERY
 #define CONFIG_POWER_BATTERY_TRATS
-#define CONFIG_USB_GADGET
-#define CONFIG_USB_GADGET_S3C_UDC_OTG
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW	2
-#define CONFIG_USB_CABLE_CHECK
 
 /* Common misc for Samsung */
 #define CONFIG_MISC_COMMON
@@ -351,10 +257,7 @@
 #define CONFIG_VIDEO_BMP_GZIP
 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  ((500 * 160 * 4) + 54)
 
-#define CONFIG_CMD_USB_MASS_STORAGE
-#define CONFIG_USB_GADGET_MASS_STORAGE
-
-/* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT    1
+#define LCD_XRES	720
+#define LCD_YRES	1280
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/trats2.h b/include/configs/trats2.h
index e30c428a442..85cf4aadc54 100644
--- a/include/configs/trats2.h
+++ b/include/configs/trats2.h
@@ -8,27 +8,17 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_TRATS2_H
+#define __CONFIG_TRATS2_H
 
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_SAMSUNG		/* in a SAMSUNG core */
-#define CONFIG_S5P		/* which is in a S5P Family */
-#define CONFIG_EXYNOS4		/* which is in a EXYNOS4XXX */
-#define CONFIG_TIZEN		/* TIZEN lib */
+#include <configs/exynos4-dt.h>
 
-#include <asm/arch/cpu.h>		/* get chip and board defs */
-
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_PROMPT	"Trats2 # "	/* Monitor Command Prompt */
 
-#define CONFIG_SKIP_LOWLEVEL_INIT
+#undef CONFIG_DEFAULT_DEVICE_TREE
+#define CONFIG_DEFAULT_DEVICE_TREE	exynos4412-trats2
 
-#define CONFIG_SYS_CACHELINE_SIZE	32
+#define CONFIG_TIZEN			/* TIZEN lib */
 
 #define CONFIG_SYS_L2CACHE_OFF
 #ifndef CONFIG_SYS_L2CACHE_OFF
@@ -36,129 +26,55 @@
 #define CONFIG_SYS_PL310_BASE	0x10502000
 #endif
 
-#define CONFIG_NR_DRAM_BANKS	4
-#define PHYS_SDRAM_1		0x40000000	/* LDDDR2 DMC 0 */
-#define PHYS_SDRAM_1_SIZE	(256 << 20)	/* 256 MB in CS 0 */
-#define PHYS_SDRAM_2		0x50000000	/* LPDDR2 DMC 1 */
-#define PHYS_SDRAM_2_SIZE	(256 << 20)	/* 256 MB in CS 0 */
-#define PHYS_SDRAM_3		0x60000000	/* LPDDR2 DMC 1 */
-#define PHYS_SDRAM_3_SIZE	(256 << 20)	/* 256 MB in CS 0 */
-#define PHYS_SDRAM_4		0x70000000	/* LPDDR2 DMC 1 */
-#define PHYS_SDRAM_4_SIZE	(256 << 20)	/* 256 MB in CS 0 */
-#define PHYS_SDRAM_END		0x80000000
-
-#define CONFIG_SYS_MEM_TOP_HIDE		(1 << 20)	/* ram console */
-
-#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
-#define CONFIG_SYS_TEXT_BASE		0x78100000
-
-#define CONFIG_SYS_CLK_FREQ		24000000
-
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_REVISION_TAG
-
-/* MACH_TYPE_TRATS2 */
-#define MACH_TYPE_TRATS2		3765
-#define CONFIG_MACH_TYPE		MACH_TYPE_TRATS2
+/* TRATS2 has 4 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS		4
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
+#define SDRAM_BANK_SIZE			(256 << 20)	/* 256 MB */
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5E00000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
 
-#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_SYS_TEXT_BASE		0x43e00000
 
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (80 * SZ_1M))
 
 /* select serial console configuration */
 #define CONFIG_SERIAL2
+#define CONFIG_BAUDRATE			115200
 
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+/* Console configuration */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
 
-#define CONFIG_CMDLINE_EDITING
+#define CONFIG_BOOTARGS			"Please use defined boot"
+#define CONFIG_BOOTCOMMAND		"run mmcboot"
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
 
-#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR \
+					- GENERATED_GBL_DATA_SIZE)
 
-/* It should define before config_cmd_default.h */
-#define CONFIG_SYS_NO_FLASH
-
-/***********************************************************
- * Command definition
- ***********************************************************/
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_ECHO
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_NAND
-#undef CONFIG_CMD_MISC
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_SOURCE
-#undef CONFIG_CMD_XIMG
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_DFU
-#define CONFIG_CMD_GPT
-#define CONFIG_CMD_PMIC
-
-#define CONFIG_BOOTDELAY	3
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-#define CONFIG_CMD_FAT
-#define CONFIG_FAT_WRITE
-
-/* EXT4 */
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
-
-/* USB Composite download gadget - g_dnl */
-#define CONFIG_USBDOWNLOAD_GADGET
-#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
-#define DFU_DEFAULT_POLL_TIMEOUT 300
-#define CONFIG_DFU_FUNCTION
-#define CONFIG_DFU_MMC
-
-/* TIZEN THOR downloader support */
-#define CONFIG_CMD_THOR_DOWNLOAD
-#define CONFIG_THOR_FUNCTION
-
-/* USB Samsung's IDs */
-#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
-#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
-#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
-#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D
-#define CONFIG_G_DNL_MANUFACTURER "Samsung"
-
-/* To use the TFTPBOOT over USB, Please enable the CONFIG_CMD_NET */
-#undef CONFIG_CMD_NET
-
-/* MMC */
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
-#define CONFIG_S5P_SDHCI
-#define CONFIG_SDHCI
-#define CONFIG_MMC_SDMA
-#define CONFIG_MMC_DEFAULT_DEV	0
-
-/* PWM */
-#define CONFIG_PWM
-
-#define CONFIG_BOOTARGS		"Please use defined boot"
-#define CONFIG_BOOTCOMMAND	"run mmcboot"
-#define CONFIG_DEFAULT_CONSOLE	"console=ttySAC2,115200n8\0"
+#define CONFIG_SYS_MEM_TOP_HIDE	(1 << 20)	/* ram console */
+
+#define CONFIG_SYS_MONITOR_BASE	0x00000000
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		CONFIG_MMC_DEFAULT_DEV
+#define CONFIG_ENV_SIZE			4096
+#define CONFIG_ENV_OFFSET		((32 - 4) << 10) /* 32KiB - 4KiB */
 
 #define CONFIG_ENV_OVERWRITE
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
 
 #define CONFIG_ENV_VARS_UBOOT_CONFIG
 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 
 /* Tizen - partitions definitions */
-#define PARTS_CSA		"csa"
+#define PARTS_CSA		"csa-mmc"
 #define PARTS_BOOT		"boot"
-#define PARTS_MODEM		"modem"
+#define PARTS_QBOOT		"qboot"
 #define PARTS_CSC		"csc"
 #define PARTS_ROOT		"platform"
 #define PARTS_DATA		"data"
@@ -167,18 +83,22 @@
 #define PARTS_DEFAULT \
 	"uuid_disk=${uuid_gpt_disk};" \
 	"name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
-	"name="PARTS_BOOT",size=64MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
-	"name="PARTS_MODEM",size=100MiB,uuid=${uuid_gpt_"PARTS_MODEM"};" \
+	"name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
+	"name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \
 	"name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
 	"name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
-	"name="PARTS_DATA",size=512MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
+	"name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
 	"name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
 
 #define CONFIG_DFU_ALT \
 	"u-boot mmc 80 800;" \
 	"uImage ext4 0 2;" \
+	"modem.bin ext4 0 2;" \
 	"exynos4412-trats2.dtb ext4 0 2;" \
+	""PARTS_CSA" part 0 1;" \
 	""PARTS_BOOT" part 0 2;" \
+	""PARTS_QBOOT" part 0 3;" \
+	""PARTS_CSC" part 0 4;" \
 	""PARTS_ROOT" part 0 5;" \
 	""PARTS_DATA" part 0 6;" \
 	""PARTS_UMS" part 0 7;" \
@@ -246,49 +166,11 @@
 		   "setenv spl_addr_tmp;\0" \
 	"fdtaddr=40800000\0" \
 
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory */
-#define CONFIG_SYS_PROMPT	"Trats2 # "	/* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE	384		/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	32		/* max number of command args */
-
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-
-/* memtest works on */
-#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5000000)
-#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x4800000)
-
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_LOAD_ADDR \
-					- GENERATED_GBL_DATA_SIZE)
-
-/* valid baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-#define CONFIG_SYS_MONITOR_BASE		0x00000000
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
-
-#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV		CONFIG_MMC_DEFAULT_DEV
-#define CONFIG_ENV_SIZE			4096
-#define CONFIG_ENV_OFFSET		((32 - 4) << 10) /* 32KiB - 4KiB */
-#define CONFIG_EFI_PARTITION
-#define CONFIG_PARTITION_UUIDS
-
-#define CONFIG_BOARD_EARLY_INIT_F
-
 /* I2C */
 #include <asm/arch/gpio.h>
 
+#define CONFIG_CMD_I2C
+
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_S3C24X0
 #define CONFIG_SYS_I2C_S3C24X0_SPEED	100000
@@ -318,11 +200,6 @@ int get_soft_i2c_sda_pin(void);
 #define CONFIG_POWER_MUIC_MAX77693
 #define CONFIG_POWER_FG_MAX77693
 #define CONFIG_POWER_BATTERY_TRATS2
-#define CONFIG_USB_GADGET
-#define CONFIG_USB_GADGET_S3C_UDC_OTG
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW	2
-#define CONFIG_USB_CABLE_CHECK
 
 /* Common misc for Samsung */
 #define CONFIG_MISC_COMMON
@@ -362,10 +239,7 @@ int get_soft_i2c_sda_pin(void);
 #define CONFIG_VIDEO_BMP_GZIP
 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
 
-#define CONFIG_CMD_USB_MASS_STORAGE
-#define CONFIG_USB_GADGET_MASS_STORAGE
-
-/* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT    1
+#define LCD_XRES	720
+#define LCD_YRES	1280
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h
index cc4001fcd13..62f97d24fb4 100644
--- a/include/configs/tricorder.h
+++ b/include/configs/tricorder.h
@@ -134,8 +134,6 @@
 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
 							/* to access nand at */
 							/* CS0 */
-#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
-
 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
 							/* devices */
 #define CONFIG_BCH
diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h
index 8e03f6f4c4b..f81cfa2e354 100644
--- a/include/configs/trimslice.h
+++ b/include/configs/trimslice.h
@@ -8,7 +8,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 #include "tegra20-common.h"
 
 /* Enable fdt support for TrimSlice. Flash the image in u-boot-dtb.bin */
diff --git a/include/configs/udoo.h b/include/configs/udoo.h
index 4f518527a0f..a0306de6a33 100644
--- a/include/configs/udoo.h
+++ b/include/configs/udoo.h
@@ -12,7 +12,7 @@
 #include "mx6_common.h"
 #include <asm/arch/imx-regs.h>
 #include <asm/imx-common/gpio.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 
 #define CONFIG_MX6
 #define CONFIG_DISPLAY_CPUINFO
diff --git a/include/configs/vct.h b/include/configs/vct.h
index 99831169a3f..5ab4de32741 100644
--- a/include/configs/vct.h
+++ b/include/configs/vct.h
@@ -25,7 +25,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_MIPS32				/* MIPS 4Kc CPU core	*/
 #define CPU_CLOCK_RATE			324000000 /* Clock for the MIPS core */
 #define CONFIG_SYS_MIPS_TIMER_FREQ	(CPU_CLOCK_RATE / 2)
 
diff --git a/include/configs/venice2.h b/include/configs/venice2.h
index 91808e92038..2d75f5013fd 100644
--- a/include/configs/venice2.h
+++ b/include/configs/venice2.h
@@ -8,7 +8,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 
 #include "tegra124-common.h"
 
diff --git a/include/configs/ventana.h b/include/configs/ventana.h
index 5c02c968f90..edf3720b615 100644
--- a/include/configs/ventana.h
+++ b/include/configs/ventana.h
@@ -8,7 +8,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 #include "tegra20-common.h"
 
 /* Enable fdt support for Ventana. Flash the image in u-boot-dtb.bin */
diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index 348847238e7..6c74c729525 100644
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -12,7 +12,7 @@
 #include "mx6_common.h"
 #include <asm/arch/imx-regs.h>
 #include <asm/imx-common/gpio.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 
 #define CONFIG_MX6
 #define CONFIG_DISPLAY_CPUINFO
diff --git a/include/configs/whistler.h b/include/configs/whistler.h
index d5c7e3bbd6e..9e09f03d527 100644
--- a/include/configs/whistler.h
+++ b/include/configs/whistler.h
@@ -8,7 +8,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 #include "tegra20-common.h"
 
 /* Enable fdt support for Whistler. Flash the image in u-boot-dtb.bin */
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 14f0b90b9bc..731e69b5fd8 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -242,6 +242,7 @@
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_DCACHE_OFF
 #undef CONFIG_FPGA
+#undef CONFIG_OF_CONTROL
 #endif
 
 /* MMC support */
diff --git a/include/cros_ec.h b/include/cros_ec.h
index 1e89f29eea6..1e4d8db96b7 100644
--- a/include/cros_ec.h
+++ b/include/cros_ec.h
@@ -20,6 +20,7 @@ enum cros_ec_interface_t {
 	CROS_EC_IF_SPI,
 	CROS_EC_IF_I2C,
 	CROS_EC_IF_LPC,	/* Intel Low Pin Count interface */
+	CROS_EC_IF_SANDBOX,
 };
 
 /* Our configuration information */
@@ -33,7 +34,7 @@ struct cros_ec_dev {
 	unsigned int bus_num;		/* Bus number (for I2C) */
 	unsigned int max_frequency;	/* Maximum interface frequency */
 	struct fdt_gpio_state ec_int;	/* GPIO used as EC interrupt line */
-	int cmd_version_is_supported;   /* Device supports command versions */
+	int protocol_version;           /* Protocol version to use */
 	int optimise_flash_write;	/* Don't write erased flash blocks */
 
 	/*
@@ -63,6 +64,17 @@ struct mbkp_keyscan {
 	uint8_t data[CROS_EC_KEYSCAN_COLS];
 };
 
+/* Holds information about the Chrome EC */
+struct fdt_cros_ec {
+	struct fmap_entry flash;	/* Address and size of EC flash */
+	/*
+	 * Byte value of erased flash, or -1 if not known. It is normally
+	 * 0xff but some flash devices use 0 (e.g. STM32Lxxx)
+	 */
+	int flash_erase_value;
+	struct fmap_entry region[EC_FLASH_REGION_COUNT];
+};
+
 /**
  * Read the ID of the CROS-EC device
  *
@@ -140,7 +152,7 @@ enum {
 };
 
 /**
- * Set up the Chromium OS matrix keyboard protocol
+ * Initialise the Chromium OS EC driver
  *
  * @param blob		Device tree blob containing setup information
  * @param cros_ecp        Returns pointer to the cros_ec device, or NULL if none
@@ -157,7 +169,7 @@ int cros_ec_init(const void *blob, struct cros_ec_dev **cros_ecp);
  * @param info		Place to put the info structure
  */
 int cros_ec_info(struct cros_ec_dev *dev,
-		struct ec_response_cros_ec_info *info);
+		struct ec_response_mkbp_info *info);
 
 /**
  * Read the host event flags
@@ -226,6 +238,7 @@ struct cros_ec_dev *board_get_cros_ec_dev(void);
 int cros_ec_i2c_init(struct cros_ec_dev *dev, const void *blob);
 int cros_ec_spi_init(struct cros_ec_dev *dev, const void *blob);
 int cros_ec_lpc_init(struct cros_ec_dev *dev, const void *blob);
+int cros_ec_sandbox_init(struct cros_ec_dev *dev, const void *blob);
 
 /**
  * Read information from the fdt for the i2c cros_ec interface
@@ -246,11 +259,19 @@ int cros_ec_i2c_decode_fdt(struct cros_ec_dev *dev, const void *blob);
 int cros_ec_spi_decode_fdt(struct cros_ec_dev *dev, const void *blob);
 
 /**
+ * Read information from the fdt for the sandbox cros_ec interface
+ *
+ * @param dev		CROS-EC device
+ * @param blob		Device tree blob
+ * @return 0 if ok, -1 if we failed to read all required information
+ */
+int cros_ec_sandbox_decode_fdt(struct cros_ec_dev *dev, const void *blob);
+
+/**
  * Check whether the LPC interface supports new-style commands.
  *
  * LPC has its own way of doing this, which involves checking LPC values
- * visible to the host. Do this, and update dev->cmd_version_is_supported
- * accordingly.
+ * visible to the host. Do this, and update dev->protocol_version accordingly.
  *
  * @param dev		CROS-EC device to check
  */
@@ -302,6 +323,21 @@ int cros_ec_spi_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version,
 		     uint8_t **dinp, int din_len);
 
 /**
+ * Send a packet to a CROS-EC device and return the response packet.
+ *
+ * Expects the request packet to be stored in dev->dout.  Stores the response
+ * packet in dev->din.
+ *
+ * @param dev		CROS-EC device
+ * @param out_bytes	Size of request packet to output
+ * @param in_bytes	Maximum size of response packet to receive
+ * @return number of bytes in response packet, or <0 on error
+ */
+int cros_ec_spi_packet(struct cros_ec_dev *dev, int out_bytes, int in_bytes);
+int cros_ec_sandbox_packet(struct cros_ec_dev *dev, int out_bytes,
+			   int in_bytes);
+
+/**
  * Dump a block of data for a command.
  *
  * @param name	Name for data (e.g. 'in', 'out')
@@ -431,4 +467,52 @@ int cros_ec_set_ldo(struct cros_ec_dev *dev, uint8_t index, uint8_t state);
  * @return 0 if ok, -1 on error
  */
 int cros_ec_get_ldo(struct cros_ec_dev *dev, uint8_t index, uint8_t *state);
+
+/**
+ * Initialize the Chrome OS EC at board initialization time.
+ *
+ * @return 0 if ok, -ve on error
+ */
+int cros_ec_board_init(void);
+
+/**
+ * Get access to the error reported when cros_ec_board_init() was called
+ *
+ * This permits delayed reporting of the EC error if it failed during
+ * early init.
+ *
+ * @return error (0 if there was no error, -ve if there was an error)
+ */
+int cros_ec_get_error(void);
+
+/**
+ * Returns information from the FDT about the Chrome EC flash
+ *
+ * @param blob		FDT blob to use
+ * @param config	Structure to use to return information
+ */
+int cros_ec_decode_ec_flash(const void *blob, struct fdt_cros_ec *config);
+
+/**
+ * Check the current keyboard state, in case recovery mode is requested.
+ * This function is for sandbox only.
+ *
+ * @param ec		CROS-EC device
+ */
+void cros_ec_check_keyboard(struct cros_ec_dev *dev);
+
+/*
+ * Tunnel an I2C transfer to the EC
+ *
+ * @param dev		CROS-EC device
+ * @param chip		Chip address (7-bit I2C address)
+ * @param addr		Register address to read/write
+ * @param alen		Length of register address in bytes
+ * @param buffer	Buffer containing data to read/write
+ * @param len		Length of buffer
+ * @param is_read	1 if this is a read, 0 if this is a write
+ */
+int cros_ec_i2c_xfer(struct cros_ec_dev *dev, uchar chip, uint addr,
+		     int alen, uchar *buffer, int len, int is_read);
+
 #endif
diff --git a/include/cros_ec_message.h b/include/cros_ec_message.h
index b1da53db1b3..36e2d83ce18 100644
--- a/include/cros_ec_message.h
+++ b/include/cros_ec_message.h
@@ -23,7 +23,7 @@ enum {
 	MSG_PROTO_BYTES		= MSG_HEADER_BYTES + MSG_TRAILER_BYTES,
 
 	/* Max length of messages */
-	MSG_BYTES		= EC_HOST_PARAM_SIZE + MSG_PROTO_BYTES,
+	MSG_BYTES		= EC_PROTO2_MAX_PARAM_SIZE + MSG_PROTO_BYTES,
 };
 
 #endif
diff --git a/include/dm-demo.h b/include/dm-demo.h
new file mode 100644
index 00000000000..6e38d3c5b3a
--- /dev/null
+++ b/include/dm-demo.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DM_DEMO_H
+#define __DM_DEMO_H
+
+#include <dm.h>
+
+/**
+ * struct dm_demo_pdata - configuration data for demo instance
+ *
+ * @colour: Color of the demo
+ * @sides: Numbers of sides
+ * @default_char: Default ASCII character to output (65 = 'A')
+ */
+struct dm_demo_pdata {
+	const char *colour;
+	int sides;
+	int default_char;
+};
+
+struct demo_ops {
+	int (*hello)(struct device *dev, int ch);
+	int (*status)(struct device *dev, int *status);
+};
+
+int demo_hello(struct device *dev, int ch);
+int demo_status(struct device *dev, int *status);
+int demo_list(void);
+
+int demo_parse_dt(struct device *dev);
+
+#endif
diff --git a/include/dm.h b/include/dm.h
new file mode 100644
index 00000000000..8bbb21b575e
--- /dev/null
+++ b/include/dm.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DM_H_
+#define _DM_H
+
+#include <dm/device.h>
+#include <dm/platdata.h>
+#include <dm/uclass.h>
+
+#endif
diff --git a/include/dm/device-internal.h b/include/dm/device-internal.h
new file mode 100644
index 00000000000..c026e8e49c7
--- /dev/null
+++ b/include/dm/device-internal.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ * Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DM_DEVICE_INTERNAL_H
+#define _DM_DEVICE_INTERNAL_H
+
+struct device;
+
+/**
+ * device_bind() - Create a device and bind it to a driver
+ *
+ * Called to set up a new device attached to a driver. The device will either
+ * have platdata, or a device tree node which can be used to create the
+ * platdata.
+ *
+ * Once bound a device exists but is not yet active until device_probe() is
+ * called.
+ *
+ * @parent: Pointer to device's parent, under which this driver will exist
+ * @drv: Device's driver
+ * @name: Name of device (e.g. device tree node name)
+ * @platdata: Pointer to data for this device - the structure is device-
+ * specific but may include the device's I/O address, etc.. This is NULL for
+ * devices which use device tree.
+ * @of_offset: Offset of device tree node for this device. This is -1 for
+ * devices which don't use device tree.
+ * @devp: Returns a pointer to the bound device
+ * @return 0 if OK, -ve on error
+ */
+int device_bind(struct device *parent, struct driver *drv,
+		const char *name, void *platdata, int of_offset,
+		struct device **devp);
+
+/**
+ * device_bind_by_name: Create a device and bind it to a driver
+ *
+ * This is a helper function used to bind devices which do not use device
+ * tree.
+ *
+ * @parent: Pointer to device's parent
+ * @info: Name and platdata for this device
+ * @devp: Returns a pointer to the bound device
+ * @return 0 if OK, -ve on error
+ */
+int device_bind_by_name(struct device *parent, const struct driver_info *info,
+			struct device **devp);
+
+/**
+ * device_probe() - Probe a device, activating it
+ *
+ * Activate a device so that it is ready for use. All its parents are probed
+ * first.
+ *
+ * @dev: Pointer to device to probe
+ * @return 0 if OK, -ve on error
+ */
+int device_probe(struct device *dev);
+
+/**
+ * device_remove() - Remove a device, de-activating it
+ *
+ * De-activate a device so that it is no longer ready for use. All its
+ * children are deactivated first.
+ *
+ * @dev: Pointer to device to remove
+ * @return 0 if OK, -ve on error (an error here is normally a very bad thing)
+ */
+int device_remove(struct device *dev);
+
+/**
+ * device_unbind() - Unbind a device, destroying it
+ *
+ * Unbind a device and remove all memory used by it
+ *
+ * @dev: Pointer to device to unbind
+ * @return 0 if OK, -ve on error
+ */
+int device_unbind(struct device *dev);
+
+#endif
diff --git a/include/dm/device.h b/include/dm/device.h
new file mode 100644
index 00000000000..4cd38ed2d03
--- /dev/null
+++ b/include/dm/device.h
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ * Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DM_DEVICE_H
+#define _DM_DEVICE_H
+
+#include <dm/uclass-id.h>
+#include <linker_lists.h>
+#include <linux/list.h>
+
+struct driver_info;
+
+/* Driver is active (probed). Cleared when it is removed */
+#define DM_FLAG_ACTIVATED	(1 << 0)
+
+/* DM is responsible for allocating and freeing platdata */
+#define DM_FLAG_ALLOC_PDATA	(2 << 0)
+
+/**
+ * struct device - An instance of a driver
+ *
+ * This holds information about a device, which is a driver bound to a
+ * particular port or peripheral (essentially a driver instance).
+ *
+ * A device will come into existence through a 'bind' call, either due to
+ * a U_BOOT_DEVICE() macro (in which case platdata is non-NULL) or a node
+ * in the device tree (in which case of_offset is >= 0). In the latter case
+ * we translate the device tree information into platdata in a function
+ * implemented by the driver ofdata_to_platdata method (called just before the
+ * probe method if the device has a device tree node.
+ *
+ * All three of platdata, priv and uclass_priv can be allocated by the
+ * driver, or you can use the auto_alloc_size members of struct driver and
+ * struct uclass_driver to have driver model do this automatically.
+ *
+ * @driver: The driver used by this device
+ * @name: Name of device, typically the FDT node name
+ * @platdata: Configuration data for this device
+ * @of_offset: Device tree node offset for this device (- for none)
+ * @parent: Parent of this device, or NULL for the top level device
+ * @priv: Private data for this device
+ * @uclass: Pointer to uclass for this device
+ * @uclass_priv: The uclass's private data for this device
+ * @uclass_node: Used by uclass to link its devices
+ * @child_head: List of children of this device
+ * @sibling_node: Next device in list of all devices
+ * @flags: Flags for this device DM_FLAG_...
+ */
+struct device {
+	struct driver *driver;
+	const char *name;
+	void *platdata;
+	int of_offset;
+	struct device *parent;
+	void *priv;
+	struct uclass *uclass;
+	void *uclass_priv;
+	struct list_head uclass_node;
+	struct list_head child_head;
+	struct list_head sibling_node;
+	uint32_t flags;
+};
+
+/* Returns the operations for a device */
+#define device_get_ops(dev)	(dev->driver->ops)
+
+/* Returns non-zero if the device is active (probed and not removed) */
+#define device_active(dev)	((dev)->flags & DM_FLAG_ACTIVATED)
+
+/**
+ * struct device_id - Lists the compatible strings supported by a driver
+ * @compatible: Compatible string
+ * @data: Data for this compatible string
+ */
+struct device_id {
+	const char *compatible;
+	ulong data;
+};
+
+/**
+ * struct driver - A driver for a feature or peripheral
+ *
+ * This holds methods for setting up a new device, and also removing it.
+ * The device needs information to set itself up - this is provided either
+ * by platdata or a device tree node (which we find by looking up
+ * matching compatible strings with of_match).
+ *
+ * Drivers all belong to a uclass, representing a class of devices of the
+ * same type. Common elements of the drivers can be implemented in the uclass,
+ * or the uclass can provide a consistent interface to the drivers within
+ * it.
+ *
+ * @name: Device name
+ * @id: Identiies the uclass we belong to
+ * @of_match: List of compatible strings to match, and any identifying data
+ * for each.
+ * @bind: Called to bind a device to its driver
+ * @probe: Called to probe a device, i.e. activate it
+ * @remove: Called to remove a device, i.e. de-activate it
+ * @unbind: Called to unbind a device from its driver
+ * @ofdata_to_platdata: Called before probe to decode device tree data
+ * @priv_auto_alloc_size: If non-zero this is the size of the private data
+ * to be allocated in the device's ->priv pointer. If zero, then the driver
+ * is responsible for allocating any data required.
+ * @platdata_auto_alloc_size: If non-zero this is the size of the
+ * platform data to be allocated in the device's ->platdata pointer.
+ * This is typically only useful for device-tree-aware drivers (those with
+ * an of_match), since drivers which use platdata will have the data
+ * provided in the U_BOOT_DEVICE() instantiation.
+ * ops: Driver-specific operations. This is typically a list of function
+ * pointers defined by the driver, to implement driver functions required by
+ * the uclass.
+ */
+struct driver {
+	char *name;
+	enum uclass_id id;
+	const struct device_id *of_match;
+	int (*bind)(struct device *dev);
+	int (*probe)(struct device *dev);
+	int (*remove)(struct device *dev);
+	int (*unbind)(struct device *dev);
+	int (*ofdata_to_platdata)(struct device *dev);
+	int priv_auto_alloc_size;
+	int platdata_auto_alloc_size;
+	const void *ops;	/* driver-specific operations */
+};
+
+/* Declare a new U-Boot driver */
+#define U_BOOT_DRIVER(__name)						\
+	ll_entry_declare(struct driver, __name, driver)
+
+/**
+ * dev_get_platdata() - Get the platform data for a device
+ *
+ * This checks that dev is not NULL, but no other checks for now
+ *
+ * @dev		Device to check
+ * @return platform data, or NULL if none
+ */
+void *dev_get_platdata(struct device *dev);
+
+/**
+ * dev_get_priv() - Get the private data for a device
+ *
+ * This checks that dev is not NULL, but no other checks for now
+ *
+ * @dev		Device to check
+ * @return private data, or NULL if none
+ */
+void *dev_get_priv(struct device *dev);
+
+#endif
diff --git a/include/dm/lists.h b/include/dm/lists.h
new file mode 100644
index 00000000000..0d09f9a14f5
--- /dev/null
+++ b/include/dm/lists.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DM_LISTS_H_
+#define _DM_LISTS_H_
+
+#include <dm/uclass-id.h>
+
+/**
+ * lists_driver_lookup_name() - Return u_boot_driver corresponding to name
+ *
+ * This function returns a pointer to a driver given its name. This is used
+ * for binding a driver given its name and platdata.
+ *
+ * @name: Name of driver to look up
+ * @return pointer to driver, or NULL if not found
+ */
+struct driver *lists_driver_lookup_name(const char *name);
+
+/**
+ * lists_uclass_lookup() - Return uclass_driver based on ID of the class
+ * id:		ID of the class
+ *
+ * This function returns the pointer to uclass_driver, which is the class's
+ * base structure based on the ID of the class. Returns NULL on error.
+ */
+struct uclass_driver *lists_uclass_lookup(enum uclass_id id);
+
+int lists_bind_drivers(struct device *parent);
+
+int lists_bind_fdt(struct device *parent, const void *blob, int offset);
+
+#endif
diff --git a/include/dm/platdata.h b/include/dm/platdata.h
new file mode 100644
index 00000000000..0ef3353e746
--- /dev/null
+++ b/include/dm/platdata.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ * Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DM_PLATDATA_H
+#define _DM_PLATDATA_H
+
+struct driver_info {
+	const char	*name;
+	const void	*platdata;
+};
+
+#define U_BOOT_DEVICE(__name)						\
+	ll_entry_declare(struct driver_info, __name, driver_info)
+
+#endif
diff --git a/include/dm/root.h b/include/dm/root.h
new file mode 100644
index 00000000000..0ebccda3557
--- /dev/null
+++ b/include/dm/root.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DM_ROOT_H_
+#define _DM_ROOT_H_
+
+struct device;
+
+/**
+ * dm_root() - Return pointer to the top of the driver tree
+ *
+ * This function returns pointer to the root node of the driver tree,
+ *
+ * @return pointer to root device, or NULL if not inited yet
+ */
+struct device *dm_root(void);
+
+/**
+ * dm_scan_platdata() - Scan all platform data and bind drivers
+ *
+ * This scans all available platdata and creates drivers for each
+ *
+ * @return 0 if OK, -ve on error
+ */
+int dm_scan_platdata(void);
+
+/**
+ * dm_scan_fdt() - Scan the device tree and bind drivers
+ *
+ * This scans the device tree and creates a driver for each node
+ *
+ * @blob: Pointer to device tree blob
+ * @return 0 if OK, -ve on error
+ */
+int dm_scan_fdt(const void *blob);
+
+/**
+ * dm_init() - Initialize Driver Model structures
+ *
+ * This function will initialize roots of driver tree and class tree.
+ * This needs to be called before anything uses the DM
+ *
+ * @return 0 if OK, -ve on error
+ */
+int dm_init(void);
+
+#endif
diff --git a/include/dm/test.h b/include/dm/test.h
new file mode 100644
index 00000000000..eeaa2eb2f46
--- /dev/null
+++ b/include/dm/test.h
@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2013 Google, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DM_TEST_H
+#define __DM_TEST_H
+
+#include <dm.h>
+
+/**
+ * struct dm_test_cdata - configuration data for test instance
+ *
+ * @ping_add: Amonut to add each time we get a ping
+ * @base: Base address of this device
+ */
+struct dm_test_pdata {
+	int ping_add;
+	uint32_t base;
+};
+
+/**
+ * struct test_ops - Operations supported by the test device
+ *
+ * @ping: Ping operation
+ *	@dev: Device to operate on
+ *	@pingval: Value to ping the device with
+ *	@pingret: Returns resulting value from driver
+ *	@return 0 if OK, -ve on error
+ */
+struct test_ops {
+	int (*ping)(struct device *dev, int pingval, int *pingret);
+};
+
+/* Operations that our test driver supports */
+enum {
+	DM_TEST_OP_BIND = 0,
+	DM_TEST_OP_UNBIND,
+	DM_TEST_OP_PROBE,
+	DM_TEST_OP_REMOVE,
+
+	/* For uclass */
+	DM_TEST_OP_POST_BIND,
+	DM_TEST_OP_PRE_UNBIND,
+	DM_TEST_OP_POST_PROBE,
+	DM_TEST_OP_PRE_REMOVE,
+	DM_TEST_OP_INIT,
+	DM_TEST_OP_DESTROY,
+
+	DM_TEST_OP_COUNT,
+};
+
+/* Test driver types */
+enum {
+	DM_TEST_TYPE_FIRST = 0,
+	DM_TEST_TYPE_SECOND,
+};
+
+/* The number added to the ping total on each probe */
+#define DM_TEST_START_TOTAL	5
+
+/**
+ * struct dm_test_priv - private data for the test devices
+ */
+struct dm_test_priv {
+	int ping_total;
+	int op_count[DM_TEST_OP_COUNT];
+};
+
+/**
+ * struct dm_test_perdev_class_priv - private per-device data for test uclass
+ */
+struct dm_test_uclass_perdev_priv {
+	int base_add;
+};
+
+/**
+ * struct dm_test_uclass_priv - private data for test uclass
+ */
+struct dm_test_uclass_priv {
+	int total_add;
+};
+
+/*
+ * Operation counts for the test driver, used to check that each method is
+ * called correctly
+ */
+extern int dm_testdrv_op_count[DM_TEST_OP_COUNT];
+
+extern struct dm_test_state global_test_state;
+
+/*
+ * struct dm_test_state - Entire state of dm test system
+ *
+ * This is often abreviated to dms.
+ *
+ * @root: Root device
+ * @testdev: Test device
+ * @fail_count: Number of tests that failed
+ * @force_fail_alloc: Force all memory allocs to fail
+ * @skip_post_probe: Skip uclass post-probe processing
+ */
+struct dm_test_state {
+	struct device *root;
+	struct device *testdev;
+	int fail_count;
+	int force_fail_alloc;
+	int skip_post_probe;
+};
+
+/* Test flags for each test */
+enum {
+	DM_TESTF_SCAN_PDATA	= 1 << 0,	/* test needs platform data */
+	DM_TESTF_PROBE_TEST	= 1 << 1,	/* probe test uclass */
+	DM_TESTF_SCAN_FDT	= 1 << 2,	/* scan device tree */
+};
+
+/**
+ * struct dm_test - Information about a driver model test
+ *
+ * @name: Name of test
+ * @func: Function to call to perform test
+ * @flags: Flags indicated pre-conditions for test
+ */
+struct dm_test {
+	const char *name;
+	int (*func)(struct dm_test_state *dms);
+	int flags;
+};
+
+/* Declare a new driver model test */
+#define DM_TEST(_name, _flags)						\
+	ll_entry_declare(struct dm_test, _name, dm_test) = {		\
+		.name = #_name,						\
+		.flags = _flags,					\
+		.func = _name,						\
+	}
+
+/* Declare ping methods for the drivers */
+int test_ping(struct device *dev, int pingval, int *pingret);
+int testfdt_ping(struct device *dev, int pingval, int *pingret);
+
+/**
+ * dm_check_operations() - Check that we can perform ping operations
+ *
+ * This checks that the ping operations work as expected for a device
+ *
+ * @dms: Overall test state
+ * @dev: Device to test
+ * @base: Base address, used to check ping return value
+ * @priv: Pointer to private test information
+ * @return 0 if OK, -ve on error
+ */
+int dm_check_operations(struct dm_test_state *dms, struct device *dev,
+			uint32_t base, struct dm_test_priv *priv);
+
+/**
+ * dm_test_main() - Run all the tests
+ *
+ * This runs all available driver model tests
+ *
+ * @return 0 if OK, -ve on error
+ */
+int dm_test_main(void);
+
+#endif
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
new file mode 100644
index 00000000000..f0e691c18c8
--- /dev/null
+++ b/include/dm/uclass-id.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DM_UCLASS_ID_H
+#define _DM_UCLASS_ID_H
+
+/* TODO(sjg@chromium.org): this could be compile-time generated */
+enum uclass_id {
+	/* These are used internally by driver model */
+	UCLASS_ROOT = 0,
+	UCLASS_DEMO,
+	UCLASS_TEST,
+	UCLASS_TEST_FDT,
+
+	/* U-Boot uclasses start here */
+	UCLASS_GPIO,
+
+	UCLASS_COUNT,
+	UCLASS_INVALID = -1,
+};
+
+#endif
diff --git a/include/dm/uclass-internal.h b/include/dm/uclass-internal.h
new file mode 100644
index 00000000000..cc65d5259f1
--- /dev/null
+++ b/include/dm/uclass-internal.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DM_UCLASS_INTERNAL_H
+#define _DM_UCLASS_INTERNAL_H
+
+/**
+ * uclass_find_device() - Return n-th child of uclass
+ * @id:		Id number of the uclass
+ * @index:	Position of the child in uclass's list
+ * #devp:	Returns pointer to device, or NULL on error
+ *
+ * The device is not prepared for use - this is an internal function
+ *
+ * @return the uclass pointer of a child at the given index or
+ * return NULL on error.
+ */
+int uclass_find_device(enum uclass_id id, int index, struct device **devp);
+
+/**
+ * uclass_bind_device() - Associate device with a uclass
+ *
+ * Connect the device into uclass's list of devices.
+ *
+ * @dev:	Pointer to the device
+ * #return 0 on success, -ve on error
+ */
+int uclass_bind_device(struct device *dev);
+
+/**
+ * uclass_unbind_device() - Deassociate device with a uclass
+ *
+ * Disconnect the device from uclass's list of devices.
+ *
+ * @dev:	Pointer to the device
+ * #return 0 on success, -ve on error
+ */
+int uclass_unbind_device(struct device *dev);
+
+/**
+ * uclass_post_probe_device() - Deal with a device that has just been probed
+ *
+ * Perform any post-processing of a probed device that is needed by the
+ * uclass.
+ *
+ * @dev:	Pointer to the device
+ * #return 0 on success, -ve on error
+ */
+int uclass_post_probe_device(struct device *dev);
+
+/**
+ * uclass_pre_remove_device() - Handle a device which is about to be removed
+ *
+ * Perform any pre-processing of a device that is about to be removed.
+ *
+ * @dev:	Pointer to the device
+ * #return 0 on success, -ve on error
+ */
+int uclass_pre_remove_device(struct device *dev);
+
+/**
+ * uclass_find() - Find uclass by its id
+ *
+ * @id:		Id to serach for
+ * @return pointer to uclass, or NULL if not found
+ */
+struct uclass *uclass_find(enum uclass_id key);
+
+/**
+ * uclass_destroy() - Destroy a uclass
+ *
+ * Destroy a uclass and all its devices
+ *
+ * @uc: uclass to destroy
+ * @return 0 on success, -ve on error
+ */
+int uclass_destroy(struct uclass *uc);
+
+#endif
diff --git a/include/dm/uclass.h b/include/dm/uclass.h
new file mode 100644
index 00000000000..cd23cfed163
--- /dev/null
+++ b/include/dm/uclass.h
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DM_UCLASS_H
+#define _DM_UCLASS_H
+
+#include <dm/uclass-id.h>
+#include <linux/list.h>
+
+/**
+ * struct uclass - a U-Boot drive class, collecting together similar drivers
+ *
+ * A uclass provides an interface to a particular function, which is
+ * implemented by one or more drivers. Every driver belongs to a uclass even
+ * if it is the only driver in that uclass. An example uclass is GPIO, which
+ * provides the ability to change read inputs, set and clear outputs, etc.
+ * There may be drivers for on-chip SoC GPIO banks, I2C GPIO expanders and
+ * PMIC IO lines, all made available in a unified way through the uclass.
+ *
+ * @priv: Private data for this uclass
+ * @uc_drv: The driver for the uclass itself, not to be confused with a
+ * 'struct driver'
+ * dev_head: List of devices in this uclass (devices are attached to their
+ * uclass when their bind method is called)
+ * @sibling_node: Next uclass in the linked list of uclasses
+ */
+struct uclass {
+	void *priv;
+	struct uclass_driver *uc_drv;
+	struct list_head dev_head;
+	struct list_head sibling_node;
+};
+
+struct device;
+
+/**
+ * struct uclass_driver - Driver for the uclass
+ *
+ * A uclass_driver provides a consistent interface to a set of related
+ * drivers.
+ *
+ * @name: Name of uclass driver
+ * @id: ID number of this uclass
+ * @post_bind: Called after a new device is bound to this uclass
+ * @pre_unbind: Called before a device is unbound from this uclass
+ * @post_probe: Called after a new device is probed
+ * @pre_remove: Called before a device is removed
+ * @init: Called to set up the uclass
+ * @destroy: Called to destroy the uclass
+ * @priv_auto_alloc_size: If non-zero this is the size of the private data
+ * to be allocated in the uclass's ->priv pointer. If zero, then the uclass
+ * driver is responsible for allocating any data required.
+ * @per_device_auto_alloc_size: Each device can hold private data owned
+ * by the uclass. If required this will be automatically allocated if this
+ * value is non-zero.
+ * @ops: Uclass operations, providing the consistent interface to devices
+ * within the uclass.
+ */
+struct uclass_driver {
+	const char *name;
+	enum uclass_id id;
+	int (*post_bind)(struct device *dev);
+	int (*pre_unbind)(struct device *dev);
+	int (*post_probe)(struct device *dev);
+	int (*pre_remove)(struct device *dev);
+	int (*init)(struct uclass *class);
+	int (*destroy)(struct uclass *class);
+	int priv_auto_alloc_size;
+	int per_device_auto_alloc_size;
+	const void *ops;
+};
+
+/* Declare a new uclass_driver */
+#define UCLASS_DRIVER(__name)						\
+	ll_entry_declare(struct uclass_driver, __name, uclass)
+
+/**
+ * uclass_get() - Get a uclass based on an ID, creating it if needed
+ *
+ * Every uclass is identified by an ID, a number from 0 to n-1 where n is
+ * the number of uclasses. This function allows looking up a uclass by its
+ * ID.
+ *
+ * @key: ID to look up
+ * @ucp: Returns pointer to uclass (there is only one per ID)
+ * @return 0 if OK, -ve on error
+ */
+int uclass_get(enum uclass_id key, struct uclass **ucp);
+
+/**
+ * uclass_get_device() - Get a uclass device based on an ID and index
+ *
+ * id: ID to look up
+ * @index: Device number within that uclass (0=first)
+ * @ucp: Returns pointer to uclass (there is only one per for each ID)
+ * @return 0 if OK, -ve on error
+ */
+int uclass_get_device(enum uclass_id id, int index, struct device **ucp);
+
+/**
+ * uclass_first_device() - Get the first device in a uclass
+ *
+ * @id: Uclass ID to look up
+ * @devp: Returns pointer to the first device in that uclass, or NULL if none
+ * @return 0 if OK (found or not found), -1 on error
+ */
+int uclass_first_device(enum uclass_id id, struct device **devp);
+
+/**
+ * uclass_next_device() - Get the next device in a uclass
+ *
+ * @devp: On entry, pointer to device to lookup. On exit, returns pointer
+ * to the next device in the same uclass, or NULL if none
+ * @return 0 if OK (found or not found), -1 on error
+ */
+int uclass_next_device(struct device **devp);
+
+/**
+ * uclass_foreach_dev() - Helper function to iteration through devices
+ *
+ * This creates a for() loop which works through the available devices in
+ * a uclass in order from start to end.
+ *
+ * @pos: struct device * to hold the current device. Set to NULL when there
+ * are no more devices.
+ * uc: uclass to scan
+ */
+#define uclass_foreach_dev(pos, uc)					\
+	for (pos = list_entry((&(uc)->dev_head)->next, typeof(*pos),	\
+			uclass_node);					\
+	     prefetch(pos->uclass_node.next),				\
+			&pos->uclass_node != (&(uc)->dev_head);		\
+	     pos = list_entry(pos->uclass_node.next, typeof(*pos),	\
+			uclass_node))
+
+#endif
diff --git a/include/dm/ut.h b/include/dm/ut.h
new file mode 100644
index 00000000000..fa9eac02265
--- /dev/null
+++ b/include/dm/ut.h
@@ -0,0 +1,95 @@
+/*
+ * Simple unit test library for driver model
+ *
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DM_UT_H
+#define __DM_UT_H
+
+struct dm_test_state;
+
+/**
+ * ut_fail() - Record failure of a unit test
+ *
+ * @dms: Test state
+ * @fname: Filename where the error occured
+ * @line: Line number where the error occured
+ * @func: Function name where the error occured
+ * @cond: The condition that failed
+ */
+void ut_fail(struct dm_test_state *dms, const char *fname, int line,
+	     const char *func, const char *cond);
+
+/**
+ * ut_failf() - Record failure of a unit test
+ *
+ * @dms: Test state
+ * @fname: Filename where the error occured
+ * @line: Line number where the error occured
+ * @func: Function name where the error occured
+ * @cond: The condition that failed
+ * @fmt: printf() format string for the error, followed by args
+ */
+void ut_failf(struct dm_test_state *dms, const char *fname, int line,
+	      const char *func, const char *cond, const char *fmt, ...)
+			__attribute__ ((format (__printf__, 6, 7)));
+
+
+/* Assert that a condition is non-zero */
+#define ut_assert(cond)							\
+	if (!(cond)) {							\
+		ut_fail(dms, __FILE__, __LINE__, __func__, #cond);	\
+		return -1;						\
+	}
+
+/* Assert that a condition is non-zero, with printf() string */
+#define ut_assertf(cond, fmt, args...)					\
+	if (!(cond)) {							\
+		ut_failf(dms, __FILE__, __LINE__, __func__, #cond,	\
+			 fmt, ##args);					\
+		return -1;						\
+	}
+
+/* Assert that two int expressions are equal */
+#define ut_asserteq(expr1, expr2) {					\
+	unsigned int val1 = (expr1), val2 = (expr2);			\
+									\
+	if (val1 != val2) {						\
+		ut_failf(dms, __FILE__, __LINE__, __func__,		\
+			 #expr1 " == " #expr2,				\
+			 "Expected %d, got %d", val1, val2);		\
+		return -1;						\
+	}								\
+}
+
+/* Assert that two string expressions are equal */
+#define ut_asserteq_str(expr1, expr2) {					\
+	const char *val1 = (expr1), *val2 = (expr2);			\
+									\
+	if (strcmp(val1, val2)) {					\
+		ut_failf(dms, __FILE__, __LINE__, __func__,		\
+			 #expr1 " = " #expr2,				\
+			 "Expected \"%s\", got \"%s\"", val1, val2);	\
+		return -1;						\
+	}								\
+}
+
+/* Assert that two pointers are equal */
+#define ut_asserteq_ptr(expr1, expr2) {					\
+	const void *val1 = (expr1), *val2 = (expr2);			\
+									\
+	if (val1 != val2) {						\
+		ut_failf(dms, __FILE__, __LINE__, __func__,		\
+			 #expr1 " = " #expr2,				\
+			 "Expected %p, got %p", val1, val2);		\
+		return -1;						\
+	}								\
+}
+
+/* Assert that an operation succeeds (returns 0) */
+#define ut_assertok(cond)	ut_asserteq(0, cond)
+
+#endif
diff --git a/include/dm/util.h b/include/dm/util.h
new file mode 100644
index 00000000000..8be64a921dd
--- /dev/null
+++ b/include/dm/util.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DM_UTIL_H
+
+void dm_warn(const char *fmt, ...);
+
+#ifdef DEBUG
+void dm_dbg(const char *fmt, ...);
+#else
+static inline void dm_dbg(const char *fmt, ...)
+{
+}
+#endif
+
+struct list_head;
+
+/**
+ * list_count_items() - Count number of items in a list
+ *
+ * @param head:		Head of list
+ * @return number of items, or 0 if empty
+ */
+int list_count_items(struct list_head *head);
+
+#endif
diff --git a/include/ec_commands.h b/include/ec_commands.h
index 12811cc070e..78baab1641a 100644
--- a/include/ec_commands.h
+++ b/include/ec_commands.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
+/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -42,13 +42,19 @@
 #define EC_LPC_ADDR_HOST_CMD   0x204
 
 /* I/O addresses for host command args and params */
-#define EC_LPC_ADDR_HOST_ARGS  0x800
-#define EC_LPC_ADDR_HOST_PARAM 0x804
-#define EC_HOST_PARAM_SIZE     0x0fc  /* Size of param area in bytes */
-
-/* I/O addresses for host command params, old interface */
-#define EC_LPC_ADDR_OLD_PARAM  0x880
-#define EC_OLD_PARAM_SIZE      0x080  /* Size of param area in bytes */
+/* Protocol version 2 */
+#define EC_LPC_ADDR_HOST_ARGS    0x800  /* And 0x801, 0x802, 0x803 */
+#define EC_LPC_ADDR_HOST_PARAM   0x804  /* For version 2 params; size is
+					 * EC_PROTO2_MAX_PARAM_SIZE */
+/* Protocol version 3 */
+#define EC_LPC_ADDR_HOST_PACKET  0x800  /* Offset of version 3 packet */
+#define EC_LPC_HOST_PACKET_SIZE  0x100  /* Max size of version 3 packet */
+
+/* The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff
+ * and they tell the kernel that so we have to think of it as two parts. */
+#define EC_HOST_CMD_REGION0    0x800
+#define EC_HOST_CMD_REGION1    0x880
+#define EC_HOST_CMD_REGION_SIZE 0x80
 
 /* EC command register bit functions */
 #define EC_LPC_CMDR_DATA	(1 << 0)  /* Data ready for host to read */
@@ -122,8 +128,8 @@
 #define EC_SWITCH_LID_OPEN               0x01
 #define EC_SWITCH_POWER_BUTTON_PRESSED   0x02
 #define EC_SWITCH_WRITE_PROTECT_DISABLED 0x04
-/* Recovery requested via keyboard */
-#define EC_SWITCH_KEYBOARD_RECOVERY      0x08
+/* Was recovery requested via keyboard; now unused. */
+#define EC_SWITCH_IGNORE1		 0x08
 /* Recovery requested via dedicated signal (from servo board) */
 #define EC_SWITCH_DEDICATED_RECOVERY     0x10
 /* Was fake developer mode switch; now unused.  Remove in next refactor. */
@@ -132,10 +138,13 @@
 /* Host command interface flags */
 /* Host command interface supports LPC args (LPC interface only) */
 #define EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED  0x01
+/* Host command interface supports version 3 protocol */
+#define EC_HOST_CMD_FLAG_VERSION_3   0x02
 
 /* Wireless switch flags */
 #define EC_WIRELESS_SWITCH_WLAN      0x01
 #define EC_WIRELESS_SWITCH_BLUETOOTH 0x02
+#define EC_WIRELESS_SWITCH_WWAN      0x04
 
 /*
  * This header file is used in coreboot both in C and ACPI code.  The ACPI code
@@ -191,6 +200,9 @@ enum ec_status {
 	EC_RES_UNAVAILABLE = 9,		/* No response available */
 	EC_RES_TIMEOUT = 10,		/* We got a timeout */
 	EC_RES_OVERFLOW = 11,		/* Table / data overflow */
+	EC_RES_INVALID_HEADER = 12,     /* Header contains invalid data */
+	EC_RES_REQUEST_TRUNCATED = 13,  /* Didn't get the entire request */
+	EC_RES_RESPONSE_TOO_BIG = 14    /* Response was too big to handle */
 };
 
 /*
@@ -272,6 +284,105 @@ struct ec_lpc_host_args {
  */
 #define EC_HOST_ARGS_FLAG_TO_HOST   0x02
 
+/*****************************************************************************/
+
+/*
+ * Protocol version 2 for I2C and SPI send a request this way:
+ *
+ *	0	EC_CMD_VERSION0 + (command version)
+ *	1	Command number
+ *	2	Length of params = N
+ *	3..N+2	Params, if any
+ *	N+3	8-bit checksum of bytes 0..N+2
+ *
+ * The corresponding response is:
+ *
+ *	0	Result code (EC_RES_*)
+ *	1	Length of params = M
+ *	2..M+1	Params, if any
+ *	M+2	8-bit checksum of bytes 0..M+1
+ */
+#define EC_PROTO2_REQUEST_HEADER_BYTES 3
+#define EC_PROTO2_REQUEST_TRAILER_BYTES 1
+#define EC_PROTO2_REQUEST_OVERHEAD (EC_PROTO2_REQUEST_HEADER_BYTES +	\
+				    EC_PROTO2_REQUEST_TRAILER_BYTES)
+
+#define EC_PROTO2_RESPONSE_HEADER_BYTES 2
+#define EC_PROTO2_RESPONSE_TRAILER_BYTES 1
+#define EC_PROTO2_RESPONSE_OVERHEAD (EC_PROTO2_RESPONSE_HEADER_BYTES +	\
+				     EC_PROTO2_RESPONSE_TRAILER_BYTES)
+
+/* Parameter length was limited by the LPC interface */
+#define EC_PROTO2_MAX_PARAM_SIZE 0xfc
+
+/* Maximum request and response packet sizes for protocol version 2 */
+#define EC_PROTO2_MAX_REQUEST_SIZE (EC_PROTO2_REQUEST_OVERHEAD +	\
+				    EC_PROTO2_MAX_PARAM_SIZE)
+#define EC_PROTO2_MAX_RESPONSE_SIZE (EC_PROTO2_RESPONSE_OVERHEAD +	\
+				     EC_PROTO2_MAX_PARAM_SIZE)
+
+/*****************************************************************************/
+
+/*
+ * Value written to legacy command port / prefix byte to indicate protocol
+ * 3+ structs are being used.  Usage is bus-dependent.
+ */
+#define EC_COMMAND_PROTOCOL_3 0xda
+
+#define EC_HOST_REQUEST_VERSION 3
+
+/* Version 3 request from host */
+struct ec_host_request {
+	/* Struct version (=3)
+	 *
+	 * EC will return EC_RES_INVALID_HEADER if it receives a header with a
+	 * version it doesn't know how to parse.
+	 */
+	uint8_t struct_version;
+
+	/*
+	 * Checksum of request and data; sum of all bytes including checksum
+	 * should total to 0.
+	 */
+	uint8_t checksum;
+
+	/* Command code */
+	uint16_t command;
+
+	/* Command version */
+	uint8_t command_version;
+
+	/* Unused byte in current protocol version; set to 0 */
+	uint8_t reserved;
+
+	/* Length of data which follows this header */
+	uint16_t data_len;
+} __packed;
+
+#define EC_HOST_RESPONSE_VERSION 3
+
+/* Version 3 response from EC */
+struct ec_host_response {
+	/* Struct version (=3) */
+	uint8_t struct_version;
+
+	/*
+	 * Checksum of response and data; sum of all bytes including checksum
+	 * should total to 0.
+	 */
+	uint8_t checksum;
+
+	/* Result code (EC_RES_*) */
+	uint16_t result;
+
+	/* Length of data which follows this header */
+	uint16_t data_len;
+
+	/* Unused bytes in current protocol version; set to 0 */
+	uint16_t reserved;
+} __packed;
+
+/*****************************************************************************/
 /*
  * Notes on commands:
  *
@@ -411,6 +522,46 @@ struct ec_response_get_comms_status {
 	uint32_t flags;		/* Mask of enum ec_comms_status */
 } __packed;
 
+/*
+ * Fake a variety of responses, purely for testing purposes.
+ * FIXME: Would be nice to force checksum errors.
+ */
+#define EC_CMD_TEST_PROTOCOL		0x0a
+
+/* Tell the EC what to send back to us. */
+struct ec_params_test_protocol {
+	uint32_t ec_result;
+	uint32_t ret_len;
+	uint8_t buf[32];
+} __packed;
+
+/* Here it comes... */
+struct ec_response_test_protocol {
+	uint8_t buf[32];
+} __packed;
+
+/* Get prococol information */
+#define EC_CMD_GET_PROTOCOL_INFO	0x0b
+
+/* Flags for ec_response_get_protocol_info.flags */
+/* EC_RES_IN_PROGRESS may be returned if a command is slow */
+#define EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED (1 << 0)
+
+struct ec_response_get_protocol_info {
+	/* Fields which exist if at least protocol version 3 supported */
+
+	/* Bitmask of protocol versions supported (1 << n means version n)*/
+	uint32_t protocol_versions;
+
+	/* Maximum request packet size, in bytes */
+	uint16_t max_request_packet_size;
+
+	/* Maximum response packet size, in bytes */
+	uint16_t max_response_packet_size;
+
+	/* Flags; see EC_PROTOCOL_INFO_* */
+	uint32_t flags;
+} __packed;
 
 /*****************************************************************************/
 /* Flash commands */
@@ -452,15 +603,15 @@ struct ec_params_flash_read {
 
 /* Write flash */
 #define EC_CMD_FLASH_WRITE 0x12
+#define EC_VER_FLASH_WRITE 1
+
+/* Version 0 of the flash command supported only 64 bytes of data */
+#define EC_FLASH_WRITE_VER0_SIZE 64
 
 struct ec_params_flash_write {
 	uint32_t offset;   /* Byte offset to write */
 	uint32_t size;     /* Size to write in bytes */
-	/*
-	 * Data to write.  Could really use EC_PARAM_SIZE - 8, but tidiest to
-	 * use a power of 2 so writes stay aligned.
-	 */
-	uint8_t data[64];
+	/* Followed by data to write */
 } __packed;
 
 /* Erase flash */
@@ -536,7 +687,7 @@ struct ec_response_flash_protect {
 
 enum ec_flash_region {
 	/* Region which holds read-only EC image */
-	EC_FLASH_REGION_RO,
+	EC_FLASH_REGION_RO = 0,
 	/* Region which holds rewritable EC image */
 	EC_FLASH_REGION_RW,
 	/*
@@ -544,6 +695,8 @@ enum ec_flash_region {
 	 * EC_FLASH_REGION_RO)
 	 */
 	EC_FLASH_REGION_WP_RO,
+	/* Number of regions */
+	EC_FLASH_REGION_COUNT,
 };
 
 struct ec_params_flash_region_info {
@@ -727,6 +880,49 @@ enum lightbar_command {
 };
 
 /*****************************************************************************/
+/* LED control commands */
+
+#define EC_CMD_LED_CONTROL 0x29
+
+enum ec_led_id {
+	EC_LED_ID_BATTERY_LED = 0,
+	EC_LED_ID_POWER_BUTTON_LED,
+	EC_LED_ID_ADAPTER_LED,
+};
+
+/* LED control flags */
+#define EC_LED_FLAGS_QUERY (1 << 0) /* Query LED capability only */
+#define EC_LED_FLAGS_AUTO  (1 << 1) /* Switch LED back to automatic control */
+
+enum ec_led_colors {
+	EC_LED_COLOR_RED = 0,
+	EC_LED_COLOR_GREEN,
+	EC_LED_COLOR_BLUE,
+	EC_LED_COLOR_YELLOW,
+	EC_LED_COLOR_WHITE,
+
+	EC_LED_COLOR_COUNT
+};
+
+struct ec_params_led_control {
+	uint8_t led_id;     /* Which LED to control */
+	uint8_t flags;      /* Control flags */
+
+	uint8_t brightness[EC_LED_COLOR_COUNT];
+} __packed;
+
+struct ec_response_led_control {
+	/*
+	 * Available brightness value range.
+	 *
+	 * Range 0 means color channel not present.
+	 * Range 1 means on/off control.
+	 * Other values means the LED is control by PWM.
+	 */
+	uint8_t brightness_range[EC_LED_COLOR_COUNT];
+} __packed;
+
+/*****************************************************************************/
 /* Verified boot commands */
 
 /*
@@ -914,57 +1110,57 @@ struct ec_params_tmp006_set_calibration {
 } __packed;
 
 /*****************************************************************************/
-/* CROS_EC - Matrix KeyBoard Protocol */
+/* MKBP - Matrix KeyBoard Protocol */
 
 /*
  * Read key state
  *
- * Returns raw data for keyboard cols; see ec_response_cros_ec_info.cols for
+ * Returns raw data for keyboard cols; see ec_response_mkbp_info.cols for
  * expected response size.
  */
-#define EC_CMD_CROS_EC_STATE 0x60
+#define EC_CMD_MKBP_STATE 0x60
 
 /* Provide information about the matrix : number of rows and columns */
-#define EC_CMD_CROS_EC_INFO 0x61
+#define EC_CMD_MKBP_INFO 0x61
 
-struct ec_response_cros_ec_info {
+struct ec_response_mkbp_info {
 	uint32_t rows;
 	uint32_t cols;
 	uint8_t switches;
 } __packed;
 
 /* Simulate key press */
-#define EC_CMD_CROS_EC_SIMULATE_KEY 0x62
+#define EC_CMD_MKBP_SIMULATE_KEY 0x62
 
-struct ec_params_cros_ec_simulate_key {
+struct ec_params_mkbp_simulate_key {
 	uint8_t col;
 	uint8_t row;
 	uint8_t pressed;
 } __packed;
 
 /* Configure keyboard scanning */
-#define EC_CMD_CROS_EC_SET_CONFIG 0x64
-#define EC_CMD_CROS_EC_GET_CONFIG 0x65
+#define EC_CMD_MKBP_SET_CONFIG 0x64
+#define EC_CMD_MKBP_GET_CONFIG 0x65
 
 /* flags */
-enum cros_ec_config_flags {
-	EC_CROS_EC_FLAGS_ENABLE = 1,	/* Enable keyboard scanning */
+enum mkbp_config_flags {
+	EC_MKBP_FLAGS_ENABLE = 1,	/* Enable keyboard scanning */
 };
 
-enum cros_ec_config_valid {
-	EC_CROS_EC_VALID_SCAN_PERIOD		= 1 << 0,
-	EC_CROS_EC_VALID_POLL_TIMEOUT		= 1 << 1,
-	EC_CROS_EC_VALID_MIN_POST_SCAN_DELAY	= 1 << 3,
-	EC_CROS_EC_VALID_OUTPUT_SETTLE		= 1 << 4,
-	EC_CROS_EC_VALID_DEBOUNCE_DOWN		= 1 << 5,
-	EC_CROS_EC_VALID_DEBOUNCE_UP		= 1 << 6,
-	EC_CROS_EC_VALID_FIFO_MAX_DEPTH		= 1 << 7,
+enum mkbp_config_valid {
+	EC_MKBP_VALID_SCAN_PERIOD		= 1 << 0,
+	EC_MKBP_VALID_POLL_TIMEOUT		= 1 << 1,
+	EC_MKBP_VALID_MIN_POST_SCAN_DELAY	= 1 << 3,
+	EC_MKBP_VALID_OUTPUT_SETTLE		= 1 << 4,
+	EC_MKBP_VALID_DEBOUNCE_DOWN		= 1 << 5,
+	EC_MKBP_VALID_DEBOUNCE_UP		= 1 << 6,
+	EC_MKBP_VALID_FIFO_MAX_DEPTH		= 1 << 7,
 };
 
 /* Configuration for our key scanning algorithm */
-struct ec_cros_ec_config {
+struct ec_mkbp_config {
 	uint32_t valid_mask;		/* valid fields */
-	uint8_t flags;		/* some flags (enum cros_ec_config_flags) */
+	uint8_t flags;		/* some flags (enum mkbp_config_flags) */
 	uint8_t valid_flags;		/* which flags are valid */
 	uint16_t scan_period_us;	/* period between start of scans */
 	/* revert to interrupt mode after no activity for this long */
@@ -983,12 +1179,12 @@ struct ec_cros_ec_config {
 	uint8_t fifo_max_depth;
 } __packed;
 
-struct ec_params_cros_ec_set_config {
-	struct ec_cros_ec_config config;
+struct ec_params_mkbp_set_config {
+	struct ec_mkbp_config config;
 } __packed;
 
-struct ec_response_cros_ec_get_config {
-	struct ec_cros_ec_config config;
+struct ec_response_mkbp_get_config {
+	struct ec_mkbp_config config;
 } __packed;
 
 /* Run the key scan emulation */
@@ -1144,7 +1340,7 @@ struct ec_response_gpio_get {
 #define EC_CMD_I2C_READ 0x94
 
 struct ec_params_i2c_read {
-	uint16_t addr;
+	uint16_t addr; /* 8-bit address (7-bit shifted << 1) */
 	uint8_t read_size; /* Either 8 or 16. */
 	uint8_t port;
 	uint8_t offset;
@@ -1158,7 +1354,7 @@ struct ec_response_i2c_read {
 
 struct ec_params_i2c_write {
 	uint16_t data;
-	uint16_t addr;
+	uint16_t addr; /* 8-bit address (7-bit shifted << 1) */
 	uint8_t write_size; /* Either 8 or 16. */
 	uint8_t port;
 	uint8_t offset;
@@ -1242,6 +1438,61 @@ struct ec_response_ldo_get {
 } __packed;
 
 /*****************************************************************************/
+/* Power info. */
+
+/*
+ * Get power info.
+ */
+#define EC_CMD_POWER_INFO 0x9d
+
+struct ec_response_power_info {
+	uint32_t usb_dev_type;
+	uint16_t voltage_ac;
+	uint16_t voltage_system;
+	uint16_t current_system;
+	uint16_t usb_current_limit;
+} __packed;
+
+/*****************************************************************************/
+/* I2C passthru command */
+
+#define EC_CMD_I2C_PASSTHRU 0x9e
+
+/* Slave address is 10 (not 7) bit */
+#define EC_I2C_FLAG_10BIT	(1 << 16)
+
+/* Read data; if not present, message is a write */
+#define EC_I2C_FLAG_READ	(1 << 15)
+
+/* Mask for address */
+#define EC_I2C_ADDR_MASK	0x3ff
+
+#define EC_I2C_STATUS_NAK	(1 << 0) /* Transfer was not acknowledged */
+#define EC_I2C_STATUS_TIMEOUT	(1 << 1) /* Timeout during transfer */
+
+/* Any error */
+#define EC_I2C_STATUS_ERROR	(EC_I2C_STATUS_NAK | EC_I2C_STATUS_TIMEOUT)
+
+struct ec_params_i2c_passthru_msg {
+	uint16_t addr_flags;	/* I2C slave address (7 or 10 bits) and flags */
+	uint16_t len;		/* Number of bytes to read or write */
+} __packed;
+
+struct ec_params_i2c_passthru {
+	uint8_t port;		/* I2C port number */
+	uint8_t num_msgs;	/* Number of messages */
+	struct ec_params_i2c_passthru_msg msg[];
+	/* Data to write for all messages is concatenated here */
+} __packed;
+
+struct ec_response_i2c_passthru {
+	uint8_t i2c_status;	/* Status flags (EC_I2C_STATUS_...) */
+	uint8_t num_msgs;	/* Number of messages processed */
+	uint8_t data[];		/* Data read by messages concatenated here */
+} __packed;
+
+
+/*****************************************************************************/
 /* Temporary debug commands. TODO: remove this crosbug.com/p/13849 */
 
 /*
@@ -1257,7 +1508,16 @@ struct ec_response_ldo_get {
 #define EC_CMD_CHARGE_CURRENT_LIMIT 0xa1
 
 struct ec_params_current_limit {
-	uint32_t limit;
+	uint32_t limit; /* in mA */
+} __packed;
+
+/*
+ * Set maximum external power current.
+ */
+#define EC_CMD_EXT_POWER_CURRENT_LIMIT 0xa2
+
+struct ec_params_ext_power_current_limit {
+	uint32_t limit; /* in mA */
 } __packed;
 
 /*****************************************************************************/
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 19bab794481..3196cf66833 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -79,8 +79,10 @@ enum fdt_compat_id {
 	COMPAT_SAMSUNG_EXYNOS5_USB3_PHY,/* Exynos phy controller for usb3.0 */
 	COMPAT_SAMSUNG_EXYNOS_TMU,	/* Exynos TMU */
 	COMPAT_SAMSUNG_EXYNOS_FIMD,	/* Exynos Display controller */
+	COMPAT_SAMSUNG_EXYNOS_MIPI_DSI,	/* Exynos mipi dsi */
 	COMPAT_SAMSUNG_EXYNOS5_DP,	/* Exynos Display port controller */
 	COMPAT_SAMSUNG_EXYNOS5_DWMMC,	/* Exynos5 DWMMC controller */
+	COMPAT_SAMSUNG_EXYNOS_MMC,	/* Exynos MMC controller */
 	COMPAT_SAMSUNG_EXYNOS_SERIAL,	/* Exynos UART */
 	COMPAT_MAXIM_MAX77686_PMIC,	/* MAX77686 PMIC */
 	COMPAT_GENERIC_SPI_FLASH,	/* Generic SPI Flash chip */
@@ -88,6 +90,8 @@ enum fdt_compat_id {
 	COMPAT_INFINEON_SLB9635_TPM,	/* Infineon SLB9635 TPM */
 	COMPAT_INFINEON_SLB9645_TPM,	/* Infineon SLB9645 TPM */
 	COMPAT_SAMSUNG_EXYNOS5_I2C,	/* Exynos5 High Speed I2C Controller */
+	COMPAT_SANDBOX_HOST_EMULATION,	/* Sandbox emulation of a function */
+	COMPAT_SANDBOX_LCD_SDL,		/* Sandbox LCD emulation with SDL */
 
 	COMPAT_COUNT,
 };
@@ -530,4 +534,22 @@ const u8 *fdtdec_locate_byte_array(const void *blob, int node,
  */
 int fdtdec_decode_region(const void *blob, int node,
 		const char *prop_name, void **ptrp, size_t *size);
+
+/* A flash map entry, containing an offset and length */
+struct fmap_entry {
+	uint32_t offset;
+	uint32_t length;
+};
+
+/**
+ * Read a flash entry from the fdt
+ *
+ * @param blob		FDT blob
+ * @param node		Offset of node to read
+ * @param name		Name of node being read
+ * @param entry		Place to put offset and size of this node
+ * @return 0 if ok, -ve on error
+ */
+int fdtdec_read_fmap_entry(const void *blob, int node, const char *name,
+			   struct fmap_entry *entry);
 #endif
diff --git a/include/fsl_usb.h b/include/fsl_usb.h
index 915774cba8a..8b63cdd88c0 100644
--- a/include/fsl_usb.h
+++ b/include/fsl_usb.h
@@ -52,13 +52,32 @@ struct ccsr_usb_phy {
 #define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
 #define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)
 #define CONFIG_SYS_FSL_USB_SYS_CLK_VALID (1 << 0)
+#define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN (1 << 7)
+#define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK (3 << 4)
+
+#define INC_DCNT_THRESHOLD_25MV        (0 << 4)
+#define INC_DCNT_THRESHOLD_50MV        (1 << 4)
+#define DEC_DCNT_THRESHOLD_25MV        (2 << 4)
+#define DEC_DCNT_THRESHOLD_50MV        (3 << 4)
 #else
 struct ccsr_usb_phy {
-	u8	res0[0x18];
+	u32     config1;
+	u32     config2;
+	u32     config3;
+	u32     config4;
+	u32     config5;
+	u32     status1;
 	u32	usb_enable_override;
 	u8	res[0xe4];
 };
-#define	CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE	1
+#define CONFIG_SYS_FSL_USB_HS_DISCNCT_INC (3 << 22)
+#define CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL (1 << 20)
+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0 13
+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3 16
+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0 0
+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3 3
+#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK 0x07
 #endif
 
 #endif /*_ASM_FSL_USB_H_ */
diff --git a/include/lcd.h b/include/lcd.h
index d06d6f10720..5f84cd3c5b2 100644
--- a/include/lcd.h
+++ b/include/lcd.h
@@ -313,6 +313,9 @@ int lcd_get_size(int *line_length);
 int lcd_dt_simplefb_add_node(void *blob);
 int lcd_dt_simplefb_enable_existing_node(void *blob);
 
+/* Update the LCD / flush the cache */
+void lcd_sync(void);
+
 /************************************************************************/
 /* ** BITMAP DISPLAY SUPPORT						*/
 /************************************************************************/
diff --git a/include/linux/mtd/omap_elm.h b/include/linux/mtd/omap_elm.h
new file mode 100644
index 00000000000..45454eaf0f1
--- /dev/null
+++ b/include/linux/mtd/omap_elm.h
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2010-2011 Texas Instruments, <www.ti.com>
+ * Mansoor Ahamed <mansoor.ahamed@ti.com>
+ *
+ * Derived from work done by Rohit Choraria <rohitkc@ti.com> for omap3
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __ASM_ARCH_ELM_H
+#define __ASM_ARCH_ELM_H
+/*
+ * ELM Module Registers
+ */
+
+/* ELM registers bit fields */
+#define ELM_SYSCONFIG_SOFTRESET_MASK			(0x2)
+#define ELM_SYSCONFIG_SOFTRESET			(0x2)
+#define ELM_SYSSTATUS_RESETDONE_MASK			(0x1)
+#define ELM_SYSSTATUS_RESETDONE			(0x1)
+#define ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_MASK		(0x3)
+#define ELM_LOCATION_CONFIG_ECC_SIZE_MASK		(0x7FF0000)
+#define ELM_LOCATION_CONFIG_ECC_SIZE_POS		(16)
+#define ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID		(0x00010000)
+#define ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK	(0x100)
+#define ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK		(0x1F)
+
+#ifndef __ASSEMBLY__
+
+enum bch_level {
+	BCH_4_BIT = 0,
+	BCH_8_BIT,
+	BCH_16_BIT
+};
+
+
+/* BCH syndrome registers */
+struct syndrome {
+	u32 syndrome_fragment_x[7];	/* 0x400, 0x404.... 0x418 */
+	u8 res1[36];			/* 0x41c */
+};
+
+/* BCH error status & location register */
+struct location {
+	u32 location_status;		/* 0x800 */
+	u8 res1[124];			/* 0x804 */
+	u32 error_location_x[16];	/* 0x880.... */
+	u8 res2[64];			/* 0x8c0 */
+};
+
+/* BCH ELM register map - do not try to allocate memmory for this structure.
+ * We have used plenty of reserved variables to fill the slots in the ELM
+ * register memory map.
+ * Directly initialize the struct pointer to ELM base address.
+ */
+struct elm {
+	u32 rev;				/* 0x000 */
+	u8 res1[12];				/* 0x004 */
+	u32 sysconfig;				/* 0x010 */
+	u32 sysstatus;				/* 0x014 */
+	u32 irqstatus;				/* 0x018 */
+	u32 irqenable;				/* 0x01c */
+	u32 location_config;			/* 0x020 */
+	u8 res2[92];				/* 0x024 */
+	u32 page_ctrl;				/* 0x080 */
+	u8 res3[892];				/* 0x084 */
+	struct  syndrome syndrome_fragments[8]; /* 0x400 */
+	u8 res4[512];				/* 0x600 */
+	struct location  error_location[8];	/* 0x800 */
+};
+
+int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count,
+		u32 *error_locations);
+int elm_config(enum bch_level level);
+void elm_reset(void);
+void elm_init(void);
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARCH_ELM_H */
diff --git a/include/linux/mtd/omap_gpmc.h b/include/linux/mtd/omap_gpmc.h
new file mode 100644
index 00000000000..22f65739695
--- /dev/null
+++ b/include/linux/mtd/omap_gpmc.h
@@ -0,0 +1,84 @@
+/*
+ * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
+ * Rohit Choraria <rohitkc@ti.com>
+ *
+ * (C) Copyright 2013 Andreas Bießmann <andreas.devel@googlemail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __ASM_OMAP_GPMC_H
+#define __ASM_OMAP_GPMC_H
+
+#define GPMC_BUF_EMPTY	0
+#define GPMC_BUF_FULL	1
+
+enum omap_ecc {
+	/* 1-bit  ECC calculation by Software, Error detection by Software */
+	OMAP_ECC_HAM1_CODE_SW = 1, /* avoid un-initialized int can be 0x0 */
+	/* 1-bit  ECC calculation by GPMC, Error detection by Software */
+	/* ECC layout compatible to legacy ROMCODE. */
+	OMAP_ECC_HAM1_CODE_HW,
+	/* 4-bit  ECC calculation by GPMC, Error detection by Software */
+	OMAP_ECC_BCH4_CODE_HW_DETECTION_SW,
+	/* 4-bit  ECC calculation by GPMC, Error detection by ELM */
+	OMAP_ECC_BCH4_CODE_HW,
+	/* 8-bit  ECC calculation by GPMC, Error detection by Software */
+	OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
+	/* 8-bit  ECC calculation by GPMC, Error detection by ELM */
+	OMAP_ECC_BCH8_CODE_HW,
+};
+
+struct gpmc_cs {
+	u32 config1;		/* 0x00 */
+	u32 config2;		/* 0x04 */
+	u32 config3;		/* 0x08 */
+	u32 config4;		/* 0x0C */
+	u32 config5;		/* 0x10 */
+	u32 config6;		/* 0x14 */
+	u32 config7;		/* 0x18 */
+	u32 nand_cmd;		/* 0x1C */
+	u32 nand_adr;		/* 0x20 */
+	u32 nand_dat;		/* 0x24 */
+	u8 res[8];		/* blow up to 0x30 byte */
+};
+
+struct bch_res_0_3 {
+	u32 bch_result_x[4];
+};
+
+struct gpmc {
+	u8 res1[0x10];
+	u32 sysconfig;		/* 0x10 */
+	u8 res2[0x4];
+	u32 irqstatus;		/* 0x18 */
+	u32 irqenable;		/* 0x1C */
+	u8 res3[0x20];
+	u32 timeout_control;	/* 0x40 */
+	u8 res4[0xC];
+	u32 config;		/* 0x50 */
+	u32 status;		/* 0x54 */
+	u8 res5[0x8];		/* 0x58 */
+	struct gpmc_cs cs[8];	/* 0x60, 0x90, .. */
+	u8 res6[0x14];		/* 0x1E0 */
+	u32 ecc_config;		/* 0x1F4 */
+	u32 ecc_control;	/* 0x1F8 */
+	u32 ecc_size_config;	/* 0x1FC */
+	u32 ecc1_result;	/* 0x200 */
+	u32 ecc2_result;	/* 0x204 */
+	u32 ecc3_result;	/* 0x208 */
+	u32 ecc4_result;	/* 0x20C */
+	u32 ecc5_result;	/* 0x210 */
+	u32 ecc6_result;	/* 0x214 */
+	u32 ecc7_result;	/* 0x218 */
+	u32 ecc8_result;	/* 0x21C */
+	u32 ecc9_result;	/* 0x220 */
+	u8 res7[12];		/* 0x224 */
+	u32 testmomde_ctrl;	/* 0x230 */
+	u8 res8[12];		/* 0x234 */
+	struct bch_res_0_3 bch_result_0_3[2];	/* 0x240 */
+};
+
+/* Used for board specific gpmc initialization */
+extern struct gpmc *gpmc_cfg;
+
+#endif /* __ASM_OMAP_GPMC_H */
diff --git a/include/linux/sizes.h b/include/linux/sizes.h
new file mode 100644
index 00000000000..ce3e8150c17
--- /dev/null
+++ b/include/linux/sizes.h
@@ -0,0 +1,47 @@
+/*
+ * include/linux/sizes.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __LINUX_SIZES_H__
+#define __LINUX_SIZES_H__
+
+#define SZ_1				0x00000001
+#define SZ_2				0x00000002
+#define SZ_4				0x00000004
+#define SZ_8				0x00000008
+#define SZ_16				0x00000010
+#define SZ_32				0x00000020
+#define SZ_64				0x00000040
+#define SZ_128				0x00000080
+#define SZ_256				0x00000100
+#define SZ_512				0x00000200
+
+#define SZ_1K				0x00000400
+#define SZ_2K				0x00000800
+#define SZ_4K				0x00001000
+#define SZ_8K				0x00002000
+#define SZ_16K				0x00004000
+#define SZ_32K				0x00008000
+#define SZ_64K				0x00010000
+#define SZ_128K				0x00020000
+#define SZ_256K				0x00040000
+#define SZ_512K				0x00080000
+
+#define SZ_1M				0x00100000
+#define SZ_2M				0x00200000
+#define SZ_4M				0x00400000
+#define SZ_8M				0x00800000
+#define SZ_16M				0x01000000
+#define SZ_32M				0x02000000
+#define SZ_64M				0x04000000
+#define SZ_128M				0x08000000
+#define SZ_256M				0x10000000
+#define SZ_512M				0x20000000
+
+#define SZ_1G				0x40000000
+#define SZ_2G				0x80000000
+
+#endif /* __LINUX_SIZES_H__ */
diff --git a/include/nand.h b/include/nand.h
index 84116f49372..fc735d1ec44 100644
--- a/include/nand.h
+++ b/include/nand.h
@@ -21,10 +21,16 @@
  * at the same time, so do it here.  When all drivers are
  * converted, this will go away.
  */
+#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_NAND_FSL_ELBC) || defined(CONFIG_NAND_FSL_IFC)
+#define CONFIG_SYS_NAND_SELF_INIT
+#endif
+#else
 #if defined(CONFIG_NAND_FSL_ELBC) || defined(CONFIG_NAND_ATMEL)\
 	|| defined(CONFIG_NAND_FSL_IFC)
 #define CONFIG_SYS_NAND_SELF_INIT
 #endif
+#endif
 
 extern void nand_init(void);
 
diff --git a/include/netdev.h b/include/netdev.h
index 37056291946..32b5073ef02 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -86,10 +86,12 @@ int uli526x_initialize(bd_t *bis);
 int armada100_fec_register(unsigned long base_addr);
 int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr,
 							unsigned long dma_addr);
+int xilinx_emaclite_of_init(const void *blob);
 int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
 							int txpp, int rxpp);
 int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int flags,
 						unsigned long ctrl_addr);
+int zynq_gem_of_init(const void *blob);
 int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio);
 /*
  * As long as the Xilinx xps_ll_temac ethernet driver has not its own interface
diff --git a/include/os.h b/include/os.h
index d6d6e5794e4..0230a7f40da 100644
--- a/include/os.h
+++ b/include/os.h
@@ -84,6 +84,14 @@ int os_open(const char *pathname, int flags);
 int os_close(int fd);
 
 /**
+ * Access to the OS unlink() system call
+ *
+ * \param pathname Path of file to delete
+ * \return 0 for success, other for error
+ */
+int os_unlink(const char *pathname);
+
+/**
  * Access to the OS exit() system call
  *
  * This exits with the supplied return code, which should be 0 to indicate
@@ -95,8 +103,12 @@ void os_exit(int exit_code) __attribute__((noreturn));
 
 /**
  * Put tty into raw mode to mimic serial console better
+ *
+ * @param fd		File descriptor of stdin (normally 0)
+ * @param allow_sigs	Allow Ctrl-C, Ctrl-Z to generate signals rather than
+ *			be handled by U-Boot
  */
-void os_tty_raw(int fd);
+void os_tty_raw(int fd, bool allow_sigs);
 
 /**
  * Acquires some memory from the underlying os.
@@ -245,4 +257,23 @@ int os_write_ram_buf(const char *fname);
  */
 int os_read_ram_buf(const char *fname);
 
+/**
+ * Jump to a new executable image
+ *
+ * This uses exec() to run a new executable image, after putting it in a
+ * temporary file. The same arguments and environment are passed to this
+ * new image, with the addition of:
+ *
+ *	-j <filename>	Specifies the filename the image was written to. The
+ *			calling image may want to delete this at some point.
+ *	-m <filename>	Specifies the file containing the sandbox memory
+ *			(ram_buf) from this image, so that the new image can
+ *			have access to this. It also means that the original
+ *			memory filename passed to U-Boot will be left intact.
+ *
+ * @param dest		Buffer containing executable image
+ * @param size		Size of buffer
+ */
+int os_jump_to_image(const void *dest, int size);
+
 #endif
diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl
index 331b6664594..5fcef9cebb4 100644
--- a/include/ppc_asm.tmpl
+++ b/include/ppc_asm.tmpl
@@ -135,7 +135,7 @@
 
 #define PLPRCR	0x00000284
 
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
 
 #define HID2		1011
 
diff --git a/include/sdhci.h b/include/sdhci.h
index 74d06ae18a2..32e04f53b54 100644
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -12,6 +12,7 @@
 
 #include <asm/io.h>
 #include <mmc.h>
+#include <fdtdec.h>
 
 /*
  * Controller registers
@@ -244,6 +245,10 @@ struct sdhci_host {
 	const struct sdhci_ops *ops;
 	int index;
 
+	int bus_width;
+	struct fdt_gpio_state pwr_gpio;	/* Power GPIO */
+	struct fdt_gpio_state cd_gpio;		/* Card Detect GPIO */
+
 	void (*set_control_reg)(struct sdhci_host *host);
 	void (*set_clock)(int dev_index, unsigned int div);
 	uint	voltages;
diff --git a/include/sound.h b/include/sound.h
index a06ab853869..155e1b40e28 100644
--- a/include/sound.h
+++ b/include/sound.h
@@ -30,6 +30,15 @@ struct sound_codec_info {
 };
 
 /*
+ * Generates square wave sound data for 1 second
+ *
+ * @param data          data buffer pointer
+ * @param size          size of the buffer
+ * @param freq          frequency of the wave
+ */
+void sound_create_square_wave(unsigned short *data, int size, uint32_t freq);
+
+/*
  * Initialises audio sub system
  * @param blob	Pointer of device tree node or NULL if none.
  * @return	int value 0 for success, -1 for error
diff --git a/include/spi_flash.h b/include/spi_flash.h
index f79f0eacca0..1a112862240 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -52,7 +52,7 @@ enum spi_dual_flash {
  * @sector_size:	Sector size of this device
  * @nr_sectors:		No.of sectors on this device
  * @e_rd_cmd:		Enum list for read commands
- * @flags:		Importent param, for flash specific behaviour
+ * @flags:		Important param, for flash specific behaviour
  */
 struct spi_flash_params {
 	const char *name;
@@ -88,11 +88,11 @@ extern const struct spi_flash_params spi_flash_params_table[];
  * @memory_map:		Address of read-only SPI flash access
  * @read:		Flash read ops: Read len bytes at offset into buf
  *			Supported cmds: Fast Array Read
- * @write:		Flash write ops: Write len bytes from buf into offeset
+ * @write:		Flash write ops: Write len bytes from buf into offset
  *			Supported cmds: Page Program
  * @erase:		Flash erase ops: Erase len bytes from offset
  *			Supported cmds: Sector erase 4K, 32K, 64K
- * return 0 - Sucess, 1 - Failure
+ * return 0 - Success, 1 - Failure
  */
 struct spi_flash {
 	struct spi_slave *spi;
diff --git a/include/usb/s3c_udc.h b/include/usb/s3c_udc.h
index ce3dd2c6bbe..70e48f88ee7 100644
--- a/include/usb/s3c_udc.h
+++ b/include/usb/s3c_udc.h
@@ -10,7 +10,7 @@
 #define __S3C_USB_GADGET
 
 #include <asm/errno.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
 #include <linux/list.h>
diff --git a/include/usb_ether.h b/include/usb_ether.h
index 678c9dff252..35700a21b59 100644
--- a/include/usb_ether.h
+++ b/include/usb_ether.h
@@ -40,23 +40,25 @@ struct ueth_data {
 };
 
 /*
- * Function definitions for each USB ethernet driver go here, bracketed by
- * #ifdef CONFIG_USB_ETHER_xxx...#endif
+ * Function definitions for each USB ethernet driver go here
+ * (declaration is unconditional, compilation is conditional)
  */
-#ifdef CONFIG_USB_ETHER_ASIX
 void asix_eth_before_probe(void);
 int asix_eth_probe(struct usb_device *dev, unsigned int ifnum,
 		      struct ueth_data *ss);
 int asix_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
 		      struct eth_device *eth);
-#endif
 
-#ifdef CONFIG_USB_ETHER_SMSC95XX
+void mcs7830_eth_before_probe(void);
+int mcs7830_eth_probe(struct usb_device *dev, unsigned int ifnum,
+		      struct ueth_data *ss);
+int mcs7830_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
+			 struct eth_device *eth);
+
 void smsc95xx_eth_before_probe(void);
 int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum,
 			struct ueth_data *ss);
 int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
 			struct eth_device *eth);
-#endif
 
 #endif /* __USB_ETHER_H__ */
diff --git a/include/usbroothubdes.h b/include/usbroothubdes.h
new file mode 100644
index 00000000000..adb70cd6af2
--- /dev/null
+++ b/include/usbroothubdes.h
@@ -0,0 +1,129 @@
+/*
+ * USB virtual root hub descriptors
+ *
+ * (C) Copyright 2014
+ * Stephen Warren swarren@wwwdotorg.org
+ *
+ * Based on ohci-hcd.c
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __USBROOTHUBDES_H__
+#define __USBROOTHUBDES_H__
+
+/* Device descriptor */
+static __u8 root_hub_dev_des[] = {
+	0x12,		/* __u8  bLength; */
+	0x01,		/* __u8  bDescriptorType; Device */
+	0x10,		/* __u16 bcdUSB; v1.1 */
+	0x01,
+	0x09,		/* __u8  bDeviceClass; HUB_CLASSCODE */
+	0x00,		/* __u8  bDeviceSubClass; */
+	0x00,		/* __u8  bDeviceProtocol; */
+	0x08,		/* __u8  bMaxPacketSize0; 8 Bytes */
+	0x00,		/* __u16 idVendor; */
+	0x00,
+	0x00,		/* __u16 idProduct; */
+	0x00,
+	0x00,		/* __u16 bcdDevice; */
+	0x00,
+	0x00,		/* __u8  iManufacturer; */
+	0x01,		/* __u8  iProduct; */
+	0x00,		/* __u8  iSerialNumber; */
+	0x01,		/* __u8  bNumConfigurations; */
+};
+
+/* Configuration descriptor */
+static __u8 root_hub_config_des[] = {
+	0x09,		/* __u8  bLength; */
+	0x02,		/* __u8  bDescriptorType; Configuration */
+	0x19,		/* __u16 wTotalLength; */
+	0x00,
+	0x01,		/* __u8  bNumInterfaces; */
+	0x01,		/* __u8  bConfigurationValue; */
+	0x00,		/* __u8  iConfiguration; */
+	0x40,		/* __u8  bmAttributes;
+			 *       Bit 7: Bus-powered
+			 *       6: Self-powered,
+			 *       5 Remote-wakwup,
+			 *       4..0: resvd
+			 */
+	0x00,		/* __u8  MaxPower; */
+	/* interface */
+	0x09,		/* __u8  if_bLength; */
+	0x04,		/* __u8  if_bDescriptorType; Interface */
+	0x00,		/* __u8  if_bInterfaceNumber; */
+	0x00,		/* __u8  if_bAlternateSetting; */
+	0x01,		/* __u8  if_bNumEndpoints; */
+	0x09,		/* __u8  if_bInterfaceClass; HUB_CLASSCODE */
+	0x00,		/* __u8  if_bInterfaceSubClass; */
+	0x00,		/* __u8  if_bInterfaceProtocol; */
+	0x00,		/* __u8  if_iInterface; */
+	/* endpoint */
+	0x07,		/* __u8  ep_bLength; */
+	0x05,		/* __u8  ep_bDescriptorType; Endpoint */
+	0x81,		/* __u8  ep_bEndpointAddress; IN Endpoint 1 */
+	0x03,		/* __u8  ep_bmAttributes; Interrupt */
+	0x02,		/* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
+	0x00,
+	0xff,		/* __u8  ep_bInterval; 255 ms */
+};
+
+#ifdef WANT_USB_ROOT_HUB_HUB_DES
+static unsigned char root_hub_hub_des[] = {
+	0x09,		/* __u8  bLength; */
+	0x29,		/* __u8  bDescriptorType; Hub-descriptor */
+	0x02,		/* __u8  bNbrPorts; */
+	0x00,		/* __u16 wHubCharacteristics; */
+	0x00,
+	0x01,		/* __u8  bPwrOn2pwrGood; 2ms */
+	0x00,		/* __u8  bHubContrCurrent; 0 mA */
+	0x00,		/* __u8  DeviceRemovable; *** 7 Ports max *** */
+	0xff,		/* __u8  PortPwrCtrlMask; *** 7 ports max *** */
+};
+#endif
+
+static unsigned char root_hub_str_index0[] = {
+	0x04,		/* __u8  bLength; */
+	0x03,		/* __u8  bDescriptorType; String-descriptor */
+	0x09,		/* __u8  lang ID */
+	0x04,		/* __u8  lang ID */
+};
+
+static unsigned char root_hub_str_index1[] = {
+	32,		/* __u8  bLength; */
+	0x03,		/* __u8  bDescriptorType; String-descriptor */
+	'U',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	'-',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	'B',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	'o',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	'o',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	't',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	' ',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	'R',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	'o',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	'o',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	't',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	' ',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	'H',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	'u',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	'b',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+};
+
+#endif
author	Stefano Babic <sbabic@denx.de>	2014-04-04 11:35:30 +0200
committer	Stefano Babic <sbabic@denx.de>	2014-04-04 11:35:30 +0200
commit	1cad23c5f471d695bed1e3907e30caee3c2a3056 (patch)
tree	34e035df5db9b327aeae36eff9d0645a915e3177 /include
parent	5dd73bc0a40a4b318195eab871a1f535aad6b43b (diff)
parent	00b132bf34c5be86a108ac7fe8231ad9e97f6de4 (diff)