* Patches by Udi Finkelstein, 2 June 2003:LABEL_2003_06_04_0200

  - Added support for custom keyboards, initialized by defining a
    board-specific drv_keyboard_init as well as defining CONFIG_KEYBOARD .
  - Added support for the RBC823 board.
  - cpu/mpc8xx/lcd.c now automatically calculates the
    Horizontal Pixel Count field.

* Fix alignment problem in BOOTP (dhcp_leasetime option)
  [pointed out by Nicolas Lacressonnière, 2 Jun 2003]

* Patch by Mark Rakes, 14 May 2003:
  add support for Intel e1000 gig cards.

* Patch by Nye Liu, 3 Jun 2003:
  fix critical typo in MAMR definition (include/mpc8xx.h)

* Fix requirement to align U-Boot image on 16 kB boundaries on PPC.

* Patch by Klaus Heydeck, 2 Jun 2003
  Minor changes for KUP4K configuration

10 files changed, 563 insertions, 102 deletions

diff --git a/include/commproc.h b/include/commproc.h
index e9b0ab7771c..d6cf9baadcb 100644
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -1331,6 +1331,7 @@ typedef struct scc_enet {
 
 #if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
     defined(CONFIG_R360MPI) || \
+    defined(CONFIG_RBC823) || \
     defined(CONFIG_TQM823L) || \
     defined(CONFIG_TQM850L) || \
     defined(CONFIG_ETX094)  || \
diff --git a/include/configs/FADS823.h b/include/configs/FADS823.h
index 58d33c77e56..acb2eed2a8a 100644
--- a/include/configs/FADS823.h
+++ b/include/configs/FADS823.h
@@ -58,7 +58,7 @@
 
 /* Wireless 56Khz 4PPM keyboard on SMCx */
 
-/*#define CONFIG_WL_4PPM_KEYBOARD		1 */
+/*#define CONFIG_KEYBOARD		1 */
 #define CONFIG_WL_4PPM_KEYBOARD_SMC	0	/* SMC to use (0 indexed) */
 
 /*
diff --git a/include/configs/GENIETV.h b/include/configs/GENIETV.h
index 99e2cfcb705..ef2cb3a8542 100644
--- a/include/configs/GENIETV.h
+++ b/include/configs/GENIETV.h
@@ -63,7 +63,7 @@
 
 /* Wireless 56Khz 4PPM keyboard on SMCx */
 
-/*#define CONFIG_WL_4PPM_KEYBOARD		0 */
+/*#define CONFIG_KEYBOARD		0 */
 /*#define CONFIG_WL_4PPM_KEYBOARD_SMC	0	/  SMC to use (0 indexed) */
 
 /*
diff --git a/include/configs/KUP4K.h b/include/configs/KUP4K.h
index f68f1e10db2..b924b9c5e35 100644
--- a/include/configs/KUP4K.h
+++ b/include/configs/KUP4K.h
@@ -41,39 +41,41 @@
 #define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
 #undef	CONFIG_8xx_CONS_SMC2
 #undef	CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE		9600	/* console baudrate		*/
+#define CONFIG_BAUDRATE		115200	/* console baudrate		*/
 #if 0
 #define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
 #else
-#define CONFIG_BOOTDELAY	5	/* autoboot after 1 second	*/
+#define CONFIG_BOOTDELAY	1	/* autoboot after 1 second	*/
 #endif
 
 #define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
 
 #define CONFIG_BOARD_TYPES	1	/* support board types		*/
 
-#if 0
-#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
-#endif
 
 #undef	CONFIG_BOOTARGS
 
-#define CONFIG_NFSBOOTCOMMAND \
-    "dhcp ;"\
-	"setenv bootargs root=/dev/nfs ro nfsroot=$(nfsip):$(rootpath) "\
-	"ip=$(ipaddr):$(nfsip):$(gatewayip):"\
-	"$(netmask):heydeck.eva:eth0:off; "\
-    "bootm 100000"
 
-#define CONFIG_RAMBOOTCOMMAND	\
-    "diskboot 100000 0:1; "\
-    "setenv bootargs root=/dev/hda2 panic=1 "\
-	"ip=192.168.0.71:192.168.0.100:192.168.0.2:255.255.255.0; "\
-    "bootm"
+#define	CONFIG_EXTRA_ENV_SETTINGS					  \
+"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off panic=1;\
+ diskboot 200000 0:1; bootm 200000\0"                                     \
+"slot_b_boot=setenv bootargs root=/dev/hda2 ip=off panic=1;\
+ diskboot 200000 2:1; bootm 200000\0"                                     \
+"nfs_boot=dhcp; run nfsargs addip; bootm 200000\0"                        \
+"panic_boot=echo No Bootdevice !!! reset\0"                               \
+"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(nfsip):$(rootpath)\0" \
+"ramargs=setenv bootargs root=/dev/ram rw\0"			          \
+"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(nfsip):$(gatewayip)\
+:$(netmask):$(hostname):$(netdev):off panic=1\0"                          \
+"netdev=eth0\0"                                                           \
+"load=tftp 200000 bootloader.bitmap;tftp 100000 u-boot.bin\0"             \
+"update=protect off 1:0-8;era 1:0-8;cp.b 100000 40000000 $(filesize);\
+cp.b 200000 40040000 14000\0"                                                   \
+"nfsip=192.168.2.19\0"
+
+#define CONFIG_BOOTCOMMAND  \
+    "run slot_a_boot;run slot_b_boot;run nfs_boot;run panic_boot"
 
-#define CONFIG_BOOTCOMMAND	\
-    "run ramboot "\
-    "run nfsboot"
 
 #define CONFIG_MISC_INIT_R  1
 
@@ -124,12 +126,14 @@
 #define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+#define	CFG_LOAD_ADDR		0x200000	/* default load address	*/
 
 #define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
 
 #define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
+#define CFG_CONSOLE_INFO_QUIET 1
+
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
@@ -250,7 +254,7 @@
  *
  * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
  */
-#define CFG_PLPRCR ( (3-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
+#define CFG_PLPRCR ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -259,7 +263,7 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF00
-#define CFG_SCCR	( SCCR_TBS  |   SCCR_EBDF00 |  \
+#define CFG_SCCR	(SCCR_TBS | SCCR_EBDF01 |  \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
@@ -271,7 +275,7 @@
  */
 
 /* KUP4K use both slots, SLOT_A as "primary". */
-#define	CONFIG_PCMCIA_SLOT_A 1	
+#define	CONFIG_PCMCIA_SLOT_A 1
 
 #define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
 #define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
@@ -428,12 +432,12 @@
 #define BOOTFLAG_WARM	0x02		/* Software reboot			*/
 
 
-#if NOT_USED_FOR_NOW
+
 #define CONFIG_AUTOBOOT_KEYED		/* use key strings to stop autoboot */
 #if 0
 #define CONFIG_AUTOBOOT_PROMPT		"Boote in %d Sekunden - stop mit \"2\"\n"
 #endif
-#define CONFIG_AUTOBOOT_STOP_STR	"2" /* easy to stop for now */
-#endif /* NOT_USED_FOR_NOW */
+#define CONFIG_AUTOBOOT_STOP_STR	"." /* easy to stop for now */
+
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h
new file mode 100644
index 00000000000..08eed276c22
--- /dev/null
+++ b/include/configs/RBC823.h
@@ -0,0 +1,418 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified by Udi Finkelstein udif@udif.com
+ * For the RBC823 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
+#define CONFIG_RBC823		1	/* ...on a RBC823 module	*/
+
+
+#if 0
+#define DEBUG			1
+#define CONFIG_LAST_STAGE_INIT
+#endif
+#define CONFIG_KEYBOARD		1	/* This board has a custom keybpard */
+#define CONFIG_LCD		1	/* use LCD controller ...	*/
+#define CONFIG_HITACHI_SP19X001_Z1A	/* The LCD type we use */
+
+#define	CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2		*/
+#undef	CONFIG_8xx_CONS_SMC1
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+#if 1
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+#define CONFIG_8xx_GCLK_FREQ    48000000L
+
+#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"bootp; " 								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " 	\
+	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " 	\
+	"bootm"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#undef CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#undef	CONFIG_RTC_MPC8xx		/* don't use internal RTC of MPC8xx (no battery)	*/
+
+#define CONFIG_HARD_I2C
+#define CFG_I2C_SPEED 40000
+#define CFG_I2C_SLAVE 0xfe
+#define CFG_I2C_EEPROM_ADDR       0x50
+#define CFG_I2C_EEPROM_ADDR_LEN   1
+#define CFG_EEPROM_WRITE_BITS        4
+#define CFG_EEPROM_WRITE_DELAY_MS   10
+
+#define CONFIG_COMMANDS	      ( CFG_CMD_ALL	& \
+				~CFG_CMD_PCMCIA	& \
+				~CFG_CMD_IDE	& \
+				~CFG_CMD_PCI	& \
+				~CFG_CMD_FDC	& \
+				~CFG_CMD_HWFLOW	& \
+				~CFG_CMD_FDOS	& \
+				~CFG_CMD_SCSI	& \
+				~CFG_CMD_SETGETDCR	& \
+				~CFG_CMD_BSP	& \
+				~CFG_CMD_USB	& \
+				~CFG_CMD_VFD	& \
+				~CFG_CMD_SPI	& \
+				/* ~CFG_CMD_I2C	& */ \
+				~CFG_CMD_IRQ	& \
+				~CFG_CMD_NAND	& \
+				~CFG_CMD_JFFS2	& \
+				~CFG_CMD_DTT	& \
+				~CFG_CMD_MII	& \
+				/*~CFG_CMD_NET	&*/ \
+				/*~CFG_CMD_ELF	&*/ \
+				/* ~CFG_CMD_EEPROM	& */ \
+				~CFG_CMD_DATE	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x0100000	/* default load address	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFF00000
+#if defined(DEBUG)
+#define	CFG_MONITOR_LEN		(384 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CFG_MONITOR_LEN		(384 << 10)	/* Reserve 192 kB for Monitor	*/
+#endif
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define	CFG_ENV_OFFSET		0x10000	/*   Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x10000	/* Total Size of Environment Sector	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+/*
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+*/
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWRI | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_FRC)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ */
+
+/*
+ * for 48 MHz, we use a 4 MHz clock * 12
+ */
+#define CFG_PLPRCR							\
+		( (12-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_LOLRE )
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	(SCCR_RTDIV   | SCCR_RTSEL    | SCCR_CRQEN    | \
+		         SCCR_PRQEN   | SCCR_EBDF00   | \
+		         SCCR_COM01   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD001 | \
+			 SCCR_DFALCD00)
+
+#ifdef NOT_USED
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define	CONFIG_IDE_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_PCMCIA		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+#endif
+
+/************************************************************
+ * Disk-On-Chip configuration
+ ************************************************************/
+#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices		*/
+#define CFG_DOC_SHORT_TIMEOUT
+#define CFG_DOC_SUPPORT_2000
+#define CFG_DOC_SUPPORT_MILLENNIUM
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define	CFG_DER	0x2002000F*/
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFFF00000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x04000000	/* D.O.C Millenium	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_PRELIM_OR_AM	0xFFF80000	/* OR addr mask */
+
+/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 7, EHTR = 1	*/
+#define CFG_OR_TIMING_FLASH  (OR_ACS_DIV1 | OR_BI | OR_SCY_7_CLK | OR_EHTR)
+
+#define CFG_OR_TIMING_MSYS   (OR_ACS_DIV1 | OR_BI)
+
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
+
+#define CFG_OR1_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_MSYS)
+#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | \
+		          BR_PS_8 | BR_V)
+
+/*
+ * BR4 and OR4 (SDRAM)
+ *
+ */
+#define SDRAM_BASE4_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/*
+ * SDRAM timing:
+ */
+#define CFG_OR_TIMING_SDRAM	(OR_CSNT_SAM)
+
+#define CFG_OR4_PRELIM	(~(SDRAM_MAX_SIZE-1) | CFG_OR_TIMING_SDRAM )
+#define CFG_BR4_PRELIM	((SDRAM_BASE4_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA	187		/* start with divider for 48 MHz	*/
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/devices.h b/include/devices.h
index 4f46e17ac7b..a27c4e83f1e 100644
--- a/include/devices.h
+++ b/include/devices.h
@@ -102,8 +102,8 @@ int	drv_vfd_init (void);
 #if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
 int	drv_video_init (void);
 #endif
-#ifdef CONFIG_WL_4PPM_KEYBOARD
-int	drv_wlkbd_init (void);
+#ifdef CONFIG_KEYBOARD
+int	drv_keyboard_init (void);
 #endif
 
 #endif	/* _DEVICES_H_ */
diff --git a/include/lcd.h b/include/lcd.h
index d063c9c8b56..e52a625470c 100644
--- a/include/lcd.h
+++ b/include/lcd.h
@@ -29,6 +29,12 @@
 #ifndef _LCD_H_
 #define _LCD_H_
 
+#if defined(CONFIG_RBC823)
+void	lcd_disable (void);
+#endif
+
+extern char lcd_is_enabled;
+
 /* Video functions */
 
 int	lcd_init	(void *lcdbase);
diff --git a/include/mpc8xx.h b/include/mpc8xx.h
index a28c6ace26d..ef6d3f7dd95 100644
--- a/include/mpc8xx.h
+++ b/include/mpc8xx.h
@@ -40,8 +40,8 @@
 /*-----------------------------------------------------------------------
  * SYPCR - System Protection Control Register				11-9
  */
-#define SYPCR_SWTC	0xffff0000	/* Software Watchdog Timer Count	*/
-#define SYPCR_BMT	0x0000ff00	/* Bus Monitor Timing			*/
+#define SYPCR_SWTC	0xFFFF0000	/* Software Watchdog Timer Count	*/
+#define SYPCR_BMT	0x0000FF00	/* Bus Monitor Timing			*/
 #define SYPCR_BME	0x00000080	/* Bus Monitor Enable			*/
 #define SYPCR_SWF	0x00000008	/* Software Watchdog Freeze		*/
 #define SYPCR_SWE	0x00000004	/* Software Watchdog Enable		*/
@@ -78,7 +78,7 @@
 #define SIUMCR_MLRC00	0x00000000	/* Multi Level Reserva. Ctrl		*/
 #define SIUMCR_MLRC01	0x00000400	/* - " -				*/
 #define SIUMCR_MLRC10	0x00000800	/* - " -				*/
-#define SIUMCR_MLRC11	0x00000c00	/* - " -				*/
+#define SIUMCR_MLRC11	0x00000C00	/* - " -				*/
 #define SIUMCR_AEME	0x00000200	/* Asynchro External Master		*/
 #define SIUMCR_SEME	0x00000100	/* Synchro External Master		*/
 #define SIUMCR_BSC	0x00000080	/* Byte Select Configuration		*/
@@ -120,7 +120,7 @@
 /*-----------------------------------------------------------------------
  * PLPRCR - PLL, Low-Power, and Reset Control Register			15-30
  */
-#define PLPRCR_MF_MSK	0xfff00000	/* Multiplication factor bits		*/
+#define PLPRCR_MF_MSK	0xFFF00000	/* Multiplication factor bits		*/
 #define PLPRCR_MF_SHIFT 0x00000014	/* Multiplication factor shift value	*/
 #define PLPRCR_SPLSS	0x00008000	/* SPLL Lock Status Sticky bit		*/
 #define PLPRCR_TEXPS	0x00004000	/* TEXP Status				*/
@@ -182,24 +182,24 @@
 /*-----------------------------------------------------------------------
  * BR - Memory Controler: Base Register					16-9
  */
-#define BR_BA_MSK	0xffff8000	/* Base Address Mask			*/
+#define BR_BA_MSK	0xFFFF8000	/* Base Address Mask			*/
 #define BR_AT_MSK	0x00007000	/* Address Type Mask			*/
-#define BR_PS_MSK	0x00000c00	/* Port Size Mask			*/
+#define BR_PS_MSK	0x00000C00	/* Port Size Mask			*/
 #define BR_PS_32	0x00000000	/* 32 bit port size			*/
 #define BR_PS_16	0x00000800	/* 16 bit port size			*/
 #define BR_PS_8		0x00000400	/*  8 bit port size			*/
 #define BR_PARE		0x00000200	/* Parity Enable			*/
 #define BR_WP		0x00000100	/* Write Protect			*/
-#define BR_MS_MSK	0x000000c0	/* Machine Select Mask			*/
+#define BR_MS_MSK	0x000000C0	/* Machine Select Mask			*/
 #define BR_MS_GPCM	0x00000000	/* G.P.C.M. Machine Select		*/
 #define BR_MS_UPMA	0x00000080	/* U.P.M.A Machine Select		*/
-#define BR_MS_UPMB	0x000000c0	/* U.P.M.B Machine Select		*/
+#define BR_MS_UPMB	0x000000C0	/* U.P.M.B Machine Select		*/
 #define BR_V		0x00000001	/* Bank Valid				*/
 
 /*-----------------------------------------------------------------------
  * OR - Memory Controler: Option Register				16-11
  */
-#define OR_AM_MSK	0xffff8000	/* Address Mask Mask			*/
+#define OR_AM_MSK	0xFFFF8000	/* Address Mask Mask			*/
 #define OR_ATM_MSK	0x00007000	/* Address Type Mask Mask		*/
 #define OR_CSNT_SAM	0x00000800	/* Chip Select Negation Time/ Start	*/
 					/* Address Multiplex			*/
@@ -210,7 +210,7 @@
 #define OR_G5LA		0x00000400	/* Output #GPL5 on #GPL_A5		*/
 #define OR_G5LS		0x00000200	/* Drive #GPL high on falling edge of...*/
 #define OR_BI		0x00000100	/* Burst inhibit			*/
-#define OR_SCY_MSK	0x000000f0	/* Cycle Lenght in Clocks		*/
+#define OR_SCY_MSK	0x000000F0	/* Cycle Lenght in Clocks		*/
 #define OR_SCY_0_CLK	0x00000000	/* 0 clock cycles wait states		*/
 #define OR_SCY_1_CLK	0x00000010	/* 1 clock cycles wait states		*/
 #define OR_SCY_2_CLK	0x00000020	/* 2 clock cycles wait states		*/
@@ -221,12 +221,12 @@
 #define OR_SCY_7_CLK	0x00000070	/* 7 clock cycles wait states		*/
 #define OR_SCY_8_CLK	0x00000080	/* 8 clock cycles wait states		*/
 #define OR_SCY_9_CLK	0x00000090	/* 9 clock cycles wait states		*/
-#define OR_SCY_10_CLK	0x000000a0	/* 10 clock cycles wait states		*/
-#define OR_SCY_11_CLK	0x000000b0	/* 11 clock cycles wait states		*/
-#define OR_SCY_12_CLK	0x000000c0	/* 12 clock cycles wait states		*/
-#define OR_SCY_13_CLK	0x000000d0	/* 13 clock cycles wait states		*/
-#define OR_SCY_14_CLK	0x000000e0	/* 14 clock cycles wait states		*/
-#define OR_SCY_15_CLK	0x000000f0	/* 15 clock cycles wait states		*/
+#define OR_SCY_10_CLK	0x000000A0	/* 10 clock cycles wait states		*/
+#define OR_SCY_11_CLK	0x000000B0	/* 11 clock cycles wait states		*/
+#define OR_SCY_12_CLK	0x000000C0	/* 12 clock cycles wait states		*/
+#define OR_SCY_13_CLK	0x000000D0	/* 13 clock cycles wait states		*/
+#define OR_SCY_14_CLK	0x000000E0	/* 14 clock cycles wait states		*/
+#define OR_SCY_15_CLK	0x000000F0	/* 15 clock cycles wait states		*/
 #define OR_SETA		0x00000008	/* External Transfer Acknowledge	*/
 #define OR_TRLX		0x00000004	/* Timing Relaxed			*/
 #define OR_EHTR		0x00000002	/* Extended Hold Time on Read		*/
@@ -235,7 +235,7 @@
 /*-----------------------------------------------------------------------
  * MPTPR - Memory Periodic Timer Prescaler Register			16-17
  */
-#define MPTPR_PTP_MSK	0xff00		/* Periodic Timers Prescaler Mask	*/
+#define MPTPR_PTP_MSK	0xFF00		/* Periodic Timers Prescaler Mask	*/
 #define MPTPR_PTP_DIV2	0x2000		/* BRGCLK divided by 2			*/
 #define MPTPR_PTP_DIV4	0x1000		/* BRGCLK divided by 4			*/
 #define MPTPR_PTP_DIV8	0x0800		/* BRGCLK divided by 8			*/
@@ -265,7 +265,7 @@
 /*-----------------------------------------------------------------------
  * Machine A Mode Register						16-13
  */
-#define MAMR_PTA_MSK	0xff000000	/* Periodic Timer A period mask		*/
+#define MAMR_PTA_MSK	0xFF000000	/* Periodic Timer A period mask		*/
 #define MAMR_PTA_SHIFT	0x00000018	/* Periodic Timer A period shift	*/
 #define MAMR_PTAE	0x00800000	/* Periodic Timer A Enable		*/
 #define MAMR_AMA_MSK	0x00700000	/* Addess Multiplexing size A		*/
@@ -280,17 +280,17 @@
 #define MAMR_DSA_2_CYCL 0x00020000	/* 2 cycle Disable Period		*/
 #define MAMR_DSA_3_CYCL 0x00040000	/* 3 cycle Disable Period		*/
 #define MAMR_DSA_4_CYCL 0x00060000	/* 4 cycle Disable Period		*/
-#define MAMR_G0CLA_MSK	0x0000e000	/* General Line 0 Control A		*/
+#define MAMR_G0CLA_MSK	0x0000E000	/* General Line 0 Control A		*/
 #define MAMR_G0CLA_A12	0x00000000	/* General Line 0 : A12			*/
 #define MAMR_G0CLA_A11	0x00002000	/* General Line 0 : A11			*/
 #define MAMR_G0CLA_A10	0x00004000	/* General Line 0 : A10			*/
 #define MAMR_G0CLA_A9	0x00006000	/* General Line 0 : A9			*/
 #define MAMR_G0CLA_A8	0x00008000	/* General Line 0 : A8			*/
-#define MAMR_G0CLA_A7	0x0000a000	/* General Line 0 : A7			*/
-#define MAMR_G0CLA_A6	0x0000c000	/* General Line 0 : A6			*/
-#define MAMR_G0CLA_A5	0x0000e000	/* General Line 0 : A5			*/
+#define MAMR_G0CLA_A7	0x0000A000	/* General Line 0 : A7			*/
+#define MAMR_G0CLA_A6	0x0000C000	/* General Line 0 : A6			*/
+#define MAMR_G0CLA_A5	0x0000E000	/* General Line 0 : A5			*/
 #define MAMR_GPL_A4DIS	0x00001000	/* GPL_A4 ouput line Disable		*/
-#define MAMR_RLFA_MSK	0x00000f00	/* Read Loop Field A mask		*/
+#define MAMR_RLFA_MSK	0x00000F00	/* Read Loop Field A mask		*/
 #define MAMR_RLFA_1X	0x00000100	/* The Read Loop is executed 1 time	*/
 #define MAMR_RLFA_2X	0x00000200	/* The Read Loop is executed 2 times	*/
 #define MAMR_RLFA_3X	0x00000300	/* The Read Loop is executed 3 times	*/
@@ -300,14 +300,14 @@
 #define MAMR_RLFA_7X	0x00000700	/* The Read Loop is executed 7 times	*/
 #define MAMR_RLFA_8X	0x00000800	/* The Read Loop is executed 8 times	*/
 #define MAMR_RLFA_9X	0x00000900	/* The Read Loop is executed 9 times	*/
-#define MAMR_RLFA_10X	0x00000a00	/* The Read Loop is executed 10 times	*/
-#define MAMR_RLFA_11X	0x00000b00	/* The Read Loop is executed 11 times	*/
-#define MAMR_RLFA_12X	0x00000c00	/* The Read Loop is executed 12 times	*/
-#define MAMR_RLFA_13X	0x00000d00	/* The Read Loop is executed 13 times	*/
-#define MAMR_RLFA_14X	0x00000e00	/* The Read Loop is executed 14 times	*/
-#define MAMR_RLFA_15X	0x00000f00	/* The Read Loop is executed 15 times	*/
+#define MAMR_RLFA_10X	0x00000A00	/* The Read Loop is executed 10 times	*/
+#define MAMR_RLFA_11X	0x00000B00	/* The Read Loop is executed 11 times	*/
+#define MAMR_RLFA_12X	0x00000C00	/* The Read Loop is executed 12 times	*/
+#define MAMR_RLFA_13X	0x00000D00	/* The Read Loop is executed 13 times	*/
+#define MAMR_RLFA_14X	0x00000E00	/* The Read Loop is executed 14 times	*/
+#define MAMR_RLFA_15X	0x00000F00	/* The Read Loop is executed 15 times	*/
 #define MAMR_RLFA_16X	0x00000000	/* The Read Loop is executed 16 times	*/
-#define MAMR_WLFA_MSK	0x000000f0	/* Write Loop Field A mask		*/
+#define MAMR_WLFA_MSK	0x000000F0	/* Write Loop Field A mask		*/
 #define MAMR_WLFA_1X	0x00000010	/* The Write Loop is executed 1 time	*/
 #define MAMR_WLFA_2X	0x00000020	/* The Write Loop is executed 2 times	*/
 #define MAMR_WLFA_3X	0x00000030	/* The Write Loop is executed 3 times	*/
@@ -317,14 +317,14 @@
 #define MAMR_WLFA_7X	0x00000070	/* The Write Loop is executed 7 times	*/
 #define MAMR_WLFA_8X	0x00000080	/* The Write Loop is executed 8 times	*/
 #define MAMR_WLFA_9X	0x00000090	/* The Write Loop is executed 9 times	*/
-#define MAMR_WLFA_10X	0x000000a0	/* The Write Loop is executed 10 times	*/
-#define MAMR_WLFA_11X	0x000000b0	/* The Write Loop is executed 11 times	*/
-#define MAMR_WLFA_12X	0x000000c0	/* The Write Loop is executed 12 times	*/
-#define MAMR_WLFA_13X	0x000000d0	/* The Write Loop is executed 13 times	*/
-#define MAMR_WLFA_14X	0x000000e0	/* The Write Loop is executed 14 times	*/
-#define MAMR_WLFA_15X	0x000000f0	/* The Write Loop is executed 15 times	*/
+#define MAMR_WLFA_10X	0x000000A0	/* The Write Loop is executed 10 times	*/
+#define MAMR_WLFA_11X	0x000000B0	/* The Write Loop is executed 11 times	*/
+#define MAMR_WLFA_12X	0x000000C0	/* The Write Loop is executed 12 times	*/
+#define MAMR_WLFA_13X	0x000000D0	/* The Write Loop is executed 13 times	*/
+#define MAMR_WLFA_14X	0x000000E0	/* The Write Loop is executed 14 times	*/
+#define MAMR_WLFA_15X	0x000000F0	/* The Write Loop is executed 15 times	*/
 #define MAMR_WLFA_16X	0x00000000	/* The Write Loop is executed 16 times	*/
-#define MAMR_TLFA_MSK	0x0000000f	/* Timer Loop Field A mask		*/
+#define MAMR_TLFA_MSK	0x0000000F	/* Timer Loop Field A mask		*/
 #define MAMR_TLFA_1X	0x00000001	/* The Timer Loop is executed 1 time	*/
 #define MAMR_TLFA_2X	0x00000002	/* The Timer Loop is executed 2 times	*/
 #define MAMR_TLFA_3X	0x00000003	/* The Timer Loop is executed 3 times	*/
@@ -334,18 +334,18 @@
 #define MAMR_TLFA_7X	0x00000007	/* The Timer Loop is executed 7 times	*/
 #define MAMR_TLFA_8X	0x00000008	/* The Timer Loop is executed 8 times	*/
 #define MAMR_TLFA_9X	0x00000009	/* The Timer Loop is executed 9 times	*/
-#define MAMR_TLFA_10X	0x0000000a	/* The Timer Loop is executed 10 times	*/
-#define MAMR_TLFA_11X	0x0000000b	/* The Timer Loop is executed 11 times	*/
-#define MAMR_TLFA_12X	0x0000000c	/* The Timer Loop is executed 12 times	*/
-#define MAMR_TLFA_13X	0x0000000d	/* The Timer Loop is executed 13 times	*/
-#define MAMR_TLFA_14X	0x0000000e	/* The Timer Loop is executed 14 times	*/
-#define MAMR_TLFA_15X	0x0000000f	/* The Timer Loop is executed 15 times	*/
+#define MAMR_TLFA_10X	0x0000000A	/* The Timer Loop is executed 10 times	*/
+#define MAMR_TLFA_11X	0x0000000B	/* The Timer Loop is executed 11 times	*/
+#define MAMR_TLFA_12X	0x0000000C	/* The Timer Loop is executed 12 times	*/
+#define MAMR_TLFA_13X	0x0000000D	/* The Timer Loop is executed 13 times	*/
+#define MAMR_TLFA_14X	0x0000000E	/* The Timer Loop is executed 14 times	*/
+#define MAMR_TLFA_15X	0x0000000F	/* The Timer Loop is executed 15 times	*/
 #define MAMR_TLFA_16X	0x00000000	/* The Timer Loop is executed 16 times	*/
 
 /*-----------------------------------------------------------------------
  * Machine B Mode Register						16-13
  */
-#define MAMR_PTB_MSK	0xff000000	/* Periodic Timer B period mask		*/
+#define MAMR_PTB_MSK	0xFF000000	/* Periodic Timer B period mask		*/
 #define MAMR_PTB_SHIFT	0x00000018	/* Periodic Timer B period shift	*/
 #define MAMR_PTBE	0x00800000	/* Periodic Timer B Enable		*/
 #define MAMR_AMB_MSK	0x00700000	/* Addess Multiplex size B		*/
@@ -360,17 +360,17 @@
 #define MAMR_DSB_2_CYCL 0x00020000	/* 2 cycle Disable Period		*/
 #define MAMR_DSB_3_CYCL 0x00040000	/* 3 cycle Disable Period		*/
 #define MAMR_DSB_4_CYCL 0x00060000	/* 4 cycle Disable Period		*/
-#define MAMR_G0CLB_MSK	0x0000e000	/* General Line 0 Control B		*/
+#define MAMR_G0CLB_MSK	0x0000E000	/* General Line 0 Control B		*/
 #define MAMR_G0CLB_A12	0x00000000	/* General Line 0 : A12			*/
 #define MAMR_G0CLB_A11	0x00002000	/* General Line 0 : A11			*/
 #define MAMR_G0CLB_A10	0x00004000	/* General Line 0 : A10			*/
 #define MAMR_G0CLB_A9	0x00006000	/* General Line 0 : A9			*/
 #define MAMR_G0CLB_A8	0x00008000	/* General Line 0 : A8			*/
-#define MAMR_G0CLB_A7	0x0000a000	/* General Line 0 : A7			*/
-#define MAMR_G0CLB_A6	0x0000b000	/* General Line 0 : A6			*/
-#define MAMR_G0CLB_A5	0x0000e000	/* General Line 0 : A5			*/
+#define MAMR_G0CLB_A7	0x0000A000	/* General Line 0 : A7			*/
+#define MAMR_G0CLB_A6	0x0000C000	/* General Line 0 : A6			*/
+#define MAMR_G0CLB_A5	0x0000E000	/* General Line 0 : A5			*/
 #define MAMR_GPL_B4DIS	0x00001000	/* GPL_B4 ouput line Disable		*/
-#define MAMR_RLFB_MSK	0x00000f00	/* Read Loop Field B mask		*/
+#define MAMR_RLFB_MSK	0x00000F00	/* Read Loop Field B mask		*/
 #define MAMR_RLFB_1X	0x00000100	/* The Read Loop is executed 1 time	*/
 #define MAMR_RLFB_2X	0x00000200	/* The Read Loop is executed 2 times	*/
 #define MAMR_RLFB_3X	0x00000300	/* The Read Loop is executed 3 times	*/
@@ -380,14 +380,14 @@
 #define MAMR_RLFB_7X	0x00000700	/* The Read Loop is executed 7 times	*/
 #define MAMR_RLFB_8X	0x00000800	/* The Read Loop is executed 8 times	*/
 #define MAMR_RLFB_9X	0x00000900	/* The Read Loop is executed 9 times	*/
-#define MAMR_RLFB_10X	0x00000a00	/* The Read Loop is executed 10 times	*/
-#define MAMR_RLFB_11X	0x00000b00	/* The Read Loop is executed 11 times	*/
-#define MAMR_RLFB_12X	0x00000c00	/* The Read Loop is executed 12 times	*/
-#define MAMR_RLFB_13X	0x00000d00	/* The Read Loop is executed 13 times	*/
-#define MAMR_RLFB_14X	0x00000e00	/* The Read Loop is executed 14 times	*/
+#define MAMR_RLFB_10X	0x00000A00	/* The Read Loop is executed 10 times	*/
+#define MAMR_RLFB_11X	0x00000B00	/* The Read Loop is executed 11 times	*/
+#define MAMR_RLFB_12X	0x00000C00	/* The Read Loop is executed 12 times	*/
+#define MAMR_RLFB_13X	0x00000D00	/* The Read Loop is executed 13 times	*/
+#define MAMR_RLFB_14X	0x00000E00	/* The Read Loop is executed 14 times	*/
 #define MAMR_RLFB_15X	0x00000f00	/* The Read Loop is executed 15 times	*/
 #define MAMR_RLFB_16X	0x00000000	/* The Read Loop is executed 16 times	*/
-#define MAMR_WLFB_MSK	0x000000f0	/* Write Loop Field B mask		*/
+#define MAMR_WLFB_MSK	0x000000F0	/* Write Loop Field B mask		*/
 #define MAMR_WLFB_1X	0x00000010	/* The Write Loop is executed 1 time	*/
 #define MAMR_WLFB_2X	0x00000020	/* The Write Loop is executed 2 times	*/
 #define MAMR_WLFB_3X	0x00000030	/* The Write Loop is executed 3 times	*/
@@ -397,14 +397,14 @@
 #define MAMR_WLFB_7X	0x00000070	/* The Write Loop is executed 7 times	*/
 #define MAMR_WLFB_8X	0x00000080	/* The Write Loop is executed 8 times	*/
 #define MAMR_WLFB_9X	0x00000090	/* The Write Loop is executed 9 times	*/
-#define MAMR_WLFB_10X	0x000000a0	/* The Write Loop is executed 10 times	*/
-#define MAMR_WLFB_11X	0x000000b0	/* The Write Loop is executed 11 times	*/
-#define MAMR_WLFB_12X	0x000000c0	/* The Write Loop is executed 12 times	*/
-#define MAMR_WLFB_13X	0x000000d0	/* The Write Loop is executed 13 times	*/
-#define MAMR_WLFB_14X	0x000000e0	/* The Write Loop is executed 14 times	*/
-#define MAMR_WLFB_15X	0x000000f0	/* The Write Loop is executed 15 times	*/
+#define MAMR_WLFB_10X	0x000000A0	/* The Write Loop is executed 10 times	*/
+#define MAMR_WLFB_11X	0x000000B0	/* The Write Loop is executed 11 times	*/
+#define MAMR_WLFB_12X	0x000000C0	/* The Write Loop is executed 12 times	*/
+#define MAMR_WLFB_13X	0x000000D0	/* The Write Loop is executed 13 times	*/
+#define MAMR_WLFB_14X	0x000000E0	/* The Write Loop is executed 14 times	*/
+#define MAMR_WLFB_15X	0x000000F0	/* The Write Loop is executed 15 times	*/
 #define MAMR_WLFB_16X	0x00000000	/* The Write Loop is executed 16 times	*/
-#define MAMR_TLFB_MSK	0x0000000f	/* Timer Loop Field B mask		*/
+#define MAMR_TLFB_MSK	0x0000000F	/* Timer Loop Field B mask		*/
 #define MAMR_TLFB_1X	0x00000001	/* The Timer Loop is executed 1 time	*/
 #define MAMR_TLFB_2X	0x00000002	/* The Timer Loop is executed 2 times	*/
 #define MAMR_TLFB_3X	0x00000003	/* The Timer Loop is executed 3 times	*/
@@ -414,12 +414,12 @@
 #define MAMR_TLFB_7X	0x00000007	/* The Timer Loop is executed 7 times	*/
 #define MAMR_TLFB_8X	0x00000008	/* The Timer Loop is executed 8 times	*/
 #define MAMR_TLFB_9X	0x00000009	/* The Timer Loop is executed 9 times	*/
-#define MAMR_TLFB_10X	0x0000000a	/* The Timer Loop is executed 10 times	*/
-#define MAMR_TLFB_11X	0x0000000b	/* The Timer Loop is executed 11 times	*/
-#define MAMR_TLFB_12X	0x0000000c	/* The Timer Loop is executed 12 times	*/
-#define MAMR_TLFB_13X	0x0000000d	/* The Timer Loop is executed 13 times	*/
-#define MAMR_TLFB_14X	0x0000000e	/* The Timer Loop is executed 14 times	*/
-#define MAMR_TLFB_15X	0x0000000f	/* The Timer Loop is executed 15 times	*/
+#define MAMR_TLFB_10X	0x0000000A	/* The Timer Loop is executed 10 times	*/
+#define MAMR_TLFB_11X	0x0000000B	/* The Timer Loop is executed 11 times	*/
+#define MAMR_TLFB_12X	0x0000000C	/* The Timer Loop is executed 12 times	*/
+#define MAMR_TLFB_13X	0x0000000D	/* The Timer Loop is executed 13 times	*/
+#define MAMR_TLFB_14X	0x0000000E	/* The Timer Loop is executed 14 times	*/
+#define MAMR_TLFB_15X	0x0000000F	/* The Timer Loop is executed 15 times	*/
 #define MAMR_TLFB_16X	0x00000000	/* The Timer Loop is executed 16 times	*/
 
 /*-----------------------------------------------------------------------
@@ -446,13 +446,13 @@
 /*-----------------------------------------------------------------------
  * Timer Mode Register							18-9
  */
-#define TMR_PS_MSK              0xff00  /* Prescaler Value 			*/
+#define TMR_PS_MSK              0xFF00  /* Prescaler Value 			*/
 #define TMR_PS_SHIFT                 8  /* Prescaler position			*/
-#define TMR_CE_MSK              0x00c0  /* Capture Edge and Enable Interrupt	*/
+#define TMR_CE_MSK              0x00C0  /* Capture Edge and Enable Interrupt	*/
 #define TMR_CE_INTR_DIS         0x0000  /* Disable Interrupt on capture event 	*/
 #define TMR_CE_RISING           0x0040  /* Capture on Rising TINx edge only 	*/
 #define TMR_CE_FALLING          0x0080  /* Capture on Falling TINx edge only 	*/
-#define TMR_CE_ANY              0x00c0  /* Capture on any TINx edge 		*/
+#define TMR_CE_ANY              0x00C0  /* Capture on any TINx edge 		*/
 #define TMR_OM                  0x0020  /* Output Mode 				*/
 #define TMR_ORI                 0x0010  /* Output Reference Interrupt Enable	*/
 #define TMR_FRR                 0x0008  /* Free Run/Restart 			*/
@@ -505,7 +505,7 @@
 
 #define PCMCIA_VS1(slot)	(0x80000000 >> (slot << 4))
 #define PCMCIA_VS2(slot)	(0x40000000 >> (slot << 4))
-#define PCMCIA_VS_MASK(slot)	(0xc0000000 >> (slot << 4))
+#define PCMCIA_VS_MASK(slot)	(0xC0000000 >> (slot << 4))
 #define PCMCIA_VS_SHIFT(slot)	(30 - (slot << 4))
 
 #define PCMCIA_WP(slot)		(0x20000000 >> (slot << 4))
diff --git a/include/pci_ids.h b/include/pci_ids.h
index f4fc52fb27c..2ea48943764 100644
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
@@ -1367,6 +1367,19 @@
 #define PCI_DEVICE_ID_INTEL_82430	0x0486
 #define PCI_DEVICE_ID_INTEL_82434	0x04a3
 #define PCI_DEVICE_ID_INTEL_I960	0x0960
+#define PCI_DEVICE_ID_INTEL_82542       	0x1000
+#define PCI_DEVICE_ID_INTEL_82543GC_FIBER  	0x1001
+#define PCI_DEVICE_ID_INTEL_82543GC_COPPER 	0x1004
+#define PCI_DEVICE_ID_INTEL_82544EI_COPPER 	0x1008
+#define PCI_DEVICE_ID_INTEL_82544EI_FIBER 	0x1009
+#define PCI_DEVICE_ID_INTEL_82544GC_COPPER 	0x100C
+#define PCI_DEVICE_ID_INTEL_82544GC_LOM   	0x100D
+#define PCI_DEVICE_ID_INTEL_82540EM		0x100E
+#define PCI_DEVICE_ID_INTEL_82545EM_COPPER	0x100F
+#define PCI_DEVICE_ID_INTEL_82546EB_COPPER	0x1010
+#define PCI_DEVICE_ID_INTEL_82545EM_FIBER	0x1011
+#define PCI_DEVICE_ID_INTEL_82546EB_FIBER	0x1012
+#define PCI_DEVICE_ID_INTEL_82540EM_LOM		0x1015
 #define PCI_DEVICE_ID_INTEL_82559	0x1030
 #define PCI_DEVICE_ID_INTEL_82559ER	0x1209
 #define PCI_DEVICE_ID_INTEL_82092AA_0	0x1221
diff --git a/include/status_led.h b/include/status_led.h
index 0d5a56ebc64..c1fb7f3f23c 100644
--- a/include/status_led.h
+++ b/include/status_led.h
@@ -296,6 +296,25 @@ void status_led_set  (int led, int state);
 
 # define STATUS_LED_BOOT        0               /* LED 0 used for boot status */
 
+/*****  RBC823    ********************************************************/
+#elif defined(CONFIG_RBC823)
+
+# define STATUS_LED_PAR         im_ioport.iop_pcpar
+# define STATUS_LED_DIR         im_ioport.iop_pcdir
+#  undef STATUS_LED_ODR
+# define STATUS_LED_DAT         im_ioport.iop_pcdat
+
+# define STATUS_LED_BIT         0x0002          /* LED 0 is on PC.14 */
+# define STATUS_LED_PERIOD      (CFG_HZ / 2)
+# define STATUS_LED_STATE       STATUS_LED_BLINKING
+# define STATUS_LED_BIT1        0x0004          /* LED 1 is on PC.13 */
+# define STATUS_LED_PERIOD1     (CFG_HZ)
+# define STATUS_LED_STATE1      STATUS_LED_OFF
+
+# define STATUS_LED_ACTIVE      1               /* LED on for bit == 1  */
+
+# define STATUS_LED_BOOT        0               /* LED 0 used for boot status */
+
 /************************************************************************/
 #else
 # error Status LED configuration missing