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authorScott Wood <scottwood@freescale.com>2009-06-24 17:23:49 -0500
committerScott Wood <scottwood@freescale.com>2009-07-07 17:58:10 -0500
commit1dac3a51875967f32641bbc0d26dc382ef02330a (patch)
treeda3189b90533d3a383021a92a91352141e138d36 /nand_spl
parent98713d2663d5d30dde74f48f547114a2bfd9d463 (diff)
nand_spl: Fix cmd_ctrl usage in nand_boot.c.
When adding large page NAND support to this file, I had a misunderstanding about the exact semantics of NAND_CTRL_CHANGE (which isn't documented anywhere I can find) -- it is apparently just a hint to drivers, which aren't required to preserve the old value for subsequent non-"change" invocations. This change makes nand_boot.c no longer assume this. Note that this happened to work by chance with some NAND drivers, which don't preserve the value, but treat 0 equivalently to NAND_CTRL_ALE. I don't have hardware to test this, so any testing is appreciated. Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'nand_spl')
-rw-r--r--nand_spl/nand_boot.c18
1 files changed, 11 insertions, 7 deletions
diff --git a/nand_spl/nand_boot.c b/nand_spl/nand_boot.c
index be2e69c287c..b9fd6f544c9 100644
--- a/nand_spl/nand_boot.c
+++ b/nand_spl/nand_boot.c
@@ -47,11 +47,13 @@ static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8
/* Set ALE and clear CLE to start address cycle */
/* Column address */
this->cmd_ctrl(mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
- this->cmd_ctrl(mtd, page_addr & 0xff, 0); /* A[16:9] */
- this->cmd_ctrl(mtd, (page_addr >> 8) & 0xff, 0); /* A[24:17] */
+ this->cmd_ctrl(mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */
+ this->cmd_ctrl(mtd, (page_addr >> 8) & 0xff,
+ NAND_CTRL_ALE); /* A[24:17] */
#ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE
/* One more address cycle for devices > 32MiB */
- this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f, 0); /* A[28:25] */
+ this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f,
+ NAND_CTRL_ALE); /* A[28:25] */
#endif
/* Latch in address */
this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
@@ -94,13 +96,15 @@ static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8
/* Column address */
this->cmd_ctrl(mtd, offs & 0xff,
NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
- this->cmd_ctrl(mtd, (offs >> 8) & 0xff, 0); /* A[11:9] */
+ this->cmd_ctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
/* Row address */
- this->cmd_ctrl(mtd, (page_addr & 0xff), 0); /* A[19:12] */
- this->cmd_ctrl(mtd, ((page_addr >> 8) & 0xff), 0); /* A[27:20] */
+ this->cmd_ctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
+ this->cmd_ctrl(mtd, ((page_addr >> 8) & 0xff),
+ NAND_CTRL_ALE); /* A[27:20] */
#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
/* One more address cycle for devices > 128MiB */
- this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f, 0); /* A[31:28] */
+ this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f,
+ NAND_CTRL_ALE); /* A[31:28] */
#endif
/* Latch in address */
this->cmd_ctrl(mtd, NAND_CMD_READSTART,