diff options
author | Dave Liu <daveliu@freescale.com> | 2008-12-02 11:48:51 +0800 |
---|---|---|
committer | Scott Wood <scottwood@freescale.com> | 2009-01-23 10:32:50 -0600 |
commit | c70564e6b1bd08f3230182392238907f3531a87e (patch) | |
tree | 08210e54577641c2567a0bcf3ad981855df43dea /nand_spl | |
parent | 50657c273278f74378e1ac39b41d612b92fdffa0 (diff) |
NAND: Fix cache and memory inconsistency issue
We load the secondary stage u-boot image from NAND to
system memory by nand_load, but we did not flush d-cache
to memory, nor invalidate i-cache before we jump to RAM.
When the system has cache enabled and the TLB/page attribute
of system memory is cacheable, it will cause issues.
- 83xx family is using the d-cache lock, so all of d-cache
access is cache-inhibited. so you can't see the issue.
- 85xx family is using d-cache, i-cache enable, partial
cache lock. you will see the issue.
This patch fixes the cache issue.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'nand_spl')
-rw-r--r-- | nand_spl/board/freescale/mpc8313erdb/Makefile | 6 | ||||
-rw-r--r-- | nand_spl/nand_boot_fsl_elbc.c | 5 |
2 files changed, 10 insertions, 1 deletions
diff --git a/nand_spl/board/freescale/mpc8313erdb/Makefile b/nand_spl/board/freescale/mpc8313erdb/Makefile index 3da1b1fffb8..1a8f6ff2c79 100644 --- a/nand_spl/board/freescale/mpc8313erdb/Makefile +++ b/nand_spl/board/freescale/mpc8313erdb/Makefile @@ -34,7 +34,8 @@ AFLAGS += -DCONFIG_NAND_SPL CFLAGS += -DCONFIG_NAND_SPL SOBJS = start.o ticks.o -COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o nand_init.o time.o +COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o nand_init.o \ + time.o cache.o SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) @@ -79,6 +80,9 @@ $(obj)ns16550.c: $(obj)nand_init.c: ln -sf $(SRCTREE)/cpu/mpc83xx/nand_init.c $(obj)nand_init.c +$(obj)cache.c: + ln -sf $(SRCTREE)/lib_ppc/cache.c $(obj)cache.c + $(obj)time.c: ln -sf $(SRCTREE)/lib_ppc/time.c $(obj)time.c diff --git a/nand_spl/nand_boot_fsl_elbc.c b/nand_spl/nand_boot_fsl_elbc.c index 4a961ea7b01..0d0c44e1e36 100644 --- a/nand_spl/nand_boot_fsl_elbc.c +++ b/nand_spl/nand_boot_fsl_elbc.c @@ -143,6 +143,11 @@ void nand_boot(void) * Jump to U-Boot image */ puts("transfering control\n"); + /* + * Clean d-cache and invalidate i-cache, to + * make sure that no stale data is executed. + */ + flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE); uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; uboot(); } |