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authorNaresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>2025-05-05 18:28:51 -0700
committerMichal Simek <michal.simek@amd.com>2025-06-02 09:13:48 +0200
commit85f181b194c7d3810db4a0df8ea2386287b26be0 (patch)
tree5ce3a7f25ea3bb4ff0749b20fb41968738db1dfa /scripts/dtc/pylibfdt/setup.py
parent967eebcd85865b795351bfe4e77399b9f414c6c5 (diff)
drivers: fpga: intel_sdm_mb: Flush cache before FPGA configuration
FPGA configuration encounters failure when the cache is not flushed. Add cache flushing to the memory region that holds the FPGA configuration bitstream. Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com> Link: https://lore.kernel.org/r/20250506012851.30039-1-nareshkumar.ravulapalli@altera.com Signed-off-by: Michal Simek <michal.simek@amd.com>
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