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| author | Eric Nelson <eric@nelint.com> | 2016-10-30 16:33:47 -0700 |
|---|---|---|
| committer | Max Krummenacher <max.krummenacher@toradex.com> | 2018-09-20 17:22:43 +0200 |
| commit | 9cfa6c4bf7755f7dd6aac46d880d5eb1c0eff529 (patch) | |
| tree | 853ad120ba34957cf324d1b6ac77b91622a13b93 /tools/pbl_crc32.c | |
| parent | b8f72d3269ef81c5298dff0e2d4046242eaa1bbb (diff) | |
mx6: ddr: allow 32 cycles for DQS gating calibration
The DDR calibration code is only setting flag DG_CMP_CYC (DQS gating sample
cycle) for the first PHY.
Set the 32-cycle flag for both PHYs and clear when done so the MPDGCTRL0
output value isn't polluted with calibration artifacts.
Signed-off-by: Eric Nelson <eric@nelint.com>
Reviewed-by: Marek Vasut <marex@denx.de>
(cherry picked from commit b33f74ead4dfd1ec0b500dc3d1cfef0e308b45c3)
Diffstat (limited to 'tools/pbl_crc32.c')
0 files changed, 0 insertions, 0 deletions